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Fix a fencepost in the cache flush routines, caused by using the wrong

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condition on a branch (bpl where bhi should have been used).  The error
caused one more line than intended to be flushed, which is particularly
bad if you're doing a dcache-invalidate operation.
This commit is contained in:
thorpej 2002-08-14 22:53:19 +00:00
parent 4bb5ae3d09
commit 8df22142b8
1 changed files with 6 additions and 47 deletions
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53
sys/arch/arm/arm/cpufunc_asm_xscale.S
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@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_xscale.S,v 1.14 2002/08/09 21:51:52 thorpej Exp $ */
/* $NetBSD: cpufunc_asm_xscale.S,v 1.15 2002/08/14 22:53:19 thorpej Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@ -369,7 +369,7 @@ ENTRY(xscale_cache_cleanD_rng)
1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
bhi 1b
CPWAIT(r0)
@ -390,7 +390,7 @@ ENTRY(xscale_cache_purgeID_rng)
mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
bhi 1b
CPWAIT(r0)
@ -410,7 +410,7 @@ ENTRY(xscale_cache_purgeD_rng)
mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
bhi 1b
CPWAIT(r0)
@ -430,7 +430,7 @@ ENTRY(xscale_cache_syncI_rng)
mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
bhi 1b
CPWAIT(r0)
@ -438,30 +438,7 @@ ENTRY(xscale_cache_syncI_rng)
CPWAIT_AND_RETURN(r0)
/* Used in write-through mode. */
ENTRY(xscale_cache_flushID_rng)
cmp r1, #0x4000
bcs _C_LABEL(xscale_cache_flushID)
and r2, r0, #0x1f
add r1, r1, r2
bic r0, r0, #0x1f
1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
/* Used in write-though mode. */
ENTRY(xscale_cache_flushD_rng)
cmp r1, #0x4000
bcs _C_LABEL(xscale_cache_flushD)
and r2, r0, #0x1f
add r1, r1, r2
bic r0, r0, #0x1f
@ -469,25 +446,7 @@ ENTRY(xscale_cache_flushD_rng)
1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
/* Used in write-through mode. */
ENTRY(xscale_cache_flushI_rng)
cmp r1, #0x4000
bcs _C_LABEL(xscale_cache_flushI)
and r2, r0, #0x1f
add r1, r1, r2
bic r0, r0, #0x1f
1: mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
add r0, r0, #32
subs r1, r1, #32
bpl 1b
bhi 1b
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */