deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map). Try to deal with this:
* Group all information about the backend allocator for a pool in a
separate structure. The pool references this structure, rather than
the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
to become available, but will still fail if it cannot callocate KVA
space for the pages. If this happens, carefully drain all pools using
the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
some pages, and use that information to make draining easier and more
efficient.
* Get rid of PR_URGENT. There was only one use of it, and it could be
dealt with by the caller.
From art@openbsd.org.
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
and support routines for the Broadcom CFE (Common Firmware Environment).
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
- Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
- Use a table-driven CPU detection algorithm instead of multiple
case statements.
- Add MIPS32/64 feature detection using the architected CP0 registers
(from Broadcom Corp).
- Call MD mips_machdep_cache_config() function if
__HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
L2 cache on some ports.
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.
simonb