8e85aac1ce
move pci/pci_machdep.h to include/pci_machdep.h. (can't do it via
...
repository copy because alpha already had an include/pci_machdep.h in
the attic.)
1999-03-19 03:40:46 +00:00
02a2323b29
ovbcopy->memmove
1999-03-12 22:56:21 +00:00
a92175a153
nuke ovbcopy
1999-03-12 22:54:58 +00:00
1611b4799f
Gronk. DWLPX comment in a MCPCIA file.
1999-02-17 03:17:17 +00:00
02d221f94a
Fix printf format problems on Alpha.
1999-02-12 06:25:13 +00:00
db631acd8a
Fix printf format problems on Alpha.
1999-02-12 06:07:52 +00:00
d963824bdc
#include <machine/intrcnt.h>
1998-11-19 02:35:39 +00:00
bc9cb58205
Fix interrupt map for baseboard bridge.
1998-11-19 02:33:37 +00:00
82b48f66b6
If NSIO not defined, compile errors.
1998-10-31 23:51:05 +00:00
e43333b7e7
Move if_ade* from alpha/pci/ to alpha/a12/
1998-09-24 05:36:05 +00:00
86f044d10e
Track changes elsewhere in the PCI interface.
1998-09-23 21:20:55 +00:00
55714d5b34
Update for vm_offset_t, vaddr_t sweep.
1998-09-23 21:17:17 +00:00
1df7dffd26
Nuke an unused variable.
1998-09-01 21:28:04 +00:00
d58173741d
kill the last remnants of __BROKEN_INDIRECT_CONFIG. (only the pica port
...
used it, and it's non-working and apparently slated for replacement.)
1998-08-31 22:28:04 +00:00
3110e22945
use current bus_space interface names for barrier ops
1998-08-30 23:29:10 +00:00
c529c40718
Normalize the copyright notice on this file.
1998-08-15 20:42:25 +00:00
d5df55112a
vm_offset_t -> {paddr_t,vaddr_t}, vm_size_t -> vsize_t
1998-08-14 16:50:00 +00:00
8eeb95fce4
Implement pci_intr_disestablish().
1998-08-01 20:25:12 +00:00
92fa3a68ad
In sio_intr_disestablish, also make sure that IRQs 0, 1, 8, and 13
...
default to edge-triggered, just like in the setup.
1998-08-01 19:38:29 +00:00
0b60fda7c8
Implement sio_intr_disestablish(), and ensure that an initially-enabled
...
interrupt is never disabled and an initially-level-triggered interrupt
never becomes untyped.
1998-08-01 18:54:21 +00:00
f948e430bb
Provide a hook for bypassing space accounting, needed to support ISA PnP
...
for now.
1998-07-31 04:37:02 +00:00
eb32016a95
Split up using BWX for PCI config and bus access. Default to using BWX for
...
the former, but not the latter. Hopefully, this will address some problems
people have been experiencing w/ some devices on Pyxis systems when BWX
is used for bus access. (If it's not used for PCI config access, we can
get fatal machine checks while probing behind PCI-PCI bridges!!)
1998-07-29 01:28:44 +00:00
a5e7f763c2
minor tweak, and example of how to do error insertion
1998-07-08 00:58:09 +00:00
275fb86f8d
add some error handling definitions
1998-07-08 00:40:18 +00:00
de83dce0de
On second thought, call that like the rest of the shared intr functions.
1998-07-07 22:24:38 +00:00
1ddd528346
Fix typi.
1998-07-07 22:02:57 +00:00
e82fc7d3cd
The Pyxis core logic in the 164SX and 164LX seems to have problems with
...
stray interrupts. Do what Digital UNIX (formerly DEC OSF/1) does; just
ignore strays.
1998-07-07 21:49:47 +00:00
ca73507d0b
The Pyxis core logic in the Miata seems to have problems with stray interrupts.
...
Do what Digital UNIX (formerly DEC OSF/1) does; just ignore strays.
1998-07-07 21:47:49 +00:00
be83de18fd
Use ALPHA_SHARED_INTR_DISABLE() to test if a shared interrupt should
...
be disabled after a stray.
1998-07-07 21:44:57 +00:00
011f2bda08
defopt NS, NSIP.
1998-07-05 06:49:00 +00:00
3751946b97
defopt INET, NETATALK.
1998-07-05 00:51:04 +00:00
02b767eee5
Take a stab at EB66 support. An EB66 is basically an EB64+ with a
...
21066 LCA instead of a 21064 + APECS.
1998-06-27 10:10:51 +00:00
dff0b84aba
Oops, forgot option header.
1998-06-27 08:59:03 +00:00
50604bf85b
Kill off some EVCNT_COUNTERS calls, since [A] it has to be rewritten anyway
...
before it can be useful, and [B] #ifdefs do not belong at every call site,
a common API should be defined and the implementations conditionalized, not
the calls. Duhh.
Also, remove the initial XXX mystery_icu debugging code.
1998-06-26 21:59:46 +00:00
a0f70c580c
New platforms: Mikasa and Mikasa/Pinnacle, aka Pinkasa.
...
Like the 1000A, the AlphaServer 1000 has a daughtercard assembly that
integrates the CPU and core logic, so these can be ev4/apecs or ev5/cia.
New systype, and, sigh, another way of doing interrupts and another
mystery icu.
Kill off some EVCNT_COUNTERS calls, since [A] it has to be rewritten anyway
before it can be useful, and [B] #ifdefs do not belong at every call site,
a common API should be defined and the implementations conditionalized, not
all the calls. Duhh.
1998-06-26 21:45:56 +00:00
78d7f07efd
Very preliminary support for the Tadpole/DEC AlphaBook. These are basically
...
AXPpci33 machines + power management and a Cirrus PCI-PCMCIA controller.
There is currently no support for the power management facilities, and
the PCI-PCMCIA controller driver needs some work, but this should boot
and run from disk.
1998-06-26 05:42:34 +00:00
63e87b1a8e
New platforms: Noritake, Pintake, and Corelle. Sometimes these are ev4/apecs,
...
sometimes they are ev5/cia.
1998-06-24 01:38:59 +00:00
49d5ae18ba
Call pci_1000a_pickintr() like on other platforms, but for 1000a expand
...
the iot, memt, and pc in the call so that pci_1000a_pickintr() (and the
other routines in that module) do not need to be aware of the core logic
type just to pass down memory and I/O space tags or to call the decompose
function.
1998-06-24 01:32:06 +00:00
e2ebc10c2d
Duuuh! Align the SGMAP page tables to 32K, not 32M.
1998-06-23 02:31:05 +00:00
02182100df
Use config_defer().
1998-06-09 18:49:33 +00:00
8dedb90f13
The ISA chipset must persist; it's required after autoconfig time.
1998-06-08 23:49:05 +00:00
14df007174
Oops, don't forget to fill in *addrp.
1998-06-07 00:29:29 +00:00
0890af5ca8
Only disable an interrupt line after MAXSTRAYs if there is no handler
...
attached; we get stray interrupts on PCI devices sometimes, for some
unknown reason. (Similar problem exists on the 164SX, which also has
a Pyxis.)
1998-06-06 23:29:23 +00:00
331a7f56c1
Remove some debugging code no longer relevant now that we have DMA
...
window chaining.
1998-06-06 23:11:52 +00:00
eabad6b572
Implement bus_space_{alloc,free}() for swiz PCI I/O space.
1998-06-06 22:44:46 +00:00
7a6d646c9b
Implement bus_space_{alloc,free}() for BWX bus space.
1998-06-06 22:28:16 +00:00
04ba8480ae
Use REGVAL64() to frob the Pyxis interrupt mask register.
1998-06-06 20:42:36 +00:00
098dd211c7
Define a REGVAL64() for some Pyxis registers.
1998-06-06 20:40:14 +00:00
85d08836f1
- Don't call *_dma_init() twice; there's no need to. Just do it in *attach().
...
- Display Pyxis revision properly.
1998-06-06 01:33:44 +00:00
c0fa3c6ac4
Don't call *_dma_init() twice; there's no need to. Just do it in *attach().
1998-06-06 01:33:23 +00:00
9331237596
Oops, turn off some debugging printfs.
1998-06-05 21:47:14 +00:00
bf8523f4e4
- Egads! There are Pyxis "Pass 1" chips that do not have the DMA bug!
...
Use the check recommended by the Digital Workstation engineers; look
for Miata 1 systems (i.e. with Intel SIO). From Andrew Gallatin.
- Update copyright (Pyxis and BWX).
1998-06-05 19:25:19 +00:00
f251e3372d
Don't attempt to map the PCI IDE interrupt at bus 0 device 11 on the
...
AlphaPC 164 and AlphaPC 164LX - these are wired to compatibility mode.
1998-06-05 19:15:41 +00:00
1aa688234e
Miata 1 has an Intel SIO at bus 0 device 7 and a CMD PCI IDE at bus 0
...
device 4. Miata 1.5 and Miata 2 have a Cypress at device 7 and PCI IDE
at functions 1 and 2 of the Cypress (like the PC164SX). These on-board
PCI IDE controllers are wired to compatibility mode, so don't bother
trying to map the interrupt.
1998-06-05 19:04:51 +00:00
c072110af0
Actually, I did use a few of them on this file (I wasn't clear enough
...
in my mail to Ross, I guess...)
1998-06-05 17:42:53 +00:00
bb362059ac
On Pass 1 Pyxis, disable PCI Read Prefetching, and warn the user about
...
the DMA bug that exists on this Pyxis revision.
1998-06-05 17:24:11 +00:00
29977868a7
What was called CNFG in ALCOR and ALCOR2 is actually called PYXIS_CTRL1
...
in Pyxis. Add a comment to this fact.
1998-06-05 17:22:34 +00:00
73e5032ac9
Define the Pyxis-specific bits in the CIA_CSR_REV register (ID mask, and
...
the ID for the 21174).
1998-06-05 17:16:31 +00:00
5790ee09ee
Revert...Jason didn't use Andrew's diffs.
1998-06-05 15:28:40 +00:00
8f455480ef
Tweak the copyrights a little bit. pci_550.h gets a TNF copyright, not
...
CMU, and pci_550.c keeps TNF but gets "Andrew Gallatin and Jason R. Thorpe".
1998-06-05 03:34:27 +00:00
cf914cac00
oops, read CNFG on all Pyxis revs.
1998-06-05 02:15:38 +00:00
cbaedc8675
Support for the Digital Personal Workstation [456]xx, a.k.a. Miata (systype
...
DEC_550). Mostly cloned from the EB164 systype, with some modifications
from myself, and a few more from Andrew Gellatin.
1998-06-05 02:13:41 +00:00
3cfb38c5d1
Define the Pyxis interrupt request register.
1998-06-05 00:53:02 +00:00
3249813e11
For whatever reason, the firmware seems to enable PCI loopback mode if it
...
also enables BWX. Make sure it's enabled if we have an old, buggy firmware
rev.
1998-06-04 22:58:33 +00:00
d4d49905dd
Add support for using BWX for PCI config space and PCI i/o and mem space
...
on the ALCOR2 and Pyxis. BWX is enabled iff:
- It hasn't been disabled by the user (patch `cia_use_bwx' or build cia.o
with the option "CIA_USE_BWX=0"),
- it's enabled in CIA_CSR_CNFG,
- we are running on an EV5-family processor,
- BWX is in the processor's capabilities mask.
1998-06-04 21:34:45 +00:00
616125f8d1
Deal with a hardware bug in Pass 1 and Pass 2 Pyxis chips. Basically,
...
the scatter/gather TLB cannot be invalidated on these chips. So, to
work around this, we configure the otherwise unsed DMA Window 2 as a
2M SGMAP window at 128M, point all of its page table entries at the
DMA spill page, and, when the TLB is to be invalidated, put the PCI bus
into loopback mode, and create a target hit on Window 2 every 64k for
the number of TLB entries (plus a few ... it seems to not work unless
we read a few extra times), forcing out old TLB entries to make room for
the new, dummy target hits.
1998-06-04 18:11:23 +00:00
6dc28f5445
CIA and Pyxis have 8 scatter/gather TLB entries.
1998-06-04 01:18:22 +00:00
32fef69ef7
Define the CIA control register.
1998-06-04 01:04:11 +00:00
d94f02f9fd
Ok, now we _REALLY_ have Pyxis recognition correct. There are two systypes
...
that can have Pyxis: EB164 (AlphaPC164LX and AlphaPC164SX) and DEC_550 (Miata),
and these systypes/variations _always_ have Pyxis.
1998-06-03 23:16:55 +00:00
15c52040a5
Define the ALT_MEM big in the CIA revision register.
1998-06-03 22:19:08 +00:00
d6041754c2
Allow the DMA tag to specify a boundary contraint. If the device has a
...
more strict boundary, the map will use it, otherwise the map will inherit
the tag's, unless the tag's constraint is 0 (no boundary constraint).
1998-06-03 18:25:53 +00:00
0c05b92da1
pull in new PC display headers
1998-05-28 16:59:31 +00:00
66e7b8998f
Only disable stray interrupts if there is no interrupt handler attached
1998-05-24 19:09:57 +00:00
30e2441b99
Prototype sio_intr_alloc().
1998-05-23 21:36:33 +00:00
9c2e213217
Add sio_intr_alloc (copied from i386's isa_intr_alloc) for PCMCIA.
1998-05-23 18:35:56 +00:00
0cb3acc9ae
Correct a small, but fatal, typo.
1998-05-21 23:38:04 +00:00
d19fbe1196
Garbage-collect the old confargs stuff that was used in the Early Days.
...
It isn't really appropriate anymore. Replace it with a real mainbus
attach args structure.
1998-05-14 00:01:30 +00:00
49aa171ab9
Add support for chaining DMA windows together, for falling back on
...
SGMAPs if a direct-mapped window fails.
1998-05-13 21:21:16 +00:00
6172f5a0ac
Use flags instead of a bunch of booleans. Add a "use bwx" flag.
1998-05-12 19:07:21 +00:00
0b64ea0879
Gah, typo.
1998-05-12 18:45:04 +00:00
86ee1b1000
Oops, and the writes, too.
1998-05-12 18:44:32 +00:00
cc45d00d3c
Clean up the code that puts the PCI controller into config mode 1; no
...
functional difference.
1998-05-12 18:40:44 +00:00
34bbe5cd80
Rework ALCOR/ALCOR2/Pyxis recognition Yet Again. (Actually, just the
...
way it's displayed, and mask off the revision once we've determined
which chip we're talking to.)
1998-05-11 23:56:16 +00:00
0624060713
Rework PCI interrupt mapping on the EB164 systype. Rather than computing
...
interrupt routing directly, use the interrupt routing information provided
in the PCI "line" register. The previous scheme did not work properly on
AlphaPC 164SXs. Also, be silent about the fact that 0/8/x does not
have its interrupt mapped; this is to be expected on the 164SX (this is
the Cypress PCI-ISA bridge, which has IDE wired to compat mode on functions
1 and 2; the 164SX does _not_ have PCI IDE on device 11 like other AlphaPCs).
1998-05-11 23:36:46 +00:00
4665241bf8
Simplify the direct-mapped DMA case somewhat by adding a window base
...
member to the DMA tag, and calling the direct-mapped back-ends directly,
rather than through chipset-specific front-ends which pass the window
base as an additional argument.
1998-05-07 20:09:37 +00:00
294015435b
remove the unneccessary alpha_mbs and slight cleanup
1998-05-05 22:01:54 +00:00
742983f1eb
make it impossible to compile w/o SIO (you cannot have a console otherwise
1998-05-05 22:01:31 +00:00
de4d1c62af
pretty much redo interrupt code- now handles shared interrupts and solves the buspin int problem
1998-04-30 04:31:19 +00:00
e3904356a4
do some mbs before a config read/write
1998-04-30 04:25:22 +00:00
9e97d1cc17
Define Pyxis Interrupt Mask and General Purpose Output registers.
1998-04-29 03:09:26 +00:00
28b467b65b
Add support for the DEC EB64+.
1998-04-29 00:24:59 +00:00
4ccb48a525
Try (again) to get the chip number right for Alcor and Pyxis, using the
...
following (iffy) hueristic:
CIA revision 1 -> 21171
CIA revision 2 -> 21172
CIA revision > 2 -> 21174
1998-04-28 18:11:35 +00:00
b6eff278f2
Fix some whitespace lossage.
1998-04-25 00:12:44 +00:00
660e718e2e
Drivers for PC-like console devices are MI now.
1998-04-24 20:05:54 +00:00
6cd64be0b6
fix minor typo
1998-04-24 01:25:18 +00:00
4fc79b8fd3
First cut at PCI IDE compat interrupt support for the EB164 systype.
...
PCI IDE is found on the AlphaPC 164SX's Cypress PCI-ISA bridge.
1998-04-18 01:18:37 +00:00
574b87a792
Initialize the PCI IDE compat interrupt PCI method to NULL; PCI IDE
...
compat interrupts are not currently supported on these platforms.
1998-04-18 01:12:23 +00:00
78c7ebb2d0
Add a second Alpha-specific pci_chipset_tag_t method for establishing
...
PCI IDE compat interrupts. Note that this function is optional, and
platform-specific code may initialize the pointer to NULL.
1998-04-18 01:10:54 +00:00
a5f006fb5f
Fix a typo.
1998-04-18 01:09:20 +00:00
783382095c
Machine-dependent bits for PCI IDE. This redirects PCI IDE compat interrupt
...
goop to the appropriate platform-dependent code.
1998-04-18 01:08:52 +00:00
815703e5ec
Make function names in printfs and panics consistent.
1998-04-16 19:50:55 +00:00
a048ee73ca
Fix a whitespace botch.
1998-04-16 19:40:56 +00:00
2615a1d8d3
Allow device 8 (the SIO) to have its interrupt mapped; there might be
...
a PCI IDE controller on one of the PCI-ISA bridge's functions (e.g.
AlphaPC 164SX).
1998-04-16 19:24:24 +00:00
584f3e8aa0
Adapt PCI console selection to new mi drivers.
1998-04-15 20:46:34 +00:00
6cc22e724e
Hmmm- how did that happen- I missed a merge
1998-04-15 01:18:17 +00:00
aed073a77f
add Alpha 4100 support
1998-04-15 00:50:14 +00:00
0ba76b38c8
spurious interrupt notification and finally adding vmstat -i support
1998-04-15 00:49:58 +00:00
0229740b5e
removal of unneeded define
1998-04-15 00:49:17 +00:00
5f59df9630
oops on byte enables for TurboLaser systems
1998-04-15 00:48:58 +00:00
164f56220e
Add support for the Cypress CY82C693 PCI-ISA bridge. This bridge is more or
...
less like an Intel SIO except that the ELCR registers are accessed differently
than on the Intel SIO.
XXX This code needs to be split up into bridge front-end and PIC back-end
XXX pieces.
1998-04-14 22:31:17 +00:00
4c01c3c48e
Pass the pci_chipset_tag_t to sio_intr_setup(). XXX This code should be
...
rearranged so that other non-PCI-but-in-all-other-ways-ISA-PIC-like
devices can share code.
1998-04-14 22:20:59 +00:00
e40e2ff2d0
A little buglet: softc for pceb is same as sio- so declare it as such.
...
By not doing so, a very obscure bug followed where the config search
stuff stopped at the bridge (pceb) and didn't even call match for the
two Qlogic ISP cards that followed.
1998-04-12 08:32:19 +00:00
ce4810822b
Add autoconfiguration support for the Cypress 82C693 PCI-ISA bridge,
...
found on AlphaPC164SX boards.
Partially from Anders Magnusson <ragge@ludd.luth.se>.
1998-03-28 06:58:43 +00:00
040f7cbc70
Remove references to pmap.old.h - It should have just been pmap.h, but
...
that isn't necessary, either, since <vm/vm.h> is already included.
1998-03-26 18:17:13 +00:00
8e5970917e
Redo it slightly so that S/G now appears to work a bit better. This
...
version has 2GB direct map starting at 2GB, and either 256MB or 1GB
S/G starting at 1MB. I've done *some* testing on this, but I'm not
quite happy with it yet.
1998-03-23 07:42:40 +00:00
88c34f6f5f
Spaicing for 32 bit ptes (dwlpx only, really) is 0x20, not 1
1998-03-23 07:09:12 +00:00
66194d05bc
Do a more complete job of figuring out what kind of DWLP? we have- figure
...
out how much s/g ram is available. Can't really use the 128K entry S/G
ram yet- but I'll fix that later. More importantly, add in a dwlpx_iointr
handler that will try and figure out what the DWLPX error is and at
least print out what is happening- I actually found it useful in S/G
entry debugging as it could tell me that I had some bad S/G entries.
1998-03-23 06:38:10 +00:00
51ba315ba2
Slightly restructure interrupt handling to accomodate the addition
...
of a dwlpx_iointr vector.
1998-03-23 06:32:39 +00:00
7c83bc0da6
Prepare for handling multisized S/G maps. Specify dwlpx_iointr function.
1998-03-23 06:31:54 +00:00
34f87569b9
add some error defintions
1998-03-21 22:02:42 +00:00
ff94450f84
Use the more consistent register field names & add ctags(1) keys.
1998-03-02 07:07:41 +00:00
6e6f663204
Rewrite of interrupt dispatch logic. Add ctags(1) keys for *a12*.h files.
1998-03-02 07:03:20 +00:00
13aeff8570
Fix attachment message.
1998-03-02 06:59:38 +00:00
1ada245647
Support attachment of xb and a12dc, define most of the remaining
...
core logic register fields.
1998-03-02 06:56:16 +00:00
469f9b6126
Clean up attachment code and prototypes.
1998-03-02 06:53:34 +00:00
58509e699f
Add support for UVM.
1998-02-24 07:38:01 +00:00
314f40f8d8
We can't count on the CIA revision register telling us if we're a 21171
...
or 21172, so make the chip/revsion output a little more sane.
1998-02-12 20:43:45 +00:00
612aea038c
Use the common _bus_dmamap_sync() as the _dmamap_sync method in the
...
bus_dma_tag_t.
1998-02-04 07:37:28 +00:00
6270ed1711
Add the A12 fast ethernet controller, an if_de.c hacked (prior to
...
bus_dma's appearance in the tree) to support sram bounce buffers.
When a busified if_de.c appears, this module can join awd.c at the
end of that long walk on a short pier.
1998-01-31 01:43:40 +00:00
12f93343cd
Add basic platform support for NetBSD on the Avalon A12. I'm running this
...
CVS commit on one right now...
1998-01-29 21:42:50 +00:00
8df306036a
Initialize s/g DMA registers in the same order as the CIA chipset's:
...
(1) window base
(2) window mask
(3) translation base
1998-01-17 22:46:55 +00:00
3366b987d0
Put SGMAP-related stuff in the DMA map structure directly, rather than
...
indirecting through a pointer.
1998-01-17 21:53:52 +00:00
63db8935a6
Fix initialization of DMA window 0:
...
- Make sure the page table is aligned to at least 32k.
- Don't consider the MEMCS signal when checking for a window hit.
1998-01-17 03:43:59 +00:00
9554b5a243
Update for "minptalign" argument to alpha_sgmap_init().
1998-01-17 03:40:32 +00:00
399f3639cf
Don't assume that we'll be using direct-mapped DMA for PCI.
1998-01-17 03:39:51 +00:00
5419debcb7
Adjust for config changes.
1998-01-12 10:21:02 +00:00
023044a749
Clean up printing of chipset revision/capabilities.
1997-10-27 01:08:42 +00:00
611012d836
Make the copy_region methods do overlapping copies properly. Fixes
...
port-alpha/4216 (Chris Demetriou).
1997-10-25 01:21:57 +00:00
c44bfc9eae
Make compile without DIAGNOSTIC set.
1997-10-14 06:22:02 +00:00
0c2efd7025
Add a "scrollskip" member to wscons_emulfuncs (XXX even though it's not
...
a function) which specifies how many lines will be skipped when scrolling
up when the bottom of the screen is reached. Dumb framebuffers skip 10
lines (as before) because the copies are s ... l ... o ... w, but it's
silly to skip 10 lines on VGA, since the copies are much faster, so we
only skip one in that case.
1997-09-25 01:31:53 +00:00
15e10104d5
Define the BWX-capable regions of the CIA chipset's address space (mem,
...
i/o, pci config space mode 0, pci config space mode 1) and the CIA
REV and CNFG CSRs.
1997-09-17 01:35:34 +00:00
879c4c5cf4
If the CIA revision is >= 2, read the CIA configuration register, and
...
remember its contents. Print out a bit of information about the chip,
including whether or not it supports the EV56 BWX instructions.
1997-09-17 01:34:18 +00:00
37b8edbeac
In addition to MAS_ABT, check TAR_ABT when doing configuration space
...
reads. This is necessary because of newer AlphaStation firmware doing
the Wrong Thing with target aborts behind PCI-PCI bridges, much like they
do the Wrong Thing with master aborts. Reported by Matthias Drochner.
1997-09-15 23:31:15 +00:00
12f6c5aba1
Make sure to clear MAS_ABT if we received one.
1997-09-15 23:01:29 +00:00
3c3c6a3b31
Use the symbolic name for "received master abort".
1997-09-15 22:35:54 +00:00
8ff22715e8
Define bits in the CIA_ERR register.
1997-09-15 22:34:38 +00:00
f784e8dc15
Apparently, new AlphaStation 500/600 firmware has the same problem with
...
PCI master aborts as eb164 firmware, so use the same workaround mechanism
on all system types (clear error register's master abort bit, and check
it after accessing configuration space), not just eb164's.
This also fixes a bug on eb164's - when making the Alpha port compile
again, I made an error that caused this to not be used on eb164 systems,
either. Thanks to Matt Jacob for pointing out this goof.
1997-09-13 05:58:07 +00:00
ed2ec4869c
Update for Chris Demetriou's changes made to the bus.h interface:
...
- bus_space_copy -> bus_space_copy_region (for consistency)
- "cacheable" argument becomes a "flags" argument instead, with
BUS_SPACE_MAP_CACHEABLE and BUS_SPACE_MAP_LINEAR flags currently
defined.
1997-09-06 05:44:07 +00:00
1aa35e94d4
s/BUS_BARRIER/BUS_SPACE_BARRIER/g
1997-09-06 05:21:14 +00:00
2ecccdc05f
Define Status 0 and Status 1 registers.
1997-09-05 02:14:31 +00:00
cgd