Deal with a hardware bug in Pass 1 and Pass 2 Pyxis chips. Basically,
the scatter/gather TLB cannot be invalidated on these chips. So, to work around this, we configure the otherwise unsed DMA Window 2 as a 2M SGMAP window at 128M, point all of its page table entries at the DMA spill page, and, when the TLB is to be invalidated, put the PCI bus into loopback mode, and create a target hit on Window 2 every 64k for the number of TLB entries (plus a few ... it seems to not work unless we read a few extra times), forcing out old TLB entries to make room for the new, dummy target hits.
This commit is contained in:
thorpej
parent
c6d1832868
commit
616125f8d1
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@ -1,4 +1,4 @@
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/* $NetBSD: cia_dma.c,v 1.9 1998/06/03 18:25:54 thorpej Exp $ */
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/* $NetBSD: cia_dma.c,v 1.10 1998/06/04 18:11:23 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -39,7 +39,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: cia_dma.c,v 1.9 1998/06/03 18:25:54 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cia_dma.c,v 1.10 1998/06/04 18:11:23 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -89,15 +89,16 @@ void cia_bus_dmamap_unload_sgmap __P((bus_dma_tag_t, bus_dmamap_t));
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#define CIA_SGMAP_MAPPED_BASE (8*1024*1024)
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#define CIA_SGMAP_MAPPED_SIZE (8*1024*1024)
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/*
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* Macro to flush CIA scatter/gather TLB.
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*/
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#define CIA_TLB_INVALIDATE() \
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do { \
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alpha_mb(); \
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REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL; \
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alpha_mb(); \
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} while (0)
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void cia_tlb_invalidate __P((void));
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void cia_broken_pyxis_tlb_invalidate __P((void));
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void (*cia_tlb_invalidate_fn) __P((void));
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#define CIA_TLB_INVALIDATE() (*cia_tlb_invalidate_fn)()
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struct alpha_sgmap cia_pyxis_bug_sgmap;
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#define CIA_PYXIS_BUG_BASE (1*128*1024)
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#define CIA_PYXIS_BUG_SIZE (2*1024*1024)
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void
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cia_dma_init(ccp)
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@ -191,6 +192,55 @@ cia_dma_init(ccp)
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REGVAL(CIA_PCI_T0BASE) = tbase;
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alpha_mb();
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/*
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* Pass 1 and 2 (i.e. revision <= 1) of the Pyxis have a
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* broken scatter/gather TLB; it cannot be invalidated. To
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* work around this problem, we configure window 2 as an SG
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* 2M window at 128M, which we use in DMA loopback mode to
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* read a spill page. This works by causing TLB misses,
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* causing the old entries to be purged to make room for
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* the new entries coming in for the spill page.
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*/
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if ((ccp->cc_flags & CCF_ISPYXIS) != 0 && ccp->cc_rev <= 1) {
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u_int64_t *page_table;
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int i;
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cia_tlb_invalidate_fn =
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cia_broken_pyxis_tlb_invalidate;
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alpha_sgmap_init(t, &cia_pyxis_bug_sgmap,
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"pyxis_bug_sgmap", CIA_PYXIS_BUG_BASE, 0,
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CIA_PYXIS_BUG_SIZE, sizeof(u_int64_t), NULL,
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(32*1024*1024));
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REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE |
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CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN;
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alpha_mb();
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REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M;
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alpha_mb();
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tbase = cia_pyxis_bug_sgmap.aps_ptpa >>
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CIA_PCI_TnBASE_SHIFT;
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if ((tbase & CIA_PCI_TnBASE_MASK) != tbase)
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panic("cia_dma_init: bad page table address");
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REGVAL(CIA_PCI_T2BASE) = tbase;
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alpha_mb();
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/*
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* Initialize the page table to point at the spill
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* page. Leave the last entry invalid.
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*/
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pci_sgmap_pte64_init_spill_page_pte();
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for (i = 0, page_table = cia_pyxis_bug_sgmap.aps_pt;
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i < (CIA_PYXIS_BUG_SIZE / PAGE_SIZE) - 1; i++) {
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page_table[i] =
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pci_sgmap_pte64_prefetch_spill_page_pte;
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}
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alpha_mb();
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} else
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cia_tlb_invalidate_fn = cia_tlb_invalidate;
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CIA_TLB_INVALIDATE();
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}
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@ -388,3 +438,59 @@ cia_bus_dmamap_unload_sgmap(t, map)
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*/
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_bus_dmamap_unload(t, map);
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}
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/*
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* Flush the CIA scatter/gather TLB.
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*/
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void
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cia_tlb_invalidate()
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{
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alpha_mb();
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REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL;
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alpha_mb();
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}
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/*
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* Flush the scatter/gather TLB on broken Pyxis chips.
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*/
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void
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cia_broken_pyxis_tlb_invalidate()
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{
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volatile u_int64_t dummy;
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u_int32_t ctrl;
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int i, s;
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s = splhigh();
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/*
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* Put the Pyxis into PCI loopback mode.
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*/
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alpha_mb();
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ctrl = REGVAL(CIA_CSR_CTRL);
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REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
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alpha_mb();
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/*
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* Now, read from PCI dense memory space at offset 128M (our
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* target window base), skipping 64k on each read. This forces
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* S/G TLB misses.
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*
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* XXX Looks like the TLB entries are `not quite LRU'. We need
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* XXX to read more times than there are actual tags!
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*/
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for (i = 0; i < CIA_TLB_NTAGS + 4; i++) {
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dummy = *((volatile u_int64_t *)
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ALPHA_PHYS_TO_K0SEG(CIA_PCI_DENSE + CIA_PYXIS_BUG_BASE +
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(i * 65536)));
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}
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/*
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* Restore normal PCI operation.
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*/
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alpha_mb();
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REGVAL(CIA_CSR_CTRL) = ctrl;
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alpha_mb();
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splx(s);
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}
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