Define Status 0 and Status 1 registers.
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/* $NetBSD: lcareg.h,v 1.7 1997/06/06 23:54:31 thorpej Exp $ */
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/* $NetBSD: lcareg.h,v 1.8 1997/09/05 02:14:31 thorpej Exp $ */
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/*
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* Copyright (c) 1995 Carnegie-Mellon University.
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@ -48,8 +48,19 @@
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#define IOC_HAE_RSVSD 0xffffffff07ffffffUL
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#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */
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#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */
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#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */
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#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */
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#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */
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#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */
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#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */
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#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */
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#define IOC_STAT0_CODESHIFT 8
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#define IOC_STAT0_P_NBR 0x00000000ffffe000UL /* page number mask */
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#define LCA_IOC_STAT1 (LCA_IOC_BASE + 0x060) /* Status 1 */
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#define IOC_STAT1_ADDR 0x00000000ffffffffUL /* PCI address mask */
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#define LCA_IOC_TBIA (LCA_IOC_BASE + 0x080) /* TLB Invalidate All */
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#define LCA_IOC_TB_ENA (LCA_IOC_BASE + 0x0a0) /* TLB Enable */
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