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Define the Pyxis interrupt request register.

This commit is contained in:
thorpej 1998-06-05 00:53:02 +00:00
parent 3249813e11
commit 3cfb38c5d1
1 changed files with 2 additions and 1 deletions
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3
sys/arch/alpha/pci/ciareg.h
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@ -1,4 +1,4 @@
/* $NetBSD: ciareg.h,v 1.18 1998/06/04 01:18:22 thorpej Exp $ */
/* $NetBSD: ciareg.h,v 1.19 1998/06/05 00:53:02 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
@ -71,6 +71,7 @@
#define CIA_PCI_W3MASK 0x8760000740UL
#define CIA_PCI_T3BASE 0x8760000780UL
#define PYXIS_INT_REQ 0x87a0000000UL
#define PYXIS_INT_MASK 0x87a0000040UL
#define PYXIS_GPO 0x87a0000180UL