Do a more complete job of figuring out what kind of DWLP? we have- figure
out how much s/g ram is available. Can't really use the 128K entry S/G ram yet- but I'll fix that later. More importantly, add in a dwlpx_iointr handler that will try and figure out what the DWLPX error is and at least print out what is happening- I actually found it useful in S/G entry debugging as it could tell me that I had some bad S/G entries.
This commit is contained in:
mjacob
parent
51ba315ba2
commit
66194d05bc
@ -1,4 +1,4 @@
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/* $NetBSD: dwlpx.c,v 1.13 1998/01/12 10:21:12 thorpej Exp $ */
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/* $NetBSD: dwlpx.c,v 1.14 1998/03/23 06:38:10 mjacob Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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@ -32,7 +32,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.13 1998/01/12 10:21:12 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.14 1998/03/23 06:38:10 mjacob Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -53,10 +53,14 @@ __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.13 1998/01/12 10:21:12 thorpej Exp $");
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#include <alpha/include/pmap.old.h>
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#define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
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#define DWLPX_SYSBASE(sc) \
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((((unsigned long)((sc)->dwlpx_node - 4)) << 36) | \
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(((unsigned long) (sc)->dwlpx_hosenum) << 34) | \
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(1LL << 39))
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static int dwlpxmatch __P((struct device *, struct cfdata *, void *));
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static void dwlpxattach __P((struct device *, struct device *, void *));
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struct cfattach dwlpx_ca = {
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sizeof(struct dwlpx_softc), dwlpxmatch, dwlpxattach
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};
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@ -64,6 +68,7 @@ struct cfattach dwlpx_ca = {
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extern struct cfdriver dwlpx_cd;
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static int dwlpxprint __P((void *, const char *));
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static struct dwlpx_softc *dwlps[DWLPX_NIONODE][DWLPX_NHOSE];
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static int
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dwlpxprint(aux, pnp)
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@ -107,31 +112,28 @@ dwlpxattach(parent, self, aux)
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sc->dwlpx_node = ka->ka_node;
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sc->dwlpx_dtype = ka->ka_dtype;
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sc->dwlpx_hosenum = ka->ka_hosenum;
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/*
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* On reads, you get a fault if you read a nonexisted HPC.
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* The internal KFTIA hose (hose 0) has only 2 HPCs.
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*/
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sc->dwlpx_nhpc = NHPC;
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if (sc->dwlpx_hosenum == 0) {
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if (TLDEV_DTYPE(sc->dwlpx_dtype) == TLDEV_DTYPE_KFTIA) {
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sc->dwlpx_nhpc = NHPC - 1;
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}
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}
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dwlps[sc->dwlpx_node - 4][sc->dwlpx_hosenum] = sc;
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dwlpx_init(sc);
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/* XXX Need to detect DWLPA vs. DWLPB here. */
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pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
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printf(": PCIA rev. %d, STD I/O %spresent\n",
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printf(": PCIA rev. %d, STD I/O %spresent, %s DMA maps.\n",
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(pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK,
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(pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "");
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(pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "",
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#ifdef MSS3_DEBUG_SG
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(sc->dwlpx_sgmapsz == DWLPX_SG128K)? "128K S/G" : "32K S/G");
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#else
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(physmem <= btoc(2048LL << 20LL))? "Direct" :
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(sc->dwlpx_sgmapsz == DWLPX_SG128K)? "128K S/G" : "32K S/G");
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#endif
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#if 0
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#if 0
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{
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int hpc, slot, slotval;
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const char *str;
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printf("%s: %sK Scatter/Gather RAM Entries Available.\n",
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sc->dwlpx_dev.dv_xname,
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sc->dwlpx_sgmapsz == DWLPX_SG32K? "32" : "128");
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for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) {
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for (slot = 0; slot < 4; slot++) {
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slotval = (pcia_present >>
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@ -190,9 +192,30 @@ dwlpx_init(sc)
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struct dwlpx_softc *sc;
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{
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int i;
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u_int32_t ctl;
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struct dwlpx_config *ccp = &sc->dwlpx_cc;
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unsigned long ls = DWLPX_SYSBASE(sc);
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if (ccp->cc_initted == 0) {
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/*
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* On reads, you get a fault if you read a nonexisted HPC.
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* We know the internal KFTIA hose (hose 0) has only 2 HPCs,
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* but we can also actually probe for HPCs.
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* Assume at least one.
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*/
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for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC;
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sc->dwlpx_nhpc++) {
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if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
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sizeof (ctl)) != 0) {
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break;
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}
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}
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if (sc->dwlpx_nhpc != NHPC) {
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/* clear (potential) Illegal CSR Address Error */
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REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
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PCIA_ERR_ALLERR;
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}
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dwlpx_bus_io_init(&ccp->cc_iot, ccp);
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dwlpx_bus_mem_init(&ccp->cc_memt, ccp);
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}
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@ -202,16 +225,34 @@ dwlpx_init(sc)
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/*
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* Establish a precalculated base for convenience's sake.
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*/
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ccp->cc_sysbase =
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(((unsigned long)(sc->dwlpx_node - 4)) << 36) |
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(((unsigned long) sc->dwlpx_hosenum) << 34) |
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(1LL << 39);
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ccp->cc_sysbase = ls;
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/*
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* Set up DMA stuff for this DWLPX.
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*/
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dwlpx_dma_init(ccp);
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/*
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* If there are only 2 HPCs, then the 'present' register is not
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* implemented, so there will only ever be 32K SG entries. Otherwise
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* any revision greater than zero will have 128K entries.
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*/
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ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
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if (sc->dwlpx_nhpc == 2) {
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sc->dwlpx_sgmapsz = DWLPX_SG32K;
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#if 0
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/*
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* As of 2/25/98- When I enable SG128K, and then have to flip
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* TBIT below, I get bad SGRAM errors. We'll fix this later
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* if this gets important.
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*/
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} else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
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sc->dwlpx_sgmapsz = DWLPX_SG128K;
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#endif
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} else {
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sc->dwlpx_sgmapsz = DWLPX_SG32K;
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}
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/*
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* Set up interrupt stuff for this DWLPX.
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*
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@ -249,7 +290,7 @@ dwlpx_init(sc)
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* Establish HAE values, as well as make sure of sanity elsewhere.
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*/
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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u_int32_t ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
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ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
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ctl &= 0x0fffffff;
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ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
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/*
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@ -265,7 +306,98 @@ dwlpx_init(sc)
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ctl |= PCIA_CTL_CUTENA;
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/*
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* Fit in appropriate S/G Map Ram size.
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*/
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if (sc->dwlpx_sgmapsz == DWLPX_SG32K)
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ctl |= PCIA_CTL_SG32K;
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else if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
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ctl |= PCIA_CTL_SG128K;
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else
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ctl |= PCIA_CTL_SG32K;
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REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
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}
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/*
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* Enable TBIT if required
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*/
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if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
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REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
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alpha_mb();
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ccp->cc_initted = 1;
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}
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void
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dwlpx_iointr(framep, vec)
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void *framep;
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unsigned long vec;
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{
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struct dwlpx_softc *sc;
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struct dwlpx_config *ccp;
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int ionode, hosenum, i;
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struct {
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u_int32_t err;
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u_int32_t addr;
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} hpcs[NHPC];
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ionode = (vec >> 8) & 0xf;
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hosenum = (vec >> 4) & 0x7;
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if (ionode >= DWLPX_NIONODE || hosenum >= DWLPX_NHOSE) {
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panic("dwlpx_iointr: mangled vector %x", vec);
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/* NOTREACHED */
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}
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sc = dwlps[ionode][hosenum];
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ccp = &sc->dwlpx_cc;
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
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hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
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}
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printf("%s: node %d hose %d error interrupt\n",
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sc->dwlpx_dev.dv_xname, ionode + 4, hosenum);
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
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continue;
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printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
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"Failing Address 0x%x\n",
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i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
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"read from", hpcs[i].addr & ~3);
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if (hpcs[i].err & PCIA_ERR_SERR_L)
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printf("\t PCI device asserted SERR_L\n");
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if (hpcs[i].err & PCIA_ERR_ILAT)
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printf("\t Incremental Latency Exceeded\n");
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if (hpcs[i].err & PCIA_ERR_SGPRTY)
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printf("\t CPU access of SG RAM Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_ILLCSR)
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printf("\t Illegal CSR Address Error\n");
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if (hpcs[i].err & PCIA_ERR_PCINXM)
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printf("\t Nonexistent PCI Address Error\n");
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if (hpcs[i].err & PCIA_ERR_DSCERR)
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printf("\t PCI Target Disconnect Error\n");
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if (hpcs[i].err & PCIA_ERR_ABRT)
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printf("\t PCI Target Abort Error\n");
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if (hpcs[i].err & PCIA_ERR_WPRTY)
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printf("\t PCI Write Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_DPERR)
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printf("\t PCI Data Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_APERR)
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printf("\t PCI Address Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_DFLT)
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printf("\t SG Map RAM Invalid Entry Error\n");
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if (hpcs[i].err & PCIA_ERR_DPRTY)
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printf("\t DMA access of SG RAM Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_DRPERR)
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printf("\t DMA Read Return Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_MABRT)
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printf("\t PCI Master Abort Error\n");
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if (hpcs[i].err & PCIA_ERR_CPRTY)
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printf("\t CSR Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_COVR)
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printf("\t CSR Overrun Error\n");
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if (hpcs[i].err & PCIA_ERR_MBPERR)
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printf("\t Mailbox Parity Error\n");
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if (hpcs[i].err & PCIA_ERR_MBILI)
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printf("\t Mailbox Illegal Length Error\n");
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REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
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}
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}
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