Add basic platform support for NetBSD on the Avalon A12. I'm running this
CVS commit on one right now...
This commit is contained in:
ross
parent
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/* $NetBSD: a12c.c,v 1.1 1998/01/29 21:42:50 ross Exp $ */
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/* [Notice revision 2.0]
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* Copyright (c) 1997 Avalon Computer Systems, Inc.
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* All rights reserved.
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*
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* Author: Ross Harvey
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright and
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* author notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* 4. This copyright will be assigned to The NetBSD Foundation on
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* 1/1/2000 unless these terms (including possibly the assignment
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* date) are updated in writing by Avalon prior to the latest specified
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* assignment date.
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*
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* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_avalon_a12.h" /* Config options headers */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: a12c.c,v 1.1 1998/01/29 21:42:50 ross Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <machine/rpb.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/a12creg.h>
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#include <alpha/pci/a12cvar.h>
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#include <alpha/pci/pci_a12.h>
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int a12cmatch __P((struct device *, struct cfdata *, void *));
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void a12cattach __P((struct device *, struct device *, void *));
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struct cfattach a12c_ca = {
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sizeof(struct a12c_softc), a12cmatch, a12cattach,
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};
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extern struct cfdriver a12c_cd;
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static int a12cprint __P((void *, const char *pnp));
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static void hrh_noclock(void);
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/* There can be only one. */
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int a12cfound;
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struct a12c_config a12c_configuration;
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int
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a12cmatch(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct confargs *ca = aux;
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/* Make sure that we're looking for an A12C. */
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if (strcmp(ca->ca_name, a12c_cd.cd_name) != 0)
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return (0);
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if (a12cfound)
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return (0);
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return (1);
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}
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/*
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* Set up the chipset's function pointers.
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*/
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void
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a12c_init(ccp, mallocsafe)
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struct a12c_config *ccp;
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int mallocsafe;
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{
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if (!ccp->ac_initted) {
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/* someday these may allocate memory, do once only */
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ccp->ac_iot = 0;
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ccp->ac_memt = a12c_bus_mem_init(ccp);
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}
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ccp->ac_mallocsafe = mallocsafe;
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a12c_pci_init(&ccp->ac_pc, ccp);
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a12c_dma_init(ccp);
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ccp->ac_initted = 1;
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}
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void
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a12cattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct a12c_softc *sc = (struct a12c_softc *)self;
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struct a12c_config *ccp;
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struct pcibus_attach_args pba;
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/* note that we've attached the chipset; can't have 2 A12Cs. */
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a12cfound = 1;
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/*
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* set up the chipset's info; done once at console init time
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* (maybe), but we must do it here as well to take care of things
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* that need to use memory allocation.
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*/
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ccp = sc->sc_ccp = &a12c_configuration;
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a12c_init(ccp, 1);
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/* XXX print chipset information */
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printf("\n");
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switch (hwrpb->rpb_type) {
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#ifdef AVALON_A12
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case ST_AVALON_A12:
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pci_a12_pickintr(ccp);
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#ifdef EVCNT_COUNTERS
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evcnt_attach(self, "intr", &a12_intr_evcnt);
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#endif
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break;
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#endif
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default:
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panic("a12cattach: shouldn't be here, really...");
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}
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pba.pba_busname = "pci";
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pba.pba_iot = 0;
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pba.pba_memt = ccp->ac_memt;
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pba.pba_dmat = &ccp->ac_dmat_direct;
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pba.pba_pc = &ccp->ac_pc;
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pba.pba_bus = 0;
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pba.pba_flags = PCI_FLAGS_MEM_ENABLED;
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config_found(self, &pba, a12cprint);
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hrh_noclock();
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}
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static int
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a12cprint(aux, pnp)
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void *aux;
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const char *pnp;
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{
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register struct pcibus_attach_args *pba = aux;
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/* can attach xbar or pci to a12c */
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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#include <dev/dec/clockvar.h>
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static const struct clocktime zeroct;
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static void noclock_init(struct device *);
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static void noclock_get(struct device *, time_t, struct clocktime *);
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static void noclock_set(struct device *, struct clocktime *);
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static void noclock_init(struct device *dev) {
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dev = dev;
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}
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static void noclock_get(struct device *dev, time_t t, struct clocktime *ct)
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{
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*ct = zeroct;
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}
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static void noclock_set(struct device *dev, struct clocktime *ct)
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{
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if(dev!=NULL)
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*ct = *ct;
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}
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static const struct clockfns noclock_fns = {
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noclock_init, noclock_get, noclock_set
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};
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static void
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hrh_noclock(void) {
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extern const struct clockfns *clockfns;
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clockfns = &noclock_fns;
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}
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@ -0,0 +1,521 @@
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/* $NetBSD: a12c_bus_mem.c,v 1.1 1998/01/29 21:42:51 ross Exp $ */
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/* [Notice revision 2.0]
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* Copyright (c) 1997 Avalon Computer Systems, Inc.
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* All rights reserved.
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*
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* Author: Ross Harvey
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright and
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* author notice, this list of conditions, and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* 4. This copyright will be assigned to The NetBSD Foundation on
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* 1/1/2000 unless these terms (including possibly the assignment
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* date) are updated in writing by Avalon prior to the latest specified
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* assignment date.
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*
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* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_avalon_a12.h" /* Config options headers */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <alpha/pci/a12creg.h>
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#include <alpha/pci/a12cvar.h>
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__KERNEL_RCSID(0, "$NetBSD: a12c_bus_mem.c,v 1.1 1998/01/29 21:42:51 ross Exp $");
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/* Memory barrier */
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void pci_a12c_mem_barrier __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, int));
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/* Memory read (single) */
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u_int8_t pci_a12c_mem_read_1 __P((void *, bus_space_handle_t,
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bus_size_t));
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u_int16_t pci_a12c_mem_read_2 __P((void *, bus_space_handle_t,
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bus_size_t));
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u_int32_t pci_a12c_mem_read_4 __P((void *, bus_space_handle_t,
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bus_size_t));
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u_int64_t pci_a12c_mem_read_8 __P((void *, bus_space_handle_t,
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bus_size_t));
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/* Memory read multiple */
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void pci_a12c_mem_read_multi_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void pci_a12c_mem_read_multi_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void pci_a12c_mem_read_multi_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void pci_a12c_mem_read_multi_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* Memory read region */
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void pci_a12c_mem_read_region_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void pci_a12c_mem_read_region_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void pci_a12c_mem_read_region_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void pci_a12c_mem_read_region_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* Memory write (single) */
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void pci_a12c_mem_write_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t));
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void pci_a12c_mem_write_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t));
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void pci_a12c_mem_write_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t));
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void pci_a12c_mem_write_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t));
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/* Memory write multiple */
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void pci_a12c_mem_write_multi_1 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void pci_a12c_mem_write_multi_2 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void pci_a12c_mem_write_multi_4 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void pci_a12c_mem_write_multi_8 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* Memory write region */
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void pci_a12c_mem_write_region_1 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void pci_a12c_mem_write_region_2 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void pci_a12c_mem_write_region_4 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void pci_a12c_mem_write_region_8 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* Memory set multiple */
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void pci_a12c_mem_set_multi_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t, bus_size_t));
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void pci_a12c_mem_set_multi_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t, bus_size_t));
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void pci_a12c_mem_set_multi_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t, bus_size_t));
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void pci_a12c_mem_set_multi_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t, bus_size_t));
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/* Memory set region */
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void pci_a12c_mem_set_region_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t, bus_size_t));
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void pci_a12c_mem_set_region_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t, bus_size_t));
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void pci_a12c_mem_set_region_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t, bus_size_t));
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void pci_a12c_mem_set_region_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t, bus_size_t));
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/* Memory copy */
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void pci_a12c_mem_copy_region_1 __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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void pci_a12c_mem_copy_region_2 __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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void pci_a12c_mem_copy_region_4 __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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void pci_a12c_mem_copy_region_8 __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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#define __S(S) __STRING(S)
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/* mapping/unmapping */
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int pci_a12c_mem_map __P((void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *));
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void pci_a12c_mem_unmap __P((void *, bus_space_handle_t,
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bus_size_t));
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int pci_a12c_mem_subregion __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, bus_space_handle_t *));
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/* allocation/deallocation */
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int pci_a12c_mem_alloc __P((void *, bus_addr_t, bus_addr_t,
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bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
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bus_space_handle_t *));
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void pci_a12c_mem_free __P((void *, bus_space_handle_t,
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bus_size_t));
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static struct alpha_bus_space pci_a12c_mem_space = {
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/* cookie */
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NULL,
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/* mapping/unmapping */
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pci_a12c_mem_map,
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pci_a12c_mem_unmap,
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pci_a12c_mem_subregion,
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/* allocation/deallocation */
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pci_a12c_mem_alloc,
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pci_a12c_mem_free,
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/* barrier */
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pci_a12c_mem_barrier,
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/* read (single) */
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pci_a12c_mem_read_1,
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pci_a12c_mem_read_2,
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pci_a12c_mem_read_4,
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pci_a12c_mem_read_8,
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/* read multiple */
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pci_a12c_mem_read_multi_1,
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pci_a12c_mem_read_multi_2,
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pci_a12c_mem_read_multi_4,
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pci_a12c_mem_read_multi_8,
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/* read region */
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pci_a12c_mem_read_region_1,
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pci_a12c_mem_read_region_2,
|
||||
pci_a12c_mem_read_region_4,
|
||||
pci_a12c_mem_read_region_8,
|
||||
|
||||
/* write (single) */
|
||||
pci_a12c_mem_write_1,
|
||||
pci_a12c_mem_write_2,
|
||||
pci_a12c_mem_write_4,
|
||||
pci_a12c_mem_write_8,
|
||||
|
||||
/* write multiple */
|
||||
pci_a12c_mem_write_multi_1,
|
||||
pci_a12c_mem_write_multi_2,
|
||||
pci_a12c_mem_write_multi_4,
|
||||
pci_a12c_mem_write_multi_8,
|
||||
|
||||
/* write region */
|
||||
pci_a12c_mem_write_region_1,
|
||||
pci_a12c_mem_write_region_2,
|
||||
pci_a12c_mem_write_region_4,
|
||||
pci_a12c_mem_write_region_8,
|
||||
|
||||
/* set multiple */
|
||||
pci_a12c_mem_set_multi_1,
|
||||
pci_a12c_mem_set_multi_2,
|
||||
pci_a12c_mem_set_multi_4,
|
||||
pci_a12c_mem_set_multi_8,
|
||||
|
||||
/* set region */
|
||||
pci_a12c_mem_set_region_1,
|
||||
pci_a12c_mem_set_region_2,
|
||||
pci_a12c_mem_set_region_4,
|
||||
pci_a12c_mem_set_region_8,
|
||||
|
||||
/* copy */
|
||||
pci_a12c_mem_copy_region_1,
|
||||
pci_a12c_mem_copy_region_2,
|
||||
pci_a12c_mem_copy_region_4,
|
||||
pci_a12c_mem_copy_region_8,
|
||||
};
|
||||
|
||||
bus_space_tag_t
|
||||
a12c_bus_mem_init(v)
|
||||
void *v;
|
||||
{
|
||||
bus_space_tag_t t;
|
||||
|
||||
t = &pci_a12c_mem_space;
|
||||
t->abs_cookie = v;
|
||||
return (t);
|
||||
}
|
||||
|
||||
int
|
||||
pci_a12c_mem_map(v, memaddr, memsize, flags, memhp)
|
||||
void *v;
|
||||
bus_addr_t memaddr;
|
||||
bus_size_t memsize;
|
||||
int flags;
|
||||
bus_space_handle_t *memhp;
|
||||
{
|
||||
if(flags & BUS_SPACE_MAP_LINEAR)
|
||||
printf("warning, linear a12 pci map requested\n");
|
||||
if(memaddr >= 1L<<28 || memaddr<0)
|
||||
return -1;
|
||||
*memhp = memaddr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
pci_a12c_mem_unmap(v, memh, memsize)
|
||||
void *v;
|
||||
bus_space_handle_t memh;
|
||||
bus_size_t memsize;
|
||||
{
|
||||
}
|
||||
|
||||
int
|
||||
pci_a12c_mem_subregion(v, memh, offset, size, nmemh)
|
||||
void *v;
|
||||
bus_space_handle_t memh, *nmemh;
|
||||
bus_size_t offset, size;
|
||||
{
|
||||
*nmemh = memh + offset;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
pci_a12c_mem_alloc(v, rstart, rend, size, align, boundary, flags,
|
||||
addrp, bshp)
|
||||
void *v;
|
||||
bus_addr_t rstart, rend, *addrp;
|
||||
bus_size_t size, align, boundary;
|
||||
int flags;
|
||||
bus_space_handle_t *bshp;
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
void
|
||||
pci_a12c_mem_free(v, bsh, size)
|
||||
void *v;
|
||||
bus_space_handle_t bsh;
|
||||
bus_size_t size;
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_a12c_mem_barrier(v, h, o, l, f)
|
||||
void *v;
|
||||
bus_space_handle_t h;
|
||||
bus_size_t o, l;
|
||||
int f;
|
||||
{
|
||||
/* optimize for wmb-only case but fall back to the more general mb */
|
||||
|
||||
if (f == BUS_SPACE_BARRIER_WRITE)
|
||||
alpha_wmb();
|
||||
else alpha_mb();
|
||||
}
|
||||
/*
|
||||
* Don't worry about calling small subroutines on the alpha. In the
|
||||
* time it takes to do a PCI bus target transfer, the 21164-400 can execute
|
||||
* 160 cycles, and up to 320 integer instructions.
|
||||
*/
|
||||
static void *
|
||||
setup_target_transfer(bus_space_handle_t memh, bus_size_t off)
|
||||
{
|
||||
register u_int64_t addr,t;
|
||||
|
||||
alpha_mb();
|
||||
addr = memh + off;
|
||||
t = REGVAL(A12_OMR) & ~A12_PCIAddr2;
|
||||
if (addr & 4)
|
||||
t |= A12_PCIAddr2;
|
||||
REGVAL(A12_OMR) = t;
|
||||
alpha_mb();
|
||||
return (void *)ALPHA_PHYS_TO_K0SEG(A12_PCITarget | (addr & ~4L));
|
||||
}
|
||||
|
||||
#define TARGET_EA(t,memh,off) ((t *)setup_target_transfer((memh),(off)))
|
||||
|
||||
#define TARGET_READ(n,t) \
|
||||
\
|
||||
t \
|
||||
__CONCAT(pci_a12c_mem_read_,n)(void *v, \
|
||||
bus_space_handle_t memh, \
|
||||
bus_size_t off) \
|
||||
{ \
|
||||
return *TARGET_EA(t,memh,off); \
|
||||
}
|
||||
|
||||
TARGET_READ(1, u_int8_t)
|
||||
TARGET_READ(2, u_int16_t)
|
||||
TARGET_READ(4, u_int32_t)
|
||||
TARGET_READ(8, u_int64_t)
|
||||
|
||||
#define pci_a12c_mem_read_multi_N(BYTES,TYPE) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_read_multi_,BYTES)(v, h, o, a, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
TYPE *a; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
alpha_mb(); \
|
||||
*a++ = __CONCAT(pci_a12c_mem_read_,BYTES)(v, h, o); \
|
||||
} \
|
||||
}
|
||||
|
||||
pci_a12c_mem_read_multi_N(1,u_int8_t)
|
||||
pci_a12c_mem_read_multi_N(2,u_int16_t)
|
||||
pci_a12c_mem_read_multi_N(4,u_int32_t)
|
||||
pci_a12c_mem_read_multi_N(8,u_int64_t)
|
||||
/*
|
||||
|
||||
* In this case, we _really_ don't want all those barriers that the
|
||||
* bus_space_read's once did, and that we have carried over into
|
||||
* the A12 version. Perhaps we need a gratuitous barrier-on mode.
|
||||
* The only reason to have the bus_space_r/w functions do barriers is
|
||||
* to make up for call sites that incorrectly omit the bus_space_barrier
|
||||
* calls.
|
||||
*/
|
||||
|
||||
#define pci_a12c_mem_read_region_N(BYTES,TYPE) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_read_region_,BYTES)(v, h, o, a, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
TYPE *a; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
*a++ = __CONCAT(pci_a12c_mem_read_,BYTES)(v, h, o); \
|
||||
o += sizeof *a; \
|
||||
} \
|
||||
}
|
||||
pci_a12c_mem_read_region_N(1,u_int8_t)
|
||||
pci_a12c_mem_read_region_N(2,u_int16_t)
|
||||
pci_a12c_mem_read_region_N(4,u_int32_t)
|
||||
pci_a12c_mem_read_region_N(8,u_int64_t)
|
||||
|
||||
#define TARGET_WRITE(n,t) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_write_,n)(v, memh, off, val) \
|
||||
void *v; \
|
||||
bus_space_handle_t memh; \
|
||||
bus_size_t off; \
|
||||
t val; \
|
||||
{ \
|
||||
alpha_wmb(); \
|
||||
*TARGET_EA(t,memh,off) = val; \
|
||||
alpha_wmb(); \
|
||||
}
|
||||
|
||||
TARGET_WRITE(1,u_int8_t)
|
||||
TARGET_WRITE(2,u_int16_t)
|
||||
TARGET_WRITE(4,u_int32_t)
|
||||
TARGET_WRITE(8,u_int64_t)
|
||||
|
||||
#define pci_a12c_mem_write_multi_N(BYTES,TYPE) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_write_multi_,BYTES)(v, h, o, a, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
const TYPE *a; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
__CONCAT(pci_a12c_mem_write_,BYTES)(v, h, o, *a++); \
|
||||
alpha_wmb(); \
|
||||
} \
|
||||
}
|
||||
|
||||
pci_a12c_mem_write_multi_N(1,u_int8_t)
|
||||
pci_a12c_mem_write_multi_N(2,u_int16_t)
|
||||
pci_a12c_mem_write_multi_N(4,u_int32_t)
|
||||
pci_a12c_mem_write_multi_N(8,u_int64_t)
|
||||
|
||||
#define pci_a12c_mem_write_region_N(BYTES,TYPE) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_write_region_,BYTES)(v, h, o, a, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
const TYPE *a; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
__CONCAT(pci_a12c_mem_write_,BYTES)(v, h, o, *a++); \
|
||||
o += sizeof *a; \
|
||||
} \
|
||||
}
|
||||
|
||||
pci_a12c_mem_write_region_N(1,u_int8_t)
|
||||
pci_a12c_mem_write_region_N(2,u_int16_t)
|
||||
pci_a12c_mem_write_region_N(4,u_int32_t)
|
||||
pci_a12c_mem_write_region_N(8,u_int64_t)
|
||||
|
||||
#define pci_a12c_mem_set_multi_N(BYTES,TYPE) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_set_multi_,BYTES)(v, h, o, val, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
TYPE val; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
__CONCAT(pci_a12c_mem_write_,BYTES)(v, h, o, val); \
|
||||
alpha_wmb(); \
|
||||
} \
|
||||
}
|
||||
|
||||
pci_a12c_mem_set_multi_N(1,u_int8_t)
|
||||
pci_a12c_mem_set_multi_N(2,u_int16_t)
|
||||
pci_a12c_mem_set_multi_N(4,u_int32_t)
|
||||
pci_a12c_mem_set_multi_N(8,u_int64_t)
|
||||
|
||||
#define pci_a12c_mem_set_region_N(BYTES,TYPE) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_set_region_,BYTES)(v, h, o, val, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
TYPE val; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
__CONCAT(pci_a12c_mem_write_,BYTES)(v, h, o, val); \
|
||||
o += sizeof val; \
|
||||
} \
|
||||
}
|
||||
|
||||
pci_a12c_mem_set_region_N(1,u_int8_t)
|
||||
pci_a12c_mem_set_region_N(2,u_int16_t)
|
||||
pci_a12c_mem_set_region_N(4,u_int32_t)
|
||||
pci_a12c_mem_set_region_N(8,u_int64_t)
|
||||
|
||||
#define pci_a12c_mem_copy_region_N(BYTES) \
|
||||
void \
|
||||
__CONCAT(pci_a12c_mem_copy_region_,BYTES)(v, h1, o1, h2, o2, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h1, h2; \
|
||||
bus_size_t o1, o2, c; \
|
||||
{ \
|
||||
bus_size_t o; \
|
||||
\
|
||||
if ((h1 >> 63) != 0 && (h2 >> 63) != 0) { \
|
||||
ovbcopy((void *)(h1 + o1), (void *)(h2 + o2), c * BYTES); \
|
||||
return; \
|
||||
} \
|
||||
\
|
||||
if (h1 + o1 >= h2 + o2) \
|
||||
/* src after dest: copy forward */ \
|
||||
for (o = 0; c > 0; c--, o += BYTES) \
|
||||
__CONCAT(pci_a12c_mem_write_,BYTES)(v, h2, o2 + o, \
|
||||
__CONCAT(pci_a12c_mem_read_,BYTES)(v, h1, o1 + o)); \
|
||||
else \
|
||||
/* dest after src: copy backwards */ \
|
||||
for (o = (c - 1) * BYTES; c > 0; c--, o -= BYTES) \
|
||||
__CONCAT(pci_a12c_mem_write_,BYTES)(v, h2, o2 + o, \
|
||||
__CONCAT(pci_a12c_mem_read_,BYTES)(v, h1, o1 + o)); \
|
||||
}
|
||||
pci_a12c_mem_copy_region_N(1)
|
||||
pci_a12c_mem_copy_region_N(2)
|
||||
pci_a12c_mem_copy_region_N(4)
|
||||
pci_a12c_mem_copy_region_N(8)
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/* $NetBSD: a12c_dma.c,v 1.1 1998/01/29 21:42:51 ross Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Stub version -- drivers used on the A12 (primarily ade) were adapted
|
||||
* for NetBSD prior to the availability of bus_dma.
|
||||
* They employ ad-hoc support for the required sram
|
||||
* bounce buffers and are not in the NetBSD source
|
||||
* tree. When a bus_dma if_de is available, this
|
||||
* module will need to be completed! I certainly
|
||||
* would not mind committing if_ade, but it doesn't
|
||||
* have any lasting value.
|
||||
*/
|
||||
|
||||
#include "opt_avalon_a12.h" /* Config options headers */
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: a12c_dma.c,v 1.1 1998/01/29 21:42:51 ross Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <vm/vm.h>
|
||||
|
||||
#define _ALPHA_BUS_DMA_PRIVATE
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <alpha/pci/a12creg.h>
|
||||
#include <alpha/pci/a12cvar.h>
|
||||
|
||||
bus_dma_tag_t a12c_dma_get_tag __P((bus_dma_tag_t, alpha_bus_t));
|
||||
|
||||
|
||||
int a12c_bus_dmamap_load_direct __P((bus_dma_tag_t, bus_dmamap_t, void *,
|
||||
bus_size_t, struct proc *, int));
|
||||
|
||||
int a12c_bus_dmamap_load_mbuf_direct __P((bus_dma_tag_t, bus_dmamap_t,
|
||||
struct mbuf *, int));
|
||||
|
||||
int a12c_bus_dmamap_load_uio_direct __P((bus_dma_tag_t, bus_dmamap_t,
|
||||
struct uio *, int));
|
||||
|
||||
int a12c_bus_dmamap_load_raw_direct __P((bus_dma_tag_t, bus_dmamap_t,
|
||||
bus_dma_segment_t *, int, bus_size_t, int));
|
||||
|
||||
void
|
||||
a12c_dma_init(ccp)
|
||||
struct a12c_config *ccp;
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the bus dma tag to be used for the specified bus type.
|
||||
* INTERNAL USE ONLY!
|
||||
*/
|
||||
bus_dma_tag_t
|
||||
a12c_dma_get_tag(t, bustype)
|
||||
bus_dma_tag_t t;
|
||||
alpha_bus_t bustype;
|
||||
{
|
||||
DIE();
|
||||
}
|
||||
/*
|
||||
* Load a A12C direct-mapped DMA map with a linear buffer.
|
||||
*/
|
||||
int
|
||||
a12c_bus_dmamap_load_direct(t, map, buf, buflen, p, flags)
|
||||
bus_dma_tag_t t;
|
||||
bus_dmamap_t map;
|
||||
void *buf;
|
||||
bus_size_t buflen;
|
||||
struct proc *p;
|
||||
int flags;
|
||||
{
|
||||
DIE();
|
||||
#if 0
|
||||
|
||||
return (_bus_dmamap_load_direct_common(t, map, buf, buflen, p,
|
||||
flags, A12C_DIRECT_MAPPED_BASE));
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* Load a A12C direct-mapped DMA map with an mbuf chain.
|
||||
*/
|
||||
int
|
||||
a12c_bus_dmamap_load_mbuf_direct(t, map, m, flags)
|
||||
bus_dma_tag_t t;
|
||||
bus_dmamap_t map;
|
||||
struct mbuf *m;
|
||||
int flags;
|
||||
{
|
||||
DIE();
|
||||
#if 0
|
||||
|
||||
return (_bus_dmamap_load_mbuf_direct_common(t, map, m,
|
||||
flags, A12C_DIRECT_MAPPED_BASE));
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* Load a A12C direct-mapped DMA map with a uio.
|
||||
*/
|
||||
int
|
||||
a12c_bus_dmamap_load_uio_direct(t, map, uio, flags)
|
||||
bus_dma_tag_t t;
|
||||
bus_dmamap_t map;
|
||||
struct uio *uio;
|
||||
int flags;
|
||||
{
|
||||
DIE();
|
||||
#if 0
|
||||
|
||||
return (_bus_dmamap_load_uio_direct_common(t, map, uio,
|
||||
flags, A12C_DIRECT_MAPPED_BASE));
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* Load a A12C direct-mapped DMA map with raw memory.
|
||||
*/
|
||||
int
|
||||
a12c_bus_dmamap_load_raw_direct(t, map, segs, nsegs, size, flags)
|
||||
bus_dma_tag_t t;
|
||||
bus_dmamap_t map;
|
||||
bus_dma_segment_t *segs;
|
||||
int nsegs;
|
||||
bus_size_t size;
|
||||
int flags;
|
||||
{
|
||||
DIE();
|
||||
#if 0
|
||||
|
||||
return (_bus_dmamap_load_raw_direct_common(t, map, segs, nsegs,
|
||||
size, flags, A12C_DIRECT_MAPPED_BASE));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
/* $NetBSD: a12c_pci.c,v 1.1 1998/01/29 21:42:52 ross Exp $ */
|
||||
|
||||
/* [Notice revision 2.0]
|
||||
* Copyright (c) 1997 Avalon Computer Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Author: Ross Harvey
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright and
|
||||
* author notice, this list of conditions, and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* 4. This copyright will be assigned to The NetBSD Foundation on
|
||||
* 1/1/2000 unless these terms (including possibly the assignment
|
||||
* date) are updated in writing by Avalon prior to the latest specified
|
||||
* assignment date.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "opt_avalon_a12.h" /* Config options headers */
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: a12c_pci.c,v 1.1 1998/01/29 21:42:52 ross Exp $");
|
||||
__KERNEL_COPYRIGHT(0,
|
||||
"Copyright (c) 1997 Christopher G. Demetriou. All rights reserved.");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/device.h>
|
||||
#include <vm/vm.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <alpha/pci/a12creg.h>
|
||||
#include <alpha/pci/a12cvar.h>
|
||||
|
||||
#include <machine/rpb.h> /* XXX for eb164 CIA firmware workarounds. */
|
||||
|
||||
void a12c_attach_hook __P((struct device *, struct device *,
|
||||
struct pcibus_attach_args *));
|
||||
int a12c_bus_maxdevs __P((void *, int));
|
||||
pcitag_t a12c_make_tag __P((void *, int, int, int));
|
||||
void a12c_decompose_tag __P((void *, pcitag_t, int *, int *,
|
||||
int *));
|
||||
pcireg_t a12c_conf_read __P((void *, pcitag_t, int));
|
||||
void a12c_conf_write __P((void *, pcitag_t, int, pcireg_t));
|
||||
|
||||
void
|
||||
a12c_pci_init(pc, v)
|
||||
pci_chipset_tag_t pc;
|
||||
void *v;
|
||||
{
|
||||
|
||||
pc->pc_conf_v = v;
|
||||
pc->pc_attach_hook = a12c_attach_hook;
|
||||
pc->pc_bus_maxdevs = a12c_bus_maxdevs;
|
||||
pc->pc_make_tag = a12c_make_tag;
|
||||
pc->pc_decompose_tag = a12c_decompose_tag;
|
||||
pc->pc_conf_read = a12c_conf_read;
|
||||
pc->pc_conf_write = a12c_conf_write;
|
||||
}
|
||||
|
||||
void
|
||||
a12c_attach_hook(parent, self, pba)
|
||||
struct device *parent, *self;
|
||||
struct pcibus_attach_args *pba;
|
||||
{
|
||||
}
|
||||
|
||||
int
|
||||
a12c_bus_maxdevs(cpv, busno)
|
||||
void *cpv;
|
||||
int busno;
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
pcitag_t
|
||||
a12c_make_tag(cpv, b, d, f)
|
||||
void *cpv;
|
||||
int b, d, f;
|
||||
{
|
||||
|
||||
return (b << 16) | (d << 11) | (f << 8);
|
||||
}
|
||||
|
||||
void
|
||||
a12c_decompose_tag(cpv, tag, bp, dp, fp)
|
||||
void *cpv;
|
||||
pcitag_t tag;
|
||||
int *bp, *dp, *fp;
|
||||
{
|
||||
|
||||
if (bp != NULL)
|
||||
*bp = (tag >> 16) & 0xff;
|
||||
if (dp != NULL)
|
||||
*dp = (tag >> 11) & 0x1f;
|
||||
if (fp != NULL)
|
||||
*fp = (tag >> 8) & 0x7;
|
||||
}
|
||||
|
||||
static void
|
||||
a12_clear_master_abort(void)
|
||||
{
|
||||
alpha_pal_draina();
|
||||
alpha_mb();
|
||||
REGVAL(A12_GSR) = REGVAL(A12_GSR) | A12_PCIMasterAbort;
|
||||
alpha_mb();
|
||||
}
|
||||
|
||||
static int
|
||||
a12_check_for_master_abort(void)
|
||||
{
|
||||
alpha_pal_draina();
|
||||
alpha_mb();
|
||||
return (REGVAL(A12_GSR) & A12_PCIMasterAbort)!=0;
|
||||
}
|
||||
|
||||
static int
|
||||
a12_set_pci_config_cycle(int offset)
|
||||
{
|
||||
alpha_pal_draina();
|
||||
alpha_mb();
|
||||
REGVAL(A12_OMR) = REGVAL(A12_OMR)
|
||||
| A12_PCIConfigCycle
|
||||
| (offset & 4 ? A12_PCIAddr2 : 0);
|
||||
alpha_mb();
|
||||
return offset & ~4;
|
||||
}
|
||||
|
||||
static void
|
||||
a12_reset_pci_config_cycle(void)
|
||||
{
|
||||
alpha_pal_draina();
|
||||
alpha_mb();
|
||||
REGVAL(A12_OMR) = REGVAL(A12_OMR) & ~(A12_PCIConfigCycle|A12_PCIAddr2);
|
||||
alpha_mb();
|
||||
}
|
||||
|
||||
pcireg_t
|
||||
a12c_conf_read(cpv, tag, offset)
|
||||
void *cpv;
|
||||
pcitag_t tag;
|
||||
int offset;
|
||||
{
|
||||
pcireg_t *datap, data;
|
||||
int s, ba;
|
||||
int32_t old_haxr2; /* XXX */
|
||||
|
||||
s = 0; /* XXX gcc -Wuninitialized */
|
||||
old_haxr2 = 0; /* XXX gcc -Wuninitialized */
|
||||
|
||||
if(tag)
|
||||
return ~0;
|
||||
|
||||
s = splhigh();
|
||||
a12_clear_master_abort();
|
||||
offset = a12_set_pci_config_cycle(offset);
|
||||
|
||||
datap = (pcireg_t *)(ALPHA_PHYS_TO_K0SEG(A12_PCITarget+offset));
|
||||
data = ~0L;
|
||||
if(!(ba = badaddr(datap, sizeof *datap)))
|
||||
data = *datap;
|
||||
|
||||
a12_reset_pci_config_cycle();
|
||||
if(a12_check_for_master_abort())
|
||||
data = ~0L;
|
||||
|
||||
splx(s);
|
||||
#if 0
|
||||
printf("a12c_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, offset,
|
||||
data, datap, ba ? " (badaddr)" : "");
|
||||
#endif
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
a12c_conf_write(cpv, tag, offset, data)
|
||||
void *cpv;
|
||||
pcitag_t tag;
|
||||
int offset;
|
||||
pcireg_t data;
|
||||
{
|
||||
pcireg_t *datap;
|
||||
int s;
|
||||
|
||||
s = 0; /* XXX gcc -Wuninitialized */
|
||||
|
||||
if(tag) {
|
||||
What();
|
||||
return;
|
||||
}
|
||||
|
||||
s = splhigh();
|
||||
offset = a12_set_pci_config_cycle(offset);
|
||||
datap = (pcireg_t *)(ALPHA_PHYS_TO_K0SEG(A12_PCITarget+offset));
|
||||
*datap = data;
|
||||
a12_reset_pci_config_cycle();
|
||||
splx(s);
|
||||
#if 0
|
||||
printf("a12c_conf_write: tag 0x%lx, reg 0x%lx -> 0x%x @ %p\n", tag,
|
||||
offset, data, datap);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/* $NetBSD: a12creg.h,v 1.1 1998/01/29 21:42:52 ross Exp $ */
|
||||
|
||||
/* [Notice revision 2.0]
|
||||
* Copyright (c) 1997 Avalon Computer Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Author: Ross Harvey
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright and
|
||||
* author notice, this list of conditions, and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* 4. This copyright will be assigned to The NetBSD Foundation on
|
||||
* 1/1/2000 unless these terms (including possibly the assignment
|
||||
* date) are updated in writing by Avalon prior to the latest specified
|
||||
* assignment date.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef a12creg_h_INCLUDED
|
||||
#define a12creg_h_INCLUDED
|
||||
|
||||
#define REGVAL(r) (*(volatile long *)ALPHA_PHYS_TO_K0SEG(r))
|
||||
/*
|
||||
* -- A d d r e s s L i n e --
|
||||
*
|
||||
* 39 36 29 28 27-13 12 .11 10 9 8-6 5 4 3
|
||||
*
|
||||
* IMALR 1 1 a a a-a a . a a a a-a 0 0
|
||||
* IMALR_LB 1 1 a a a-a a . a a a a-a 0 1
|
||||
* OMALR 1 1 a a a-a a . a a a a-a 1 0
|
||||
* OMALR_LB 1 1 a a a-a a . a a a a-a 1 1
|
||||
* MCRP 1 0 0 0 . 0 0 0 a-a a a a
|
||||
* MCRP_LWE 1 0 0 0 . 0 0 1 0 1
|
||||
* MCRP_LWO 1 0 0 0 . 0 1 0 1 1
|
||||
* MCSR 1 0 0 1 . 0 0 1 1
|
||||
* OMR 1 0 0 1 . 0 1 0 1
|
||||
* GSR 1 0 0 1 . 0 1 1 1
|
||||
* IETCR 1 0 0 1 . 1 0 0 1
|
||||
* CDR 1 0 0 1 . 1 0 1 1
|
||||
* PMEM 1 0 0 1 . 1 1 0 1
|
||||
* SOR 1 0 0 1 . 1 1 1 1
|
||||
* PCI Buffer 1 0 1 0 a-a a . a a a a a a
|
||||
* PCI Target 1 0 1 1 a-a a . a a a a a a
|
||||
* Main Memory 0 0 a a a-a a . a a a a a a
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#define _A12_IO 0x8000000000L
|
||||
|
||||
#define A12_OFFS_FIFO 0x0000
|
||||
#define A12_OFFS_FIFO_LWE 0x0200
|
||||
#define A12_OFFS_FIFO_LWO 0x0400
|
||||
#define A12_OFFS_VERS 0x1010
|
||||
#define A12_OFFS_MCSR 0x1210
|
||||
#define A12_OFFS_OMR 0x1410
|
||||
#define A12_OFFS_GSR 0x1610
|
||||
#define A12_OFFS_IETCR 0x1810
|
||||
#define A12_OFFS_CDR 0x1a10
|
||||
#define A12_OFFS_PMEM 0x1c10
|
||||
#define A12_OFFS_SOR 0x1e10
|
||||
|
||||
#define A12_FIFO (_A12_IO|A12_OFFS_FIFO)
|
||||
#define A12_FIFO_LWE (_A12_IO|A12_OFFS_FIFO_LWE)
|
||||
#define A12_FIFO_LWO (_A12_IO|A12_OFFS_FIFO_LWO)
|
||||
#define A12_VERS (_A12_IO|A12_OFFS_VERS)
|
||||
#define A12_MCSR (_A12_IO|A12_OFFS_MCSR)
|
||||
#define A12_OMR (_A12_IO|A12_OFFS_OMR)
|
||||
#define A12_GSR (_A12_IO|A12_OFFS_GSR)
|
||||
#define A12_IETCR (_A12_IO|A12_OFFS_IETCR)
|
||||
#define A12_CDR (_A12_IO|A12_OFFS_CDR)
|
||||
#define A12_PMEM (_A12_IO|A12_OFFS_PMEM)
|
||||
#define A12_SOR (_A12_IO|A12_OFFS_SOR)
|
||||
|
||||
#define A12_PCIBuffer 0x8020000000L
|
||||
#define A12_PCITarget 0x8030000000L
|
||||
|
||||
#define A12_PCIMasterAbort 0x8000 /* GSR */
|
||||
#define A12_PCIAddr2 0x1000 /* OMR */
|
||||
#define A12_PCIConfigCycle 0x800 /* OMR */
|
||||
#define A12_CBMAOFFSET 0x100
|
||||
|
||||
#define A12_XBAR_CHANNEL_MAX 14
|
||||
#define A12_TMP_PID_COUNT 12
|
||||
|
||||
#endif /* a12creg_h_INCLUDED */
|
||||
|
||||
#define DIE() do { printf("Nice try file=%s line=%d\n", \
|
||||
__FILE__, __LINE__); panic("Nice try."); } while(0)
|
||||
#define What() printf("%s: line %d. What?\n", __FILE__, __LINE__)
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/* $NetBSD: a12cvar.h,v 1.1 1998/01/29 21:42:53 ross Exp $ */
|
||||
|
||||
/* [Notice revision 2.0]
|
||||
* Copyright (c) 1997 Avalon Computer Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Author: Ross Harvey
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright and
|
||||
* author notice, this list of conditions, and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* 4. This copyright will be assigned to The NetBSD Foundation on
|
||||
* 1/1/2000 unless these terms (including possibly the assignment
|
||||
* date) are updated in writing by Avalon prior to the latest specified
|
||||
* assignment date.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <dev/isa/isavar.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <alpha/pci/pci_sgmap_pte64.h>
|
||||
/*
|
||||
* A12 Core Logic -a12c- configuration.
|
||||
*/
|
||||
struct a12c_config {
|
||||
int ac_initted;
|
||||
|
||||
bus_space_tag_t ac_iot, ac_memt;
|
||||
struct alpha_pci_chipset ac_pc;
|
||||
|
||||
struct alpha_bus_dma_tag ac_dmat_direct;
|
||||
struct alpha_bus_dma_tag ac_dmat_sgmap;
|
||||
|
||||
struct alpha_sgmap ac_sgmap;
|
||||
|
||||
u_int32_t ac_hae_mem;
|
||||
u_int32_t ac_hae_io;
|
||||
|
||||
struct extent *ac_io_ex, *ac_d_mem_ex, *ac_s_mem_ex;
|
||||
int ac_mallocsafe;
|
||||
};
|
||||
|
||||
struct a12c_softc {
|
||||
struct device sc_dev;
|
||||
|
||||
struct a12c_config *sc_ccp;
|
||||
};
|
||||
|
||||
void a12c_init __P((struct a12c_config *, int));
|
||||
void a12c_pci_init __P((pci_chipset_tag_t, void *));
|
||||
void a12c_dma_init __P((struct a12c_config *));
|
||||
|
||||
bus_space_tag_t a12c_bus_io_init __P((void *));
|
||||
bus_space_tag_t a12c_bus_mem_init __P((void *));
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
/* $NetBSD: pci_a12.c,v 1.1 1998/01/29 21:42:53 ross Exp $ */
|
||||
|
||||
/* [Notice revision 2.0]
|
||||
* Copyright (c) 1997 Avalon Computer Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Author: Ross Harvey
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright and
|
||||
* author notice, this list of conditions, and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* 4. This copyright will be assigned to The NetBSD Foundation on
|
||||
* 1/1/2000 unless these terms (including possibly the assignment
|
||||
* date) are updated in writing by Avalon prior to the latest specified
|
||||
* assignment date.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "opt_avalon_a12.h" /* Config options headers */
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: pci_a12.c,v 1.1 1998/01/29 21:42:53 ross Exp $");
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/param.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/syslog.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
|
||||
#include <machine/autoconf.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
#include <alpha/pci/a12creg.h>
|
||||
#include <alpha/pci/a12cvar.h>
|
||||
|
||||
#include <alpha/pci/pci_a12.h>
|
||||
|
||||
#ifndef EVCNT_COUNTERS
|
||||
#include <machine/intrcnt.h>
|
||||
#endif
|
||||
|
||||
int avalon_a12_intr_map __P((void *, pcitag_t, int, int,
|
||||
pci_intr_handle_t *));
|
||||
const char *avalon_a12_intr_string __P((void *, pci_intr_handle_t));
|
||||
void *avalon_a12_intr_establish __P((void *, pci_intr_handle_t,
|
||||
int, int (*func)(void *), void *));
|
||||
void avalon_a12_intr_disestablish __P((void *, void *));
|
||||
|
||||
static void clear_gsr_interrupt __P((long));
|
||||
static void a12_pci_icall __P((int));
|
||||
static void pci_serr __P((int));
|
||||
static void a12_xbar_flag __P((int));
|
||||
static void a12_interval __P((int));
|
||||
static void a12_check_cdr __P((int));
|
||||
|
||||
#ifdef EVCNT_COUNTERS
|
||||
struct evcnt a12_intr_evcnt;
|
||||
#endif
|
||||
|
||||
static int (*a12_established_device) __P((void *));
|
||||
static void *ih_arg;
|
||||
|
||||
void a12_iointr __P((void *framep, unsigned long vec));
|
||||
|
||||
void
|
||||
pci_a12_pickintr(ccp)
|
||||
struct a12c_config *ccp;
|
||||
{
|
||||
pci_chipset_tag_t pc = &ccp->ac_pc;
|
||||
|
||||
pc->pc_intr_v = ccp;
|
||||
pc->pc_intr_map = avalon_a12_intr_map;
|
||||
pc->pc_intr_string = avalon_a12_intr_string;
|
||||
pc->pc_intr_establish = avalon_a12_intr_establish;
|
||||
pc->pc_intr_disestablish = avalon_a12_intr_disestablish;
|
||||
|
||||
set_iointr(a12_iointr);
|
||||
}
|
||||
|
||||
int
|
||||
avalon_a12_intr_map(ccv, bustag, buspin, line, ihp)
|
||||
void *ccv;
|
||||
pcitag_t bustag;
|
||||
int buspin, line;
|
||||
pci_intr_handle_t *ihp;
|
||||
{
|
||||
/* only one PCI slot (per CPU, that is, but there are 12 CPU's!) */
|
||||
*ihp = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char *
|
||||
avalon_a12_intr_string(ccv, ih)
|
||||
void *ccv;
|
||||
pci_intr_handle_t ih;
|
||||
{
|
||||
return "a12 pci irq"; /* see "only one" note above */
|
||||
}
|
||||
|
||||
void *
|
||||
avalon_a12_intr_establish(ccv, ih, level, func, arg)
|
||||
void *ccv, *arg;
|
||||
pci_intr_handle_t ih;
|
||||
int level;
|
||||
int (*func) __P((void *));
|
||||
{
|
||||
if(a12_established_device)
|
||||
panic("avalon_a12_intr_establish");
|
||||
a12_established_device = func;
|
||||
ih_arg = arg;
|
||||
REGVAL(A12_OMR) |= 1<<7;
|
||||
return (void *)func;
|
||||
}
|
||||
|
||||
void
|
||||
avalon_a12_intr_disestablish(ccv, cookie)
|
||||
void *ccv, *cookie;
|
||||
{
|
||||
if(cookie==a12_established_device)
|
||||
a12_established_device = 0;
|
||||
else What();
|
||||
}
|
||||
|
||||
long a12_nothing;
|
||||
|
||||
static void
|
||||
clear_gsr_interrupt(write_1_to_clear)
|
||||
long write_1_to_clear;
|
||||
{
|
||||
REGVAL(A12_GSR) = write_1_to_clear;
|
||||
alpha_mb();
|
||||
a12_nothing = REGVAL(A12_GSR);
|
||||
}
|
||||
|
||||
|
||||
static void a12_pci_icall(i)
|
||||
{
|
||||
if(a12_established_device) {
|
||||
(*a12_established_device)(ih_arg);
|
||||
return;
|
||||
}
|
||||
printf("PCI irq rcvd, but no handler established.\n");
|
||||
}
|
||||
|
||||
static void pci_serr(i) { panic("pci_serr"); }
|
||||
|
||||
static void a12_xbar_flag(i) { panic("a12_xbar_flag"); }
|
||||
|
||||
static void a12_interval(i) { panic("a12_interval"); }
|
||||
|
||||
static void a12_check_cdr(i)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
static struct gintcall {
|
||||
char flag;
|
||||
char needsclear;
|
||||
char intr_index; /* XXX implicit crossref */
|
||||
void (*f)(int);
|
||||
} gintcall[] = {
|
||||
{ 6, 0, 2, a12_pci_icall },
|
||||
{ 7, 1, 3, pci_serr },
|
||||
{ 8, 1, 4, a12_xbar_flag },
|
||||
{ 9, 1, 5, a12_xbar_flag },
|
||||
/* skip 10, gsr.TEI */
|
||||
{ 11, 1, 6, a12_interval },
|
||||
{ 12, 1, 7, a12_xbar_flag },
|
||||
{ 13, 1, 8, a12_xbar_flag },
|
||||
{ 14, 1, 9, a12_check_cdr },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static void a12_GInt(void);
|
||||
static void a12_GInt(void)
|
||||
{
|
||||
struct gintcall *gic;
|
||||
long gsrvalue = REGVAL(A12_GSR) & 0x7fc0;
|
||||
|
||||
for(gic=gintcall; gic->f; ++gic) {
|
||||
if(gsrvalue & 1L<<gic->flag) {
|
||||
#ifndef EVCNT_COUNTERS
|
||||
if (gic->intr_index >= INTRCNT_A12_IRQ_LEN)
|
||||
panic("A12 INTRCNT");
|
||||
intrcnt[INTRCNT_A12_IRQ + gic->intr_index];
|
||||
#endif
|
||||
if(gic->needsclear)
|
||||
clear_gsr_interrupt(1L<<gic->flag);
|
||||
(*gic->f)(gic->flag);
|
||||
alpha_wmb();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void a12_xbar_omchint(void);
|
||||
static void a12_xbar_omchint() { panic("a12_xbar_omchint"); };
|
||||
|
||||
static void a12_xbar_imchint(void);
|
||||
static void a12_xbar_imchint() { panic("a12_xbar_imchint"); };
|
||||
|
||||
void
|
||||
a12_iointr(framep, vec)
|
||||
void *framep;
|
||||
unsigned long vec;
|
||||
{
|
||||
unsigned irq = (vec-0x900) >> 4;
|
||||
/*
|
||||
* Xbar device is in the A12 CPU core logic, so its interrupts
|
||||
* might as well be hardwired.
|
||||
*/
|
||||
#ifdef EVCNT_COUNTERS
|
||||
++a12_intr_evcnt.ev_count;
|
||||
#else
|
||||
/* XXX implicit knowledge of intrcnt[] */
|
||||
if(irq < 2)
|
||||
++intrcnt[INTRCNT_A12_IRQ + irq];
|
||||
#if 2 >= INTRCNT_A12_IRQ_LEN
|
||||
#error INTRCNT_A12_IRQ_LEN inconsistent with respect to intrcnt[] use
|
||||
#endif
|
||||
#endif
|
||||
|
||||
switch(irq) {
|
||||
case 0:
|
||||
a12_xbar_omchint();
|
||||
return;
|
||||
case 1:
|
||||
a12_xbar_imchint();
|
||||
return;
|
||||
case 2:
|
||||
a12_GInt();
|
||||
return;
|
||||
default:
|
||||
panic("a12_iointr");
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* $NetBSD: pci_a12.h,v 1.1 1998/01/29 21:42:54 ross Exp $ */
|
||||
|
||||
/* [Notice revision 2.0]
|
||||
* Copyright (c) 1997 Avalon Computer Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Author: Ross Harvey
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright and
|
||||
* author notice, this list of conditions, and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* 4. This copyright will be assigned to The NetBSD Foundation on
|
||||
* 1/1/2000 unless these terms (including possibly the assignment
|
||||
* date) are updated in writing by Avalon prior to the latest specified
|
||||
* assignment date.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
void pci_a12_pickintr __P((struct a12c_config *));
|
||||
|
||||
#ifdef EVCNT_COUNTERS
|
||||
extern struct evcnt a12_intr_evcnt;
|
||||
#endif
|
||||
Loading…
Reference in New Issue