e3a3a9f56f
Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
2002-01-05 22:41:46 +00:00
826b7655cf
include <arm/conf.h> for prototypes.
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Correct args to mmopen and mmclose.
Add RCSID line.
2002-01-05 17:02:22 +00:00
b51b9e9e63
Update with radio, cir and irframe. also add block device for ld. Update other tables in file as appropriate.
2002-01-05 00:51:30 +00:00
9b812a6774
Update mem device to bring it into line with a change in version 1.32 of i386/mem.c. Appears that we may move uio twice.
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Original i386 log message:
Optimize the case of writing to /dev/zero, and clean up the
surrounding code a bit. Partly suggested by gwr.
I think this needs to be applied to arm26 as well.
2002-01-05 00:46:33 +00:00
e984bd475c
Initialize pba_intrswiz and pba_intrtag before configuring PCI bus.
2002-01-04 22:39:47 +00:00
e25a471c87
Fix typo in comment.
2002-01-01 16:24:33 +00:00
d2453f69b1
Remove the call to abort(). We don't pull in a prototype for it,
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and there's no sane way to do so.
2002-01-01 01:58:01 +00:00
00bd2cbdac
Merge ast() and userret() between arm32 and arm26. The implementation used
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is the arm32 one.
2001-12-21 22:56:16 +00:00
a6a5d9fa2b
Use the correct version of va_arg() for _STANDALONE.
2001-12-20 20:29:09 +00:00
a938f3a7ee
Remove some outdated comments: arm26 kernels use APCS-32 now, which
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means they don't do silly things like restoring IRQ/FIQ disable bits
on function return.
2001-12-20 16:12:10 +00:00
014157862c
* Share a common vector page between arm26 and arm32.
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* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.
2001-12-20 01:20:21 +00:00
631447bb4a
Change some #if 0 to #ifdef VERBOSE_INIT_ARM.
2001-12-18 02:52:00 +00:00
f2ebadcc6f
Ensure that vidc.h gets installed somewhere -- Xarm32vidc needs it to compile.
2001-12-17 15:07:37 +00:00
7bc474a92b
mod() was unused. g/c it. New code should use abs() anyway.
2001-12-15 22:41:44 +00:00
eefdf030c9
Simplify the pixel-clock-rate-setting code, so it always works out the
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parameters from first principles rather than using a static table for some
rates. This makes it work correctly on ARM7500, for which the table was
bogus (ARM7500 has a different refclk from VIDC20).
2001-12-15 22:21:46 +00:00
80e667c6ab
Add clockctl device.
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Note that someone needs to tidy this up, we've got 92 block devices, which just ain't true. Also appears we're actually missing some, eg the ld block device.
2001-12-11 00:34:50 +00:00
51535d4bf5
Add support for dumping ELF-cormat core files.
2001-12-09 23:05:56 +00:00
b45c51b1fc
Roll the rest of the ports over to the new MI kernel build machinery.
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Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
2001-12-09 05:00:40 +00:00
3831bfec98
Improve comment on the clockswitching asm code, it doesn't use r0 at all, it just needs it to make valid asm.
2001-12-08 21:30:04 +00:00
ce689bde4d
Fix the asm macros
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The tmpx registers are now outputs, this makes them all unique.
Add the fact that cc is changed by the asm (not believed to be used but rather be correct)
Correctly specify w as an input and output register, I think this was hiding the bug below!
Allow sum to be in a different input and output register.
Correct bug in psuedo header handling for in4_cksum. Seems that the new macros turned up a latent bug in the psuedo header handling, the code was moving a pointer forward 16 bytes twice, not found before as the ADD16 macro wasn't 100% accurate, as it didn't output w, even though it modified it.
2001-12-08 21:18:50 +00:00
72dee19a8c
Reset the i80200 ICU and PMU to a pristine state very early.
2001-12-01 23:06:45 +00:00
e4dac015cd
Don't define get_cachetype() unless it's going to be used.
2001-12-01 14:21:18 +00:00
3fd0a58e9d
On the i80200, disable ECC in the Bus Controller Unit early on; we
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don't really have code to deal with ECC errors yet.
2001-12-01 06:33:40 +00:00
5936a89bf5
Add register definitions for the i80200 Interrupt Controller Unit,
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Bus Controller Unit, and Performance Monitoring Unit.
2001-12-01 05:46:19 +00:00
2b08dcc43b
Clarify a comment to state that it is intentional that we attach
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only the Secondary PCI bus (it's the only bus which can have a
device space hidden from any PCI host on the Primary bus).
Also, use the bus number from the PPB businfo register seecondary bus
field rather than hard-coding "1".
2001-11-30 19:29:44 +00:00
e90eccc52c
Clarify a comment.
2001-11-30 19:26:03 +00:00
a2c8fc94fe
Provide a way for platforms to move away from the old RiscPC-centric
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interrupt code. Garbage-collect some unused stuff.
2001-11-29 17:14:02 +00:00
a93f7ef419
Provide a hook for platform-specific interrupt code to specify
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the "spl" cookie in the switch frame.
2001-11-29 17:12:22 +00:00
b0f775a467
Remove some overly-paranoid debug code that grovels too much
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platform-specific internals.
2001-11-29 17:10:31 +00:00
8ae5055ed9
Add routines for accessing the general purpose I/O facility of
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the i80312 Companion I/O chip.
2001-11-29 08:27:11 +00:00
574dba96b1
Update copyright.
2001-11-29 08:26:18 +00:00
c5ecb8d8c5
Use the new arm_dcache_align variable to set the PCI device BHLC
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register.
2001-11-29 02:26:50 +00:00
959181a8b2
Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
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processors. Report this when the processor is attached.
2001-11-29 02:24:58 +00:00
636e9cd08b
Add a "cacheline_size" argument to pci_configure_bus(). It is used
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to set the cacheline size in the BHLC register. This should be the
size of the largest D-cache line on a system.
2001-11-28 23:48:34 +00:00
85a1db0fda
Disable MRL, MRM, and MWI for now.
2001-11-28 22:39:09 +00:00
bd3e75a9df
Oops, make sure to add in the physical base of the PCI memory
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window when mapping PCI mem space. (Whee, I can take out my
local hack, now).
2001-11-28 21:08:47 +00:00
ecb81c3f6d
- convert usage of "defopt" to "defflag" where the relevant option does
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not support a value (e.g., it's to be used as "options FOO" instead of
"options FOO=xxx"). options that take a value were converted to
defparam recently.
- minor whitespace & formatting cleanups
2001-11-28 10:21:10 +00:00
379948c31f
- Garbage-collect some unused cruft.
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- When processing ASTs, restore interrupts *after* clearing astpending.
2001-11-28 01:06:19 +00:00
b9caa4cbc7
Don't grovel interrupt-related info here; if a platform wants to
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do that, let it do that in a way it can control.
2001-11-28 00:19:53 +00:00
a2fa0b1029
Add prototypes for new XScale write-through cache routines.
2001-11-28 00:18:46 +00:00
8e96318c12
Don't define interrupt handler-related offsets here.
2001-11-28 00:18:13 +00:00
28466919a2
Use <machine/intr.h> rather than <machine/irqhandler.h>
2001-11-27 01:03:52 +00:00
8cd82ab7b7
Move interrupt-related stuff out of the generic 32-bit ARM genassym.cf
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and into platform-specific genassym.cf files.
2001-11-27 00:15:58 +00:00
ed112809c9
Allow port-specific Makefile fragments to specify a list of additional
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genassym.cf fragments, if desired.
2001-11-26 23:44:58 +00:00
2d89f9075b
Move interrupt-related stuff out of stubs.c into intr.c.
2001-11-26 23:19:04 +00:00
bb706190b3
Add code to run the XScale cache in write-though mode, and do so
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for now...
2001-11-26 22:26:44 +00:00
0ca43a5fde
Use <arm/arm32/psl.h>, not <machine/psl.h>.
2001-11-26 20:51:57 +00:00
c8c624e4aa
Don't include <machine/psl.h> directly.
2001-11-26 20:49:04 +00:00
534b950d29
Move the interrupt-related file declarations into port-specific
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config descriptions so that each port choose whether or not to
use it.
2001-11-26 20:33:43 +00:00
8ec81cf263
Sprinkle CPWAIT around to enforce some barriers. Also deal with some
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pre-B-step errata: must clean-dcache-line to an address before
invalidate-dcache-line to that address, or the dirty bits will not
get cleanred in the dcache array for that line.
2001-11-26 18:09:08 +00:00
chris