2023-02-22 11:09:09 +03:00
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/* $NetBSD: brgphy.c,v 1.91 2023/02/22 08:09:09 msaitoh Exp $ */
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2001-06-01 20:49:59 +04:00
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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2010-12-10 02:25:49 +03:00
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* driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs.
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2001-06-01 20:49:59 +04:00
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*
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* Programming information for this PHY was gleaned from FreeBSD
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* (they were apparently able to get a datasheet from Broadcom).
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*/
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2001-11-13 10:38:28 +03:00
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#include <sys/cdefs.h>
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2023-02-22 11:09:09 +03:00
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__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.91 2023/02/22 08:09:09 msaitoh Exp $");
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2001-11-13 10:38:28 +03:00
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2001-06-01 20:49:59 +04:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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2009-04-23 14:47:43 +04:00
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#include <prop/proplib.h>
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2001-06-01 20:49:59 +04:00
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/brgphyreg.h>
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2009-04-19 15:10:36 +04:00
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#include <dev/pci/if_bgereg.h>
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#include <dev/pci/if_bnxreg.h>
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2008-05-04 21:06:09 +04:00
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static int brgphymatch(device_t, cfdata_t, void *);
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static void brgphyattach(device_t, device_t, void *);
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2001-06-01 20:49:59 +04:00
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2009-04-23 14:47:43 +04:00
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struct brgphy_softc {
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struct mii_softc sc_mii;
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2010-04-27 22:52:45 +04:00
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bool sc_isbge;
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bool sc_isbnx;
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2014-06-18 01:37:20 +04:00
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uint32_t sc_chipid; /* parent's chipid */
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uint32_t sc_phyflags; /* parent's phyflags */
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uint32_t sc_shared_hwcfg; /* shared hw config */
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uint32_t sc_port_hwcfg; /* port specific hw config */
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2009-04-23 14:47:43 +04:00
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};
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2020-03-28 21:37:18 +03:00
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CFATTACH_DECL_NEW(brgphy, sizeof(struct brgphy_softc),
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brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate);
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2001-06-01 20:49:59 +04:00
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2004-08-23 10:16:06 +04:00
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static int brgphy_service(struct mii_softc *, struct mii_data *, int);
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2014-06-18 01:37:20 +04:00
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static void brgphy_copper_status(struct mii_softc *);
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static void brgphy_fiber_status(struct mii_softc *);
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static void brgphy_5708s_status(struct mii_softc *);
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static void brgphy_5709s_status(struct mii_softc *);
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2007-03-10 12:13:07 +03:00
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static int brgphy_mii_phy_auto(struct mii_softc *);
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static void brgphy_loop(struct mii_softc *);
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2009-04-19 15:10:36 +04:00
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static void brgphy_reset(struct mii_softc *);
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static void brgphy_bcm5401_dspcode(struct mii_softc *);
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static void brgphy_bcm5411_dspcode(struct mii_softc *);
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static void brgphy_bcm5421_dspcode(struct mii_softc *);
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static void brgphy_bcm54k2_dspcode(struct mii_softc *);
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static void brgphy_adc_bug(struct mii_softc *);
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static void brgphy_5704_a0_bug(struct mii_softc *);
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static void brgphy_ber_bug(struct mii_softc *);
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static void brgphy_crc_bug(struct mii_softc *);
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2011-05-02 13:03:10 +04:00
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static void brgphy_disable_early_dac(struct mii_softc *);
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2010-01-24 19:26:09 +03:00
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static void brgphy_jumbo_settings(struct mii_softc *);
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static void brgphy_eth_wirespeed(struct mii_softc *);
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2020-05-25 22:48:38 +03:00
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static void brgphy_bcm54xx_clock_delay(struct mii_softc *);
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2002-07-13 05:23:27 +04:00
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2014-06-18 01:37:20 +04:00
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static const struct mii_phy_funcs brgphy_copper_funcs = {
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brgphy_service, brgphy_copper_status, brgphy_reset,
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};
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static const struct mii_phy_funcs brgphy_fiber_funcs = {
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brgphy_service, brgphy_fiber_status, brgphy_reset,
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};
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static const struct mii_phy_funcs brgphy_5708s_funcs = {
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brgphy_service, brgphy_5708s_status, brgphy_reset,
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};
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static const struct mii_phy_funcs brgphy_5709s_funcs = {
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brgphy_service, brgphy_5709s_status, brgphy_reset,
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2007-08-06 16:16:33 +04:00
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};
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2004-08-23 10:16:06 +04:00
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static const struct mii_phydesc brgphys[] = {
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(BROADCOM, BCM5400),
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MII_PHY_DESC(BROADCOM, BCM5401),
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2019-02-25 07:56:30 +03:00
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MII_PHY_DESC(BROADCOM, BCM5402),
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MII_PHY_DESC(BROADCOM, BCM5404),
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(BROADCOM, BCM5411),
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MII_PHY_DESC(BROADCOM, BCM5421),
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2019-02-25 07:56:30 +03:00
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MII_PHY_DESC(BROADCOM, BCM5424),
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(BROADCOM, BCM5461),
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2019-02-25 07:56:30 +03:00
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MII_PHY_DESC(BROADCOM, BCM5462),
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(BROADCOM, BCM5464),
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2019-02-25 07:56:30 +03:00
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MII_PHY_DESC(BROADCOM, BCM5466),
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MII_PHY_DESC(BROADCOM, BCM54K2),
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(BROADCOM, BCM5701),
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MII_PHY_DESC(BROADCOM, BCM5703),
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MII_PHY_DESC(BROADCOM, BCM5704),
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MII_PHY_DESC(BROADCOM, BCM5705),
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MII_PHY_DESC(BROADCOM, BCM5706),
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MII_PHY_DESC(BROADCOM, BCM5714),
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MII_PHY_DESC(BROADCOM, BCM5750),
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MII_PHY_DESC(BROADCOM, BCM5752),
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MII_PHY_DESC(BROADCOM, BCM5780),
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MII_PHY_DESC(BROADCOM, BCM5708C),
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MII_PHY_DESC(BROADCOM2, BCM5481),
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MII_PHY_DESC(BROADCOM2, BCM5482),
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MII_PHY_DESC(BROADCOM2, BCM5708S),
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MII_PHY_DESC(BROADCOM2, BCM5709C),
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MII_PHY_DESC(BROADCOM2, BCM5709S),
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MII_PHY_DESC(BROADCOM2, BCM5709CAX),
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MII_PHY_DESC(BROADCOM2, BCM5722),
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MII_PHY_DESC(BROADCOM2, BCM5754),
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MII_PHY_DESC(BROADCOM2, BCM5755),
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MII_PHY_DESC(BROADCOM2, BCM5756),
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MII_PHY_DESC(BROADCOM2, BCM5761),
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MII_PHY_DESC(BROADCOM2, BCM5784),
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MII_PHY_DESC(BROADCOM2, BCM5785),
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MII_PHY_DESC(BROADCOM3, BCM5717C),
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MII_PHY_DESC(BROADCOM3, BCM5719C),
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MII_PHY_DESC(BROADCOM3, BCM5720C),
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MII_PHY_DESC(BROADCOM3, BCM57765),
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MII_PHY_DESC(BROADCOM3, BCM57780),
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2020-02-22 21:57:31 +03:00
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MII_PHY_DESC(BROADCOM4, BCM54213PE),
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(BROADCOM4, BCM5725C),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
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MII_PHY_END,
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2001-06-01 20:49:59 +04:00
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};
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2004-08-23 10:16:06 +04:00
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static int
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2009-06-17 19:43:16 +04:00
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brgphymatch(device_t parent, cfdata_t match, void *aux)
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2001-06-01 20:49:59 +04:00
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{
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struct mii_attach_args *ma = aux;
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2001-06-03 01:39:38 +04:00
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if (mii_phy_match(ma, brgphys) != NULL)
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2019-03-25 12:20:46 +03:00
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return 10;
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2001-06-01 20:49:59 +04:00
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2019-03-25 12:20:46 +03:00
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return 0;
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2001-06-01 20:49:59 +04:00
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}
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2004-08-23 10:16:06 +04:00
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static void
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2009-05-12 18:28:22 +04:00
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brgphyattach(device_t parent, device_t self, void *aux)
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2001-06-01 20:49:59 +04:00
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{
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2009-04-23 14:47:43 +04:00
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struct brgphy_softc *bsc = device_private(self);
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struct mii_softc *sc = &bsc->sc_mii;
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2001-06-01 20:49:59 +04:00
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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2001-06-03 01:39:38 +04:00
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const struct mii_phydesc *mpd;
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2009-04-23 14:47:43 +04:00
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prop_dictionary_t dict;
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2001-06-01 20:49:59 +04:00
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2001-06-03 01:39:38 +04:00
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mpd = mii_phy_match(ma, brgphys);
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2003-04-29 05:49:33 +04:00
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aprint_naive(": Media interface\n");
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
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2001-06-01 20:49:59 +04:00
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2008-05-04 21:06:09 +04:00
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sc->mii_dev = self;
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2001-06-01 20:49:59 +04:00
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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2013-03-15 10:18:13 +04:00
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sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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2007-03-10 12:13:07 +03:00
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sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
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2009-04-19 15:10:36 +04:00
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sc->mii_mpd_rev = MII_REV(ma->mii_id2);
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2001-06-01 20:49:59 +04:00
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sc->mii_pdata = mii;
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2002-03-25 23:51:24 +03:00
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sc->mii_flags = ma->mii_flags;
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2002-07-13 05:23:27 +04:00
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2011-05-02 13:03:10 +04:00
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if (device_is_a(parent, "bge"))
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2010-04-27 22:52:45 +04:00
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bsc->sc_isbge = true;
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2011-05-02 13:03:10 +04:00
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else if (device_is_a(parent, "bnx"))
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2010-04-27 22:52:45 +04:00
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bsc->sc_isbnx = true;
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2011-05-02 13:03:10 +04:00
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2014-06-18 10:35:19 +04:00
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dict = device_properties(parent);
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2011-05-02 13:03:10 +04:00
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if (bsc->sc_isbge || bsc->sc_isbnx) {
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2010-12-10 02:25:49 +03:00
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if (!prop_dictionary_get_uint32(dict, "phyflags",
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2011-05-02 13:03:10 +04:00
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&bsc->sc_phyflags))
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aprint_error_dev(self, "failed to get phyflags\n");
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if (!prop_dictionary_get_uint32(dict, "chipid",
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&bsc->sc_chipid))
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aprint_error_dev(self, "failed to get chipid\n");
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2009-04-23 14:47:43 +04:00
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}
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2010-12-10 02:25:49 +03:00
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2014-06-18 01:37:20 +04:00
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if (bsc->sc_isbnx) {
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/* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */
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if (!prop_dictionary_get_uint32(dict, "shared_hwcfg",
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&bsc->sc_shared_hwcfg))
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aprint_error_dev(self, "failed to get shared_hwcfg\n");
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if (!prop_dictionary_get_uint32(dict, "port_hwcfg",
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&bsc->sc_port_hwcfg))
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aprint_error_dev(self, "failed to get port_hwcfg\n");
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}
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if (sc->mii_flags & MIIF_HAVEFIBER) {
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2014-07-03 02:01:44 +04:00
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if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
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&& sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S)
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2014-06-18 01:37:20 +04:00
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sc->mii_funcs = &brgphy_5708s_funcs;
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2014-07-03 02:01:44 +04:00
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else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
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2014-07-03 02:21:50 +04:00
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&& (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) {
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if (bsc->sc_isbnx)
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sc->mii_funcs = &brgphy_5709s_funcs;
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else {
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/*
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* XXX
|
|
|
|
* 5720S and 5709S shares the same PHY id.
|
|
|
|
* Assume 5720S PHY if parent device is bge(4).
|
|
|
|
*/
|
|
|
|
sc->mii_funcs = &brgphy_5708s_funcs;
|
|
|
|
}
|
|
|
|
} else
|
2014-06-18 01:37:20 +04:00
|
|
|
sc->mii_funcs = &brgphy_fiber_funcs;
|
|
|
|
} else
|
|
|
|
sc->mii_funcs = &brgphy_copper_funcs;
|
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
mii_lock(mii);
|
|
|
|
|
2013-04-01 17:41:37 +04:00
|
|
|
PHY_RESET(sc);
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
|
|
|
|
sc->mii_capabilities &= ma->mii_capmask;
|
2013-04-01 17:41:37 +04:00
|
|
|
if (sc->mii_capabilities & BMSR_EXTSTAT)
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
|
2013-04-01 17:41:37 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
mii_unlock(mii);
|
|
|
|
|
2014-07-03 02:21:50 +04:00
|
|
|
if (sc->mii_flags & MIIF_HAVEFIBER) {
|
2020-03-16 02:04:50 +03:00
|
|
|
mii_lock(mii);
|
2014-07-03 02:21:50 +04:00
|
|
|
sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the proper bits for capabilities so that the
|
|
|
|
* correct media get selected by mii_phy_add_media()
|
|
|
|
*/
|
|
|
|
sc->mii_capabilities |= BMSR_ANEG;
|
|
|
|
sc->mii_capabilities &= ~BMSR_100T4;
|
|
|
|
sc->mii_extcapabilities |= EXTSR_1000XFDX;
|
2020-03-16 02:04:50 +03:00
|
|
|
mii_unlock(mii);
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-07-03 02:21:50 +04:00
|
|
|
if (bsc->sc_isbnx) {
|
2010-12-10 02:25:49 +03:00
|
|
|
/*
|
2014-07-03 02:21:50 +04:00
|
|
|
* 2.5Gb support is a software enabled feature
|
|
|
|
* on the BCM5708S and BCM5709S controllers.
|
2010-12-10 02:25:49 +03:00
|
|
|
*/
|
|
|
|
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
|
2014-07-03 02:21:50 +04:00
|
|
|
if (bsc->sc_phyflags
|
|
|
|
& BNX_PHY_2_5G_CAPABLE_FLAG) {
|
|
|
|
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX,
|
|
|
|
IFM_FDX, sc->mii_inst), 0);
|
2019-11-27 13:19:20 +03:00
|
|
|
aprint_normal_dev(self, "2500baseSX-FDX\n");
|
2010-12-10 02:25:49 +03:00
|
|
|
#undef ADD
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-07-03 02:21:50 +04:00
|
|
|
mii_phy_add_media(sc);
|
2001-06-01 20:49:59 +04:00
|
|
|
}
|
|
|
|
|
2004-08-23 10:16:06 +04:00
|
|
|
static int
|
2001-08-25 22:04:01 +04:00
|
|
|
brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
2001-06-01 20:49:59 +04:00
|
|
|
{
|
|
|
|
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t reg, speed, gig;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2001-06-01 20:49:59 +04:00
|
|
|
switch (cmd) {
|
|
|
|
case MII_POLLSTAT:
|
2014-07-03 01:51:36 +04:00
|
|
|
/* If we're not polling our PHY instance, just return. */
|
2001-06-01 20:49:59 +04:00
|
|
|
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
2019-03-25 12:20:46 +03:00
|
|
|
return 0;
|
2001-06-01 20:49:59 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MII_MEDIACHG:
|
|
|
|
/*
|
|
|
|
* If the media indicates a different PHY instance,
|
|
|
|
* isolate ourselves.
|
|
|
|
*/
|
|
|
|
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, ®);
|
2001-06-01 20:49:59 +04:00
|
|
|
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
2019-03-25 12:20:46 +03:00
|
|
|
return 0;
|
2001-06-01 20:49:59 +04:00
|
|
|
}
|
|
|
|
|
2014-07-03 01:51:36 +04:00
|
|
|
/* If the interface is not up, don't do anything. */
|
2001-06-01 20:49:59 +04:00
|
|
|
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
|
|
|
break;
|
|
|
|
|
2007-03-10 12:13:07 +03:00
|
|
|
PHY_RESET(sc); /* XXX hardware bug work-around */
|
|
|
|
|
|
|
|
switch (IFM_SUBTYPE(ife->ifm_media)) {
|
|
|
|
case IFM_AUTO:
|
|
|
|
(void) brgphy_mii_phy_auto(sc);
|
|
|
|
break;
|
2014-06-18 01:37:20 +04:00
|
|
|
case IFM_2500_SX:
|
|
|
|
speed = BRGPHY_5708S_BMCR_2500;
|
|
|
|
goto setit;
|
|
|
|
case IFM_1000_SX:
|
2007-03-10 12:13:07 +03:00
|
|
|
case IFM_1000_T:
|
|
|
|
speed = BMCR_S1000;
|
|
|
|
goto setit;
|
|
|
|
case IFM_100_TX:
|
|
|
|
speed = BMCR_S100;
|
|
|
|
goto setit;
|
|
|
|
case IFM_10_T:
|
|
|
|
speed = BMCR_S10;
|
|
|
|
setit:
|
|
|
|
brgphy_loop(sc);
|
2019-04-11 11:50:20 +03:00
|
|
|
if ((ife->ifm_media & IFM_FDX) != 0) {
|
2007-03-10 12:13:07 +03:00
|
|
|
speed |= BMCR_FDX;
|
|
|
|
gig = GTCR_ADV_1000TFDX;
|
2014-06-12 16:09:47 +04:00
|
|
|
} else
|
2007-03-10 12:13:07 +03:00
|
|
|
gig = GTCR_ADV_1000THDX;
|
|
|
|
|
|
|
|
PHY_WRITE(sc, MII_100T2CR, 0);
|
|
|
|
PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
|
2009-11-19 02:02:12 +03:00
|
|
|
PHY_WRITE(sc, MII_BMCR, speed);
|
2007-03-10 12:13:07 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) &&
|
|
|
|
(IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) &&
|
|
|
|
(IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX))
|
2007-03-10 12:13:07 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
PHY_WRITE(sc, MII_100T2CR, gig);
|
|
|
|
PHY_WRITE(sc, MII_BMCR,
|
2013-06-14 10:21:51 +04:00
|
|
|
speed | BMCR_AUTOEN | BMCR_STARTNEG);
|
2007-03-10 12:13:07 +03:00
|
|
|
|
2013-03-15 10:18:13 +04:00
|
|
|
if ((sc->mii_mpd_oui != MII_OUI_BROADCOM)
|
|
|
|
|| (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701))
|
2007-03-13 09:41:52 +03:00
|
|
|
break;
|
2007-03-10 12:13:07 +03:00
|
|
|
|
|
|
|
if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
|
|
|
|
gig |= GTCR_MAN_MS | GTCR_ADV_MS;
|
|
|
|
PHY_WRITE(sc, MII_100T2CR, gig);
|
|
|
|
break;
|
|
|
|
default:
|
2019-03-25 12:20:46 +03:00
|
|
|
return EINVAL;
|
2007-03-10 12:13:07 +03:00
|
|
|
}
|
2001-06-01 20:49:59 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MII_TICK:
|
2014-07-03 01:51:36 +04:00
|
|
|
/* If we're not currently selected, just return. */
|
2001-06-01 20:49:59 +04:00
|
|
|
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
2019-03-25 12:20:46 +03:00
|
|
|
return 0;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-07-03 01:51:36 +04:00
|
|
|
/* Is the interface even up? */
|
2013-06-21 08:25:51 +04:00
|
|
|
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
|
|
|
return 0;
|
|
|
|
|
2014-07-03 01:51:36 +04:00
|
|
|
/* Only used for autonegotiation. */
|
2013-06-21 08:25:51 +04:00
|
|
|
if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
|
|
|
|
(IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
|
|
|
|
sc->mii_ticks = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for link.
|
|
|
|
* Read the status register twice; BMSR_LINK is latch-low.
|
|
|
|
*/
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, ®);
|
|
|
|
PHY_READ(sc, MII_BMSR, ®);
|
2013-06-21 08:25:51 +04:00
|
|
|
if (reg & BMSR_LINK) {
|
|
|
|
sc->mii_ticks = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* mii_ticks == 0 means it's the first tick after changing the
|
|
|
|
* media or the link became down since the last tick
|
|
|
|
* (see above), so break to update the status.
|
|
|
|
*/
|
|
|
|
if (sc->mii_ticks++ == 0)
|
|
|
|
break;
|
|
|
|
|
2014-07-03 01:51:36 +04:00
|
|
|
/* Only retry autonegotiation every mii_anegticks seconds. */
|
2013-06-21 08:25:51 +04:00
|
|
|
KASSERT(sc->mii_anegticks != 0);
|
2023-02-22 11:09:09 +03:00
|
|
|
if (sc->mii_ticks < sc->mii_anegticks)
|
2013-06-21 08:25:51 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
brgphy_mii_phy_auto(sc);
|
2001-06-01 20:49:59 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MII_DOWN:
|
|
|
|
mii_phy_down(sc);
|
2019-03-25 12:20:46 +03:00
|
|
|
return 0;
|
2001-06-01 20:49:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Update the media status. */
|
|
|
|
mii_phy_status(sc);
|
|
|
|
|
2002-07-13 05:23:27 +04:00
|
|
|
/*
|
2007-03-10 12:13:07 +03:00
|
|
|
* Callback if something changed. Note that we need to poke the DSP on
|
|
|
|
* the Broadcom PHYs if the media changes.
|
2002-07-13 05:23:27 +04:00
|
|
|
*/
|
2005-02-27 03:26:58 +03:00
|
|
|
if (sc->mii_media_active != mii->mii_media_active ||
|
2002-07-13 05:23:27 +04:00
|
|
|
sc->mii_media_status != mii->mii_media_status ||
|
|
|
|
cmd == MII_MEDIACHG) {
|
2013-03-15 10:18:13 +04:00
|
|
|
switch (sc->mii_mpd_oui) {
|
|
|
|
case MII_OUI_BROADCOM:
|
|
|
|
switch (sc->mii_mpd_model) {
|
|
|
|
case MII_MODEL_BROADCOM_BCM5400:
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_bcm5401_dspcode(sc);
|
2013-03-15 10:18:13 +04:00
|
|
|
break;
|
|
|
|
case MII_MODEL_BROADCOM_BCM5401:
|
|
|
|
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
|
|
|
|
brgphy_bcm5401_dspcode(sc);
|
|
|
|
break;
|
|
|
|
case MII_MODEL_BROADCOM_BCM5411:
|
|
|
|
brgphy_bcm5411_dspcode(sc);
|
|
|
|
break;
|
|
|
|
}
|
2009-04-19 15:10:36 +04:00
|
|
|
break;
|
2020-05-25 22:48:38 +03:00
|
|
|
case MII_OUI_BROADCOM4:
|
|
|
|
switch (sc->mii_mpd_model) {
|
|
|
|
case MII_MODEL_BROADCOM4_BCM54213PE:
|
|
|
|
brgphy_bcm54xx_clock_delay(sc);
|
|
|
|
break;
|
|
|
|
}
|
2009-04-19 15:10:36 +04:00
|
|
|
}
|
2002-07-13 05:23:27 +04:00
|
|
|
}
|
2009-04-19 15:10:36 +04:00
|
|
|
|
|
|
|
/* Callback if something changed. */
|
|
|
|
mii_phy_update(sc, cmd);
|
2019-03-25 12:20:46 +03:00
|
|
|
return 0;
|
2001-06-01 20:49:59 +04:00
|
|
|
}
|
|
|
|
|
2004-08-23 10:16:06 +04:00
|
|
|
static void
|
2014-06-18 01:37:20 +04:00
|
|
|
brgphy_copper_status(struct mii_softc *sc)
|
2001-06-01 20:49:59 +04:00
|
|
|
{
|
|
|
|
struct mii_data *mii = sc->mii_pdata;
|
|
|
|
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmcr, bmsr, auxsts, gtsr;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2001-06-01 20:49:59 +04:00
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
2010-12-10 02:25:49 +03:00
|
|
|
if (bmsr & BMSR_LINK)
|
2001-06-01 20:49:59 +04:00
|
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2001-06-01 20:49:59 +04:00
|
|
|
if (bmcr & BMCR_ISO) {
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bmcr & BMCR_LOOP)
|
|
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
|
|
|
|
|
|
if (bmcr & BMCR_AUTOEN) {
|
|
|
|
/*
|
2019-11-26 11:21:03 +03:00
|
|
|
* The media status bits are only valid if autonegotiation
|
2001-06-01 20:49:59 +04:00
|
|
|
* has completed (or it's disabled).
|
|
|
|
*/
|
2010-12-10 02:25:49 +03:00
|
|
|
if ((bmsr & BMSR_ACOMP) == 0) {
|
2001-06-01 20:49:59 +04:00
|
|
|
/* Erg, still trying, I guess... */
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts);
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
|
|
|
|
case BRGPHY_RES_1000FD:
|
|
|
|
mii->mii_media_active |= IFM_1000_T | IFM_FDX;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_100T2SR, >sr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (gtsr & GTSR_MS_RES)
|
|
|
|
mii->mii_media_active |= IFM_ETH_MASTER;
|
|
|
|
break;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
case BRGPHY_RES_1000HD:
|
|
|
|
mii->mii_media_active |= IFM_1000_T | IFM_HDX;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_100T2SR, >sr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (gtsr & GTSR_MS_RES)
|
|
|
|
mii->mii_media_active |= IFM_ETH_MASTER;
|
|
|
|
break;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
case BRGPHY_RES_100FD:
|
|
|
|
mii->mii_media_active |= IFM_100_TX | IFM_FDX;
|
|
|
|
break;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
case BRGPHY_RES_100T4:
|
|
|
|
mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
|
|
|
|
break;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
case BRGPHY_RES_100HD:
|
|
|
|
mii->mii_media_active |= IFM_100_TX | IFM_HDX;
|
|
|
|
break;
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
case BRGPHY_RES_10FD:
|
|
|
|
mii->mii_media_active |= IFM_10_T | IFM_FDX;
|
|
|
|
break;
|
2001-06-01 20:49:59 +04:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
case BRGPHY_RES_10HD:
|
|
|
|
mii->mii_media_active |= IFM_10_T | IFM_HDX;
|
|
|
|
break;
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
default:
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
}
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
if (mii->mii_media_active & IFM_FDX)
|
|
|
|
mii->mii_media_active |= mii_phy_flowstatus(sc);
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
} else
|
|
|
|
mii->mii_media_active = ife->ifm_media;
|
|
|
|
}
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
void
|
|
|
|
brgphy_fiber_status(struct mii_softc *sc)
|
|
|
|
{
|
|
|
|
struct mii_data *mii = sc->mii_pdata;
|
|
|
|
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmcr, bmsr, anar, anlpar, result;
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (bmsr & BMSR_LINK)
|
|
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (bmcr & BMCR_LOOP)
|
|
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
|
|
|
|
|
|
if (bmcr & BMCR_AUTOEN) {
|
|
|
|
if ((bmsr & BMSR_ACOMP) == 0) {
|
|
|
|
/* Erg, still trying, I guess... */
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_ANAR, &anar);
|
|
|
|
PHY_READ(sc, MII_ANLPAR, &anlpar);
|
|
|
|
result = anar & anlpar;
|
2014-06-18 01:37:20 +04:00
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
if (result & ANAR_X_FD)
|
2014-06-18 01:37:20 +04:00
|
|
|
mii->mii_media_active |= IFM_FDX;
|
|
|
|
else
|
|
|
|
mii->mii_media_active |= IFM_HDX;
|
|
|
|
|
|
|
|
if (mii->mii_media_active & IFM_FDX)
|
|
|
|
mii->mii_media_active |= mii_phy_flowstatus(sc);
|
|
|
|
} else
|
|
|
|
mii->mii_media_active = ife->ifm_media;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
brgphy_5708s_status(struct mii_softc *sc)
|
|
|
|
{
|
|
|
|
struct mii_data *mii = sc->mii_pdata;
|
|
|
|
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmcr, bmsr;
|
2014-06-18 01:37:20 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (bmsr & BMSR_LINK)
|
|
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (bmcr & BMCR_LOOP)
|
|
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
|
|
|
|
|
|
if (bmcr & BMCR_AUTOEN) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t xstat;
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
if ((bmsr & BMSR_ACOMP) == 0) {
|
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
|
|
BRGPHY_5708S_DIG_PG0);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
|
2014-06-18 01:37:20 +04:00
|
|
|
if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) {
|
|
|
|
/* Erg, still trying, I guess... */
|
2010-12-10 02:25:49 +03:00
|
|
|
mii->mii_media_active |= IFM_NONE;
|
2014-06-18 01:37:20 +04:00
|
|
|
return;
|
2010-12-10 02:25:49 +03:00
|
|
|
}
|
2001-06-01 20:49:59 +04:00
|
|
|
}
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
|
|
BRGPHY_5708S_DIG_PG0);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
|
2014-06-18 01:37:20 +04:00
|
|
|
|
|
|
|
switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
|
|
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
|
|
|
|
mii->mii_media_active |= IFM_10_FL;
|
|
|
|
break;
|
|
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
|
|
|
|
mii->mii_media_active |= IFM_100_FX;
|
|
|
|
break;
|
|
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
|
|
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
break;
|
|
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
|
|
|
|
mii->mii_media_active |= IFM_2500_SX;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
|
|
|
|
mii->mii_media_active |= IFM_FDX;
|
|
|
|
else
|
|
|
|
mii->mii_media_active |= IFM_HDX;
|
|
|
|
|
|
|
|
if (mii->mii_media_active & IFM_FDX) {
|
|
|
|
if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE)
|
2019-03-25 12:20:46 +03:00
|
|
|
mii->mii_media_active
|
|
|
|
|= IFM_FLOW | IFM_ETH_TXPAUSE;
|
2014-06-18 01:37:20 +04:00
|
|
|
if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE)
|
2019-03-25 12:20:46 +03:00
|
|
|
mii->mii_media_active
|
|
|
|
|= IFM_FLOW | IFM_ETH_RXPAUSE;
|
2014-06-18 01:37:20 +04:00
|
|
|
}
|
|
|
|
} else
|
|
|
|
mii->mii_media_active = ife->ifm_media;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
brgphy_5709s_status(struct mii_softc *sc)
|
|
|
|
{
|
|
|
|
struct mii_data *mii = sc->mii_pdata;
|
|
|
|
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmcr, bmsr, auxsts;
|
2014-06-18 01:37:20 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2014-06-18 01:37:20 +04:00
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (bmsr & BMSR_LINK)
|
|
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2014-06-18 01:37:20 +04:00
|
|
|
if (bmcr & BMCR_ISO) {
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bmcr & BMCR_LOOP)
|
|
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
|
|
|
|
|
|
if (bmcr & BMCR_AUTOEN) {
|
|
|
|
/*
|
|
|
|
* The media status bits are only valid of autonegotiation
|
|
|
|
* has completed (or it's disabled).
|
|
|
|
*/
|
|
|
|
if ((bmsr & BMSR_ACOMP) == 0) {
|
|
|
|
/* Erg, still trying, I guess... */
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 5709S has its own general purpose status registers */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
|
|
|
|
PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts);
|
2014-06-18 01:37:20 +04:00
|
|
|
|
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
|
|
|
|
BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
|
|
|
|
|
|
|
|
switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
|
|
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
|
|
|
|
mii->mii_media_active |= IFM_10_FL;
|
|
|
|
break;
|
|
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
|
|
|
|
mii->mii_media_active |= IFM_100_FX;
|
|
|
|
break;
|
|
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
|
|
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
break;
|
|
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
|
|
|
|
mii->mii_media_active |= IFM_2500_SX;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
|
|
|
|
mii->mii_media_active |= IFM_FDX;
|
|
|
|
else
|
|
|
|
mii->mii_media_active |= IFM_HDX;
|
|
|
|
|
2004-04-10 22:47:56 +04:00
|
|
|
if (mii->mii_media_active & IFM_FDX)
|
2004-04-11 19:40:56 +04:00
|
|
|
mii->mii_media_active |= mii_phy_flowstatus(sc);
|
2001-06-01 20:49:59 +04:00
|
|
|
} else
|
|
|
|
mii->mii_media_active = ife->ifm_media;
|
|
|
|
}
|
2002-07-13 05:23:27 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
static int
|
2007-03-10 12:13:07 +03:00
|
|
|
brgphy_mii_phy_auto(struct mii_softc *sc)
|
|
|
|
{
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t anar, ktcr = 0;
|
2007-03-10 12:13:07 +03:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(sc->mii_pdata));
|
|
|
|
|
2013-06-06 07:10:48 +04:00
|
|
|
sc->mii_ticks = 0;
|
2007-03-10 12:13:07 +03:00
|
|
|
brgphy_loop(sc);
|
|
|
|
PHY_RESET(sc);
|
2010-12-10 02:25:49 +03:00
|
|
|
|
|
|
|
if (sc->mii_flags & MIIF_HAVEFIBER) {
|
|
|
|
anar = ANAR_X_FD | ANAR_X_HD;
|
|
|
|
if (sc->mii_flags & MIIF_DOPAUSE)
|
2014-06-12 16:09:47 +04:00
|
|
|
anar |= ANAR_X_PAUSE_TOWARDS;
|
2010-12-10 02:25:49 +03:00
|
|
|
} else {
|
|
|
|
anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
|
|
|
|
if (sc->mii_flags & MIIF_DOPAUSE)
|
2013-06-16 10:29:08 +04:00
|
|
|
anar |= ANAR_FC | ANAR_PAUSE_ASYM;
|
2014-06-18 01:37:20 +04:00
|
|
|
ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
|
|
|
|
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
|
|
|
|
&& (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701))
|
|
|
|
ktcr |= GTCR_MAN_MS | GTCR_ADV_MS;
|
|
|
|
PHY_WRITE(sc, MII_100T2CR, ktcr);
|
2010-12-10 02:25:49 +03:00
|
|
|
}
|
2007-03-10 12:13:07 +03:00
|
|
|
PHY_WRITE(sc, MII_ANAR, anar);
|
2010-12-10 02:25:49 +03:00
|
|
|
|
|
|
|
/* Start autonegotiation */
|
2014-06-12 16:09:47 +04:00
|
|
|
PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
|
2007-03-10 12:13:07 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
|
|
|
|
|
2019-03-25 12:20:46 +03:00
|
|
|
return EJUSTRETURN;
|
2007-03-10 12:13:07 +03:00
|
|
|
}
|
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
static void
|
2007-03-10 12:13:07 +03:00
|
|
|
brgphy_loop(struct mii_softc *sc)
|
|
|
|
{
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmsr;
|
2007-03-10 12:13:07 +03:00
|
|
|
int i;
|
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(sc->mii_pdata));
|
|
|
|
|
2007-03-10 12:13:07 +03:00
|
|
|
PHY_WRITE(sc, MII_BMCR, BMCR_LOOP);
|
2007-03-13 09:41:52 +03:00
|
|
|
for (i = 0; i < 15000; i++) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
2007-03-10 12:13:07 +03:00
|
|
|
if (!(bmsr & BMSR_LINK))
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-08-23 10:16:06 +04:00
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_reset(struct mii_softc *sc)
|
2002-07-13 05:23:27 +04:00
|
|
|
{
|
2010-11-27 20:42:04 +03:00
|
|
|
struct brgphy_softc *bsc = device_private(sc->mii_dev);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t reg;
|
2002-07-13 05:23:27 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(sc->mii_pdata));
|
|
|
|
|
2002-07-13 05:23:27 +04:00
|
|
|
mii_phy_reset(sc);
|
2013-03-15 10:18:13 +04:00
|
|
|
switch (sc->mii_mpd_oui) {
|
|
|
|
case MII_OUI_BROADCOM:
|
|
|
|
switch (sc->mii_mpd_model) {
|
|
|
|
case MII_MODEL_BROADCOM_BCM5400:
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_bcm5401_dspcode(sc);
|
2013-03-15 10:18:13 +04:00
|
|
|
break;
|
|
|
|
case MII_MODEL_BROADCOM_BCM5401:
|
|
|
|
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
|
|
|
|
brgphy_bcm5401_dspcode(sc);
|
|
|
|
break;
|
|
|
|
case MII_MODEL_BROADCOM_BCM5411:
|
|
|
|
brgphy_bcm5411_dspcode(sc);
|
|
|
|
break;
|
|
|
|
case MII_MODEL_BROADCOM_BCM5421:
|
|
|
|
brgphy_bcm5421_dspcode(sc);
|
|
|
|
break;
|
|
|
|
case MII_MODEL_BROADCOM_BCM54K2:
|
|
|
|
brgphy_bcm54k2_dspcode(sc);
|
|
|
|
break;
|
|
|
|
}
|
2009-04-19 15:10:36 +04:00
|
|
|
break;
|
2013-03-15 10:18:13 +04:00
|
|
|
case MII_OUI_BROADCOM3:
|
|
|
|
switch (sc->mii_mpd_model) {
|
|
|
|
case MII_MODEL_BROADCOM3_BCM5717C:
|
|
|
|
case MII_MODEL_BROADCOM3_BCM5719C:
|
|
|
|
case MII_MODEL_BROADCOM3_BCM5720C:
|
|
|
|
case MII_MODEL_BROADCOM3_BCM57765:
|
|
|
|
return;
|
|
|
|
}
|
2009-04-19 15:10:36 +04:00
|
|
|
break;
|
2013-03-15 10:18:13 +04:00
|
|
|
default:
|
2009-04-19 15:10:36 +04:00
|
|
|
break;
|
|
|
|
}
|
2003-01-16 21:43:40 +03:00
|
|
|
|
2009-04-19 15:10:36 +04:00
|
|
|
/* Handle any bge (NetXtreme/NetLink) workarounds. */
|
2010-04-27 22:52:45 +04:00
|
|
|
if (bsc->sc_isbge) {
|
2009-04-19 15:10:36 +04:00
|
|
|
if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
|
|
|
|
|
2013-10-31 08:26:40 +04:00
|
|
|
if (bsc->sc_phyflags & BGEPHYF_ADC_BUG)
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_adc_bug(sc);
|
2013-10-31 08:26:40 +04:00
|
|
|
if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG)
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_5704_a0_bug(sc);
|
2013-10-31 08:26:40 +04:00
|
|
|
if (bsc->sc_phyflags & BGEPHYF_BER_BUG)
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_ber_bug(sc);
|
2013-10-31 08:26:40 +04:00
|
|
|
else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) {
|
2009-04-19 15:10:36 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
|
2009-04-19 15:10:36 +04:00
|
|
|
|
2019-01-08 06:14:51 +03:00
|
|
|
if (bsc->sc_phyflags
|
2013-10-31 08:26:40 +04:00
|
|
|
& BGEPHYF_ADJUST_TRIM) {
|
2009-04-19 15:10:36 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
|
|
|
|
0x110b);
|
|
|
|
PHY_WRITE(sc, BRGPHY_TEST1,
|
|
|
|
BRGPHY_TEST1_TRIM_EN | 0x4);
|
|
|
|
} else {
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
|
|
|
|
0x010b);
|
|
|
|
}
|
|
|
|
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
|
|
|
|
}
|
2013-10-31 08:26:40 +04:00
|
|
|
if (bsc->sc_phyflags & BGEPHYF_CRC_BUG)
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_crc_bug(sc);
|
|
|
|
|
|
|
|
/* Set Jumbo frame settings in the PHY. */
|
2013-10-31 08:26:40 +04:00
|
|
|
if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE)
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_jumbo_settings(sc);
|
|
|
|
|
|
|
|
/* Adjust output voltage */
|
2013-03-15 10:18:13 +04:00
|
|
|
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
|
|
|
|
&& (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906))
|
2009-04-19 15:10:36 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
|
|
|
|
|
|
|
|
/* Enable Ethernet@Wirespeed */
|
2013-10-31 08:26:40 +04:00
|
|
|
if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED))
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_eth_wirespeed(sc);
|
|
|
|
|
2010-01-24 19:26:09 +03:00
|
|
|
#if 0
|
2009-04-19 15:10:36 +04:00
|
|
|
/* Enable Link LED on Dell boxes */
|
2013-10-31 08:26:40 +04:00
|
|
|
if (bsc->sc_phyflags & BGEPHYF_NO_3LED) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, ®);
|
2019-01-08 06:14:51 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
reg & ~BRGPHY_PHY_EXTCTL_3_LED);
|
2009-04-19 15:10:36 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
/* Handle any bnx (NetXtreme II) workarounds. */
|
2010-12-10 02:25:49 +03:00
|
|
|
} else if (bsc->sc_isbnx) {
|
2019-03-25 12:20:46 +03:00
|
|
|
uint32_t chip_num = _BNX_CHIP_NUM(bsc->sc_chipid);
|
|
|
|
uint32_t chip_id = _BNX_CHIP_ID(bsc->sc_chipid);
|
|
|
|
uint32_t chip_rev = _BNX_CHIP_REV(bsc->sc_chipid);
|
|
|
|
|
2013-03-15 10:18:13 +04:00
|
|
|
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
|
|
|
|
&& sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) {
|
2019-03-25 12:20:46 +03:00
|
|
|
/*
|
|
|
|
* Store autoneg capabilities/results in digital block
|
|
|
|
* (Page 0)
|
|
|
|
*/
|
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
|
|
BRGPHY_5708S_DIG3_PG2);
|
2019-01-08 06:14:51 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
|
|
|
|
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
|
2019-03-25 12:20:46 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
|
|
BRGPHY_5708S_DIG_PG0);
|
2009-04-19 15:10:36 +04:00
|
|
|
|
|
|
|
/* Enable fiber mode and autodetection */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, ®);
|
2019-03-25 12:20:46 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg |
|
|
|
|
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
|
2019-01-08 06:14:51 +03:00
|
|
|
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
|
2009-04-19 15:10:36 +04:00
|
|
|
|
|
|
|
/* Enable parallel detection */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, ®);
|
2019-03-25 12:20:46 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
|
2009-04-19 15:10:36 +04:00
|
|
|
|
2019-03-25 12:20:46 +03:00
|
|
|
/*
|
|
|
|
* Advertise 2.5G support through next page during
|
|
|
|
* autoneg
|
|
|
|
*/
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
|
|
|
|
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
|
|
|
|
®);
|
2019-03-25 12:20:46 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
|
|
|
|
}
|
2009-04-19 15:10:36 +04:00
|
|
|
|
|
|
|
/* Increase TX signal amplitude */
|
2019-03-25 12:20:46 +03:00
|
|
|
if ((chip_id == BNX_CHIP_ID_5708_A0) ||
|
|
|
|
(chip_id == BNX_CHIP_ID_5708_B0) ||
|
|
|
|
(chip_id == BNX_CHIP_ID_5708_B1)) {
|
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
BRGPHY_5708S_TX_MISC_PG5);
|
|
|
|
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, ®);
|
2019-01-08 06:14:51 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM);
|
2019-03-25 12:20:46 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
BRGPHY_5708S_DIG_PG0);
|
2009-04-19 15:10:36 +04:00
|
|
|
}
|
2003-07-17 15:44:26 +04:00
|
|
|
|
2019-03-25 12:20:46 +03:00
|
|
|
/*
|
|
|
|
* Backplanes use special
|
|
|
|
* driver/pre-driver/pre-emphasis values.
|
|
|
|
*/
|
2014-06-18 01:37:20 +04:00
|
|
|
if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
|
|
|
|
(bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
|
2019-03-25 12:20:46 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
|
|
BRGPHY_5708S_TX_MISC_PG5);
|
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
|
|
|
|
bsc->sc_port_hwcfg &
|
|
|
|
BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
|
|
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
|
|
BRGPHY_5708S_DIG_PG0);
|
2009-04-19 15:10:36 +04:00
|
|
|
}
|
2014-06-18 01:37:20 +04:00
|
|
|
} else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
|
2013-03-15 10:18:13 +04:00
|
|
|
&& (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) {
|
2010-12-10 02:25:49 +03:00
|
|
|
/* Select the SerDes Digital block of the AN MMD. */
|
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
|
|
|
|
BRGPHY_BLOCK_ADDR_SERDES_DIG);
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, ®);
|
2010-12-10 02:25:49 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
(reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |
|
2010-12-10 02:25:49 +03:00
|
|
|
BRGPHY_SD_DIG_1000X_CTL1_FIBER);
|
|
|
|
|
2011-05-02 13:03:10 +04:00
|
|
|
if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
|
2010-12-10 02:25:49 +03:00
|
|
|
/* Select the Over 1G block of the AN MMD. */
|
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
|
|
|
|
BRGPHY_BLOCK_ADDR_OVER_1G);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable autoneg "Next Page" to advertise
|
|
|
|
* 2.5G support.
|
|
|
|
*/
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
|
|
|
|
®);
|
2010-12-10 02:25:49 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
|
2010-12-10 02:25:49 +03:00
|
|
|
}
|
|
|
|
|
2019-01-08 06:14:51 +03:00
|
|
|
/*
|
|
|
|
* Select the Multi-Rate Backplane Ethernet block of
|
|
|
|
* the AN MMD.
|
|
|
|
*/
|
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
|
|
|
|
BRGPHY_BLOCK_ADDR_MRBE);
|
|
|
|
|
|
|
|
/* Enable MRBE speed autoneg. */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, ®);
|
2019-01-08 06:14:51 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE |
|
2019-01-08 06:14:51 +03:00
|
|
|
BRGPHY_MRBE_MSG_PG5_NP_T2);
|
|
|
|
|
|
|
|
/* Select the Clause 73 User B0 block of the AN MMD. */
|
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
|
|
|
|
BRGPHY_BLOCK_ADDR_CL73_USER_B0);
|
|
|
|
|
|
|
|
/* Enable MRBE speed autoneg. */
|
|
|
|
PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
|
|
|
|
BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
|
|
|
|
BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
|
|
|
|
BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
|
|
|
|
|
|
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
|
|
|
|
BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
|
2010-12-10 02:25:49 +03:00
|
|
|
|
2019-03-25 12:20:46 +03:00
|
|
|
} else if (chip_num == BNX_CHIP_NUM_5709) {
|
|
|
|
if ((chip_rev == BNX_CHIP_REV_Ax) ||
|
|
|
|
(chip_rev == BNX_CHIP_REV_Bx))
|
2011-05-02 13:03:10 +04:00
|
|
|
brgphy_disable_early_dac(sc);
|
|
|
|
|
|
|
|
/* Set Jumbo frame settings in the PHY. */
|
|
|
|
brgphy_jumbo_settings(sc);
|
|
|
|
|
|
|
|
/* Enable Ethernet@Wirespeed */
|
|
|
|
brgphy_eth_wirespeed(sc);
|
2009-04-19 15:10:36 +04:00
|
|
|
} else {
|
|
|
|
if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
|
|
|
|
brgphy_ber_bug(sc);
|
2003-07-17 15:44:26 +04:00
|
|
|
|
2009-04-19 15:10:36 +04:00
|
|
|
/* Set Jumbo frame settings in the PHY. */
|
|
|
|
brgphy_jumbo_settings(sc);
|
2004-10-28 11:26:17 +04:00
|
|
|
|
2009-04-19 15:10:36 +04:00
|
|
|
/* Enable Ethernet@Wirespeed */
|
|
|
|
brgphy_eth_wirespeed(sc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2007-08-06 16:16:33 +04:00
|
|
|
}
|
|
|
|
|
2003-01-16 23:02:05 +03:00
|
|
|
/* Turn off tap power management on 5401. */
|
2002-07-13 05:23:27 +04:00
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_bcm5401_dspcode(struct mii_softc *sc)
|
2002-07-13 05:23:27 +04:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
2003-01-16 23:02:05 +03:00
|
|
|
{ BRGPHY_MII_AUXCTL, 0x0c20 },
|
2002-07-13 05:23:27 +04:00
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x1804 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x1204 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0132 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0232 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
|
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
2013-03-15 10:18:13 +04:00
|
|
|
delay(40);
|
2002-07-13 05:23:27 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_bcm5411_dspcode(struct mii_softc *sc)
|
2002-07-13 05:23:27 +04:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
|
|
|
{ 0x1c, 0x8c23 },
|
|
|
|
{ 0x1c, 0x8ca3 },
|
|
|
|
{ 0x1c, 0x8c23 },
|
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
2003-01-16 21:43:40 +03:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_bcm5421_dspcode(struct mii_softc *sc)
|
|
|
|
{
|
|
|
|
uint16_t data;
|
|
|
|
|
|
|
|
/* Set Class A mode */
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
|
2009-04-19 15:10:36 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
|
|
|
|
|
|
|
|
/* Set FFE gamma override to -0.125 */
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
|
2009-04-19 15:10:36 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data);
|
2009-04-19 15:10:36 +04:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
|
|
|
|
}
|
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_bcm54k2_dspcode(struct mii_softc *sc)
|
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
|
|
|
{ 4, 0x01e1 },
|
|
|
|
{ 9, 0x0300 },
|
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
|
|
|
|
2003-01-16 21:43:40 +03:00
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_adc_bug(struct mii_softc *sc)
|
2003-01-16 21:43:40 +03:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
|
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
|
2009-04-19 15:10:36 +04:00
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0323 },
|
|
|
|
{ BRGPHY_MII_AUXCTL, 0x0400 },
|
2003-01-16 21:43:40 +03:00
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_5704_a0_bug(struct mii_softc *sc)
|
2003-01-16 21:43:40 +03:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
|
|
|
{ 0x1c, 0x8d68 },
|
2007-03-13 09:41:52 +03:00
|
|
|
{ 0x1c, 0x8d68 },
|
2003-01-16 21:43:40 +03:00
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
2004-10-28 11:26:17 +04:00
|
|
|
|
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_ber_bug(struct mii_softc *sc)
|
2004-10-28 11:26:17 +04:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
|
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x310b },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x9506 },
|
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x401f },
|
|
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
|
|
|
|
{ BRGPHY_MII_AUXCTL, 0x0400 },
|
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
2007-08-06 16:16:33 +04:00
|
|
|
|
2009-04-19 15:10:36 +04:00
|
|
|
/* BCM5701 A0/B0 CRC bug workaround */
|
2020-03-16 02:04:50 +03:00
|
|
|
static void
|
2009-04-19 15:10:36 +04:00
|
|
|
brgphy_crc_bug(struct mii_softc *sc)
|
2007-08-06 16:16:33 +04:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
int reg;
|
|
|
|
uint16_t val;
|
|
|
|
} dspcode[] = {
|
2009-04-19 15:10:36 +04:00
|
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
|
|
|
|
{ 0x1c, 0x8c68 },
|
|
|
|
{ 0x1c, 0x8d68 },
|
|
|
|
{ 0x1c, 0x8c68 },
|
2007-08-06 16:16:33 +04:00
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
2010-01-24 19:26:09 +03:00
|
|
|
|
2011-05-02 13:03:10 +04:00
|
|
|
static void
|
|
|
|
brgphy_disable_early_dac(struct mii_softc *sc)
|
|
|
|
{
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t val;
|
2011-05-02 13:03:10 +04:00
|
|
|
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &val);
|
2011-05-02 13:03:10 +04:00
|
|
|
val &= ~(1 << 8);
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2010-01-24 19:26:09 +03:00
|
|
|
static void
|
|
|
|
brgphy_jumbo_settings(struct mii_softc *sc)
|
|
|
|
{
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t val;
|
2010-01-24 19:26:09 +03:00
|
|
|
|
|
|
|
/* Set Jumbo frame settings in the PHY. */
|
2013-03-15 10:18:13 +04:00
|
|
|
if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
|
|
|
|
&& (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) {
|
2010-01-24 19:26:09 +03:00
|
|
|
/* Cannot do read-modify-write on the BCM5401 */
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
|
|
|
|
} else {
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
|
2010-01-24 19:26:09 +03:00
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
|
2010-01-24 19:26:09 +03:00
|
|
|
}
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &val);
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
|
2010-01-24 19:26:09 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
brgphy_eth_wirespeed(struct mii_softc *sc)
|
|
|
|
{
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t val;
|
2010-01-24 19:26:09 +03:00
|
|
|
|
|
|
|
/* Enable Ethernet@Wirespeed */
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
|
2010-01-24 19:26:09 +03:00
|
|
|
}
|
2020-05-25 22:48:38 +03:00
|
|
|
|
|
|
|
static void
|
|
|
|
brgphy_bcm54xx_clock_delay(struct mii_softc *sc)
|
|
|
|
{
|
|
|
|
uint16_t val;
|
|
|
|
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC |
|
|
|
|
BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT);
|
|
|
|
PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
|
|
|
|
val &= BRGPHY_AUXCTL_MISC_DATA_MASK;
|
|
|
|
if (sc->mii_flags & MIIF_RXID)
|
|
|
|
val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
|
|
|
|
else
|
|
|
|
val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN |
|
|
|
|
BRGPHY_AUXCTL_SHADOW_MISC | val);
|
|
|
|
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL);
|
|
|
|
PHY_READ(sc, BRGPHY_MII_SHADOW_1C, &val);
|
|
|
|
val &= BRGPHY_SHADOW_1C_DATA_MASK;
|
|
|
|
if (sc->mii_flags & MIIF_TXID)
|
|
|
|
val |= BRGPHY_SHADOW_1C_GTXCLK_EN;
|
|
|
|
else
|
|
|
|
val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN;
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN |
|
|
|
|
BRGPHY_SHADOW_1C_CLK_CTRL | val);
|
|
|
|
}
|