Whitespace fixes. No functional change.
This commit is contained in:
msaitoh
parent
51c183ce48
commit
ba98a0a811
@ -1,4 +1,4 @@
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/* $NetBSD: brgphy.c,v 1.76 2014/07/02 22:35:10 msaitoh Exp $ */
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/* $NetBSD: brgphy.c,v 1.77 2019/01/08 03:14:51 msaitoh Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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@ -62,7 +62,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.76 2014/07/02 22:35:10 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.77 2019/01/08 03:14:51 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -901,7 +901,7 @@ brgphy_reset(struct mii_softc *sc)
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PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG,
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0x000a);
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if (bsc->sc_phyflags
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if (bsc->sc_phyflags
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& BGEPHYF_ADJUST_TRIM) {
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PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
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0x110b);
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@ -933,8 +933,8 @@ brgphy_reset(struct mii_softc *sc)
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#if 0
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/* Enable Link LED on Dell boxes */
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if (bsc->sc_phyflags & BGEPHYF_NO_3LED) {
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PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
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PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
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PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
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PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
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& ~BRGPHY_PHY_EXTCTL_3_LED);
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}
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#endif
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@ -945,48 +945,48 @@ brgphy_reset(struct mii_softc *sc)
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&& sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) {
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/* Store autoneg capabilities/results in digital block (Page 0) */
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
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PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
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BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
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PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
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BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
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/* Enable fiber mode and autodetection */
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PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
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PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
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BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
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BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
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PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
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PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
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BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
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BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
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/* Enable parallel detection */
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PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
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PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
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BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
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PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
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PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
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BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
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/* Advertise 2.5G support through next page during autoneg */
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if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG)
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PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
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PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
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BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
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PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
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PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
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BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
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/* Increase TX signal amplitude */
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if ((_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_A0) ||
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(_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B0) ||
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(_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B1)) {
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_TX_MISC_PG5);
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PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
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PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_TX_MISC_PG5);
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PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
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PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &
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~BRGPHY_5708S_PG5_TXACTL1_VCM);
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_DIG_PG0);
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_DIG_PG0);
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}
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/* Backplanes use special driver/pre-driver/pre-emphasis values. */
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if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
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(bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_TX_MISC_PG5);
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PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
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bsc->sc_port_hwcfg &
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BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_TX_MISC_PG5);
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PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
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bsc->sc_port_hwcfg &
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BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_DIG_PG0);
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}
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@ -1015,31 +1015,31 @@ brgphy_reset(struct mii_softc *sc)
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BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
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}
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/*
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* Select the Multi-Rate Backplane Ethernet block of
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* the AN MMD.
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*/
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
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BRGPHY_BLOCK_ADDR_MRBE);
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/*
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* Select the Multi-Rate Backplane Ethernet block of
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* the AN MMD.
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*/
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
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BRGPHY_BLOCK_ADDR_MRBE);
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/* Enable MRBE speed autoneg. */
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PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
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PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) |
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BRGPHY_MRBE_MSG_PG5_NP_MBRE |
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BRGPHY_MRBE_MSG_PG5_NP_T2);
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/* Enable MRBE speed autoneg. */
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PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
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PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) |
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BRGPHY_MRBE_MSG_PG5_NP_MBRE |
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BRGPHY_MRBE_MSG_PG5_NP_T2);
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/* Select the Clause 73 User B0 block of the AN MMD. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
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BRGPHY_BLOCK_ADDR_CL73_USER_B0);
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/* Select the Clause 73 User B0 block of the AN MMD. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
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BRGPHY_BLOCK_ADDR_CL73_USER_B0);
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/* Enable MRBE speed autoneg. */
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PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
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BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
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BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
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BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
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/* Enable MRBE speed autoneg. */
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PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
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BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
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BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
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BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
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BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
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BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
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} else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) {
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if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax ||
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@ -1,4 +1,4 @@
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/* $NetBSD: igphy.c,v 1.27 2017/07/06 08:09:05 msaitoh Exp $ */
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/* $NetBSD: igphy.c,v 1.28 2019/01/08 03:14:51 msaitoh Exp $ */
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/*
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* The Intel copyright applies to the analog register setup, and the
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@ -70,7 +70,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.27 2017/07/06 08:09:05 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.28 2019/01/08 03:14:51 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_mii.h"
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@ -506,7 +506,7 @@ igphy_smartspeed_workaround(struct mii_softc *sc)
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case WM_T_82547_2:
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break;
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default:
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/* byebye */
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/* byebye */
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return;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: makphy.c,v 1.48 2018/12/30 06:40:52 msaitoh Exp $ */
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/* $NetBSD: makphy.c,v 1.49 2019/01/08 03:14:51 msaitoh Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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@ -55,7 +55,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.48 2018/12/30 06:40:52 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.49 2019/01/08 03:14:51 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -203,7 +203,7 @@ makphyattach(device_t parent, device_t self, void *aux)
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case MII_MODEL_xxMARVELL_E1112:
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if (PHY_READ(sc, MAKPHY_ESSR) & ESSR_FIBER_LINK)
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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break;
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default:
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break;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: mii_physubr.c,v 1.82 2018/12/28 05:56:07 msaitoh Exp $ */
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/* $NetBSD: mii_physubr.c,v 1.83 2019/01/08 03:14:51 msaitoh Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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@ -35,7 +35,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mii_physubr.c,v 1.82 2018/12/28 05:56:07 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mii_physubr.c,v 1.83 2019/01/08 03:14:51 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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@ -66,14 +66,14 @@ const char *mii_get_descr_stub(int oui, int model)
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return NULL;
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}
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/*
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/*
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* Routine to load the miiverbose kernel module as needed
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*/
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void mii_load_verbose(void)
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{
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if (mii_verbose_loaded == 0)
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module_autoload("miiverbose", MODULE_CLASS_MISC);
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}
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}
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static void mii_phy_statusmsg(struct mii_softc *);
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@ -244,7 +244,7 @@ mii_phy_auto(struct mii_softc *sc, int waitfor)
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
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anar &= ~(ANAR_T4|ANAR_TX_FD|ANAR_TX|ANAR_10_FD|ANAR_10);
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}
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PHY_WRITE(sc, MII_ANAR, anar);
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if (sc->mii_flags & MIIF_HAVE_GTCR) {
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uint16_t gtcr = 0;
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@ -1,4 +1,4 @@
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/* $NetBSD: mii_verbose.c,v 1.3 2010/07/25 14:44:34 pgoyette Exp $ */
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/* $NetBSD: mii_verbose.c,v 1.4 2019/01/08 03:14:51 msaitoh Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
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@ -55,7 +55,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mii_verbose.c,v 1.3 2010/07/25 14:44:34 pgoyette Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mii_verbose.c,v 1.4 2019/01/08 03:14:51 msaitoh Exp $");
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#include <sys/module.h>
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#include <dev/mii/mii_verbose.h>
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@ -90,7 +90,7 @@ miiverbose_modcmd(modcmd_t cmd, void *arg)
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default:
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return ENOTTY;
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}
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}
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}
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const char *
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mii_get_descr_real(int oui, int model) {
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