Add support for the BCM5705:
- Only BCM5705M asic rev A1 was tested. Thanks to Bill Paul (wpaul@freebsd.org) for help and support. Approved by: Frank van der Linden <fvdl@netbsd.org>
This commit is contained in:
hannken
parent
fde07830ad
commit
7b247f3812
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@ -1,4 +1,4 @@
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/* $NetBSD: brgphy.c,v 1.17 2003/04/29 01:49:33 thorpej Exp $ */
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/* $NetBSD: brgphy.c,v 1.18 2003/07/17 11:44:26 hannken Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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@ -74,7 +74,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.17 2003/04/29 01:49:33 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.18 2003/07/17 11:44:26 hannken Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -105,6 +105,7 @@ void brgphy_5401_reset(struct mii_softc *);
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void brgphy_5411_reset(struct mii_softc *);
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void brgphy_5703_reset(struct mii_softc *);
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void brgphy_5704_reset(struct mii_softc *);
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void brgphy_5705_reset(struct mii_softc *);
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const struct mii_phy_funcs brgphy_funcs = {
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brgphy_service, brgphy_status, mii_phy_reset,
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@ -126,6 +127,10 @@ const struct mii_phy_funcs brgphy_5704_funcs = {
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brgphy_service, brgphy_status, brgphy_5704_reset,
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};
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const struct mii_phy_funcs brgphy_5705_funcs = {
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brgphy_service, brgphy_status, brgphy_5705_reset,
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};
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const struct mii_phydesc brgphys[] = {
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400,
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@ -149,6 +154,9 @@ const struct mii_phydesc brgphys[] = {
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704,
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MII_STR_BROADCOM_BCM5704 },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705,
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MII_STR_BROADCOM_BCM5705 },
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{ 0, 0,
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NULL },
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};
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@ -223,6 +231,10 @@ brgphyattach(struct device *parent, struct device *self, void *aux)
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sc->mii_dev.dv_xname);
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break;
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case MII_MODEL_BROADCOM_BCM5705:
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sc->mii_funcs = &brgphy_5705_funcs;
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break;
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default:
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sc->mii_funcs = &brgphy_funcs;
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break;
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@ -276,7 +288,8 @@ brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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mii_phy_reset(sc); /* XXX hardware bug work-around */
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if (sc->mii_funcs != &brgphy_5705_funcs)
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mii_phy_reset(sc); /* XXX hardware bug work-around */
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mii_phy_setmedia(sc);
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break;
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@ -427,6 +440,16 @@ brgphy_5704_reset(struct mii_softc *sc)
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bcm5704_load_dspcode(sc);
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}
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/*
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* Hardware bug workaround. Do nothing since after
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* reset the 5705 PHY would get stuck in 10/100 MII mode.
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*/
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void
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brgphy_5705_reset(struct mii_softc *sc)
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{
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}
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/* Turn off tap power management on 5401. */
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static void
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bcm5401_load_dspcode(struct mii_softc *sc)
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@ -1,4 +1,4 @@
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$NetBSD: miidevs,v 1.48 2003/07/01 22:46:08 msaitoh Exp $
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$NetBSD: miidevs,v 1.49 2003/07/17 11:44:26 hannken Exp $
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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@ -126,6 +126,7 @@ model BROADCOM BCM5421 0x000e BCM5421 1000BASE-T media interface
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model BROADCOM BCM5701 0x0011 BCM5701 1000BASE-T media interface
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model BROADCOM BCM5703 0x0016 BCM5703 1000BASE-T media interface
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model BROADCOM BCM5704 0x0019 BCM5704 1000BASE-T media interface
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model BROADCOM BCM5705 0x001a BCM5705 1000BASE-T media interface
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/* Davicom Semiconductor PHYs */
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/* AMD Am79C873 seems to be a relabeled DM9101 */
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@ -1,10 +1,10 @@
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/* $NetBSD: miidevs.h,v 1.48 2003/07/01 22:46:08 msaitoh Exp $ */
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/* $NetBSD: miidevs.h,v 1.49 2003/07/17 11:44:26 hannken Exp $ */
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/*
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* NetBSD: miidevs,v 1.47 2003/05/02 19:39:29 scw Exp
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* NetBSD: miidevs,v 1.48 2003/07/01 22:46:08 msaitoh Exp
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*/
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/*-
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@ -154,6 +154,8 @@
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#define MII_STR_BROADCOM_BCM5703 "BCM5703 1000BASE-T media interface"
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#define MII_MODEL_BROADCOM_BCM5704 0x0019
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#define MII_STR_BROADCOM_BCM5704 "BCM5704 1000BASE-T media interface"
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#define MII_MODEL_BROADCOM_BCM5705 0x001a
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#define MII_STR_BROADCOM_BCM5705 "BCM5705 1000BASE-T media interface"
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/* Davicom Semiconductor PHYs */
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/* AMD Am79C873 seems to be a relabeled DM9101 */
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@ -1,10 +1,10 @@
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/* $NetBSD: miidevs_data.h,v 1.38 2003/07/01 22:46:08 msaitoh Exp $ */
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/* $NetBSD: miidevs_data.h,v 1.39 2003/07/17 11:44:26 hannken Exp $ */
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/*
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* NetBSD: miidevs,v 1.47 2003/05/02 19:39:29 scw Exp
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* NetBSD: miidevs,v 1.48 2003/07/01 22:46:08 msaitoh Exp
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*/
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/*-
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@ -65,6 +65,7 @@ struct mii_knowndev mii_knowndevs[] = {
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, MII_STR_BROADCOM_BCM5701 },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, MII_STR_BROADCOM_BCM5703 },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, MII_STR_BROADCOM_BCM5704 },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, MII_STR_BROADCOM_BCM5705 },
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{ MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 },
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{ MII_OUI_ICS, MII_MODEL_ICS_1889, MII_STR_ICS_1889 },
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{ MII_OUI_ICS, MII_MODEL_ICS_1890, MII_STR_ICS_1890 },
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@ -1,4 +1,4 @@
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/* $NetBSD: if_bge.c,v 1.43 2003/07/14 15:47:24 lukem Exp $ */
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/* $NetBSD: if_bge.c,v 1.44 2003/07/17 11:44:27 hannken Exp $ */
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/*
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* Copyright (c) 2001 Wind River Systems
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@ -79,7 +79,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.43 2003/07/14 15:47:24 lukem Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.44 2003/07/17 11:44:27 hannken Exp $");
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#include "bpfilter.h"
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#include "vlan.h"
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@ -206,6 +206,7 @@ int bgedebug = 0;
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#define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010
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#define BGE_QUIRK_PRODUCER_BUG 0x00000020
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#define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040
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#define BGE_QUIRK_5705_CORE 0x00000080
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/* following bugs are common to bcm5700 rev B, all flavours */
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#define BGE_QUIRK_5700_COMMON \
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@ -1145,8 +1146,10 @@ bge_chipinit(sc)
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DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname));
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dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
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(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
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(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
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(0x0F));
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(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT));
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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dma_rw_ctl |= 0x0F;
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}
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} else {
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DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname));
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/* PCI-X bus */
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@ -1281,17 +1284,22 @@ bge_blockinit(sc)
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BGE_PCI_MEMWIN_BASEADDR, 0);
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/* Configure mbuf memory pool */
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if (sc->bge_extram) {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
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} else {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
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}
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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if (sc->bge_extram) {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
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BGE_EXT_SSRAM);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
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} else {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
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BGE_BUFFPOOL_1);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
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}
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/* Configure DMA resource pool */
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CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS);
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CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
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/* Configure DMA resource pool */
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CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
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BGE_DMA_DESCRIPTORS);
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CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
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}
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/* Configure mbuf pool watermarks */
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#ifdef ORIG_WPAUL_VALUES
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@ -1300,8 +1308,13 @@ bge_blockinit(sc)
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
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#else
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/* new broadcom docs strongly recommend these: */
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
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} else {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
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}
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
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#endif
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@ -1310,20 +1323,22 @@ bge_blockinit(sc)
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CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
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/* Enable buffer manager */
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CSR_WRITE_4(sc, BGE_BMAN_MODE,
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BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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CSR_WRITE_4(sc, BGE_BMAN_MODE,
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BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
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/* Poll for buffer manager start indication */
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for (i = 0; i < BGE_TIMEOUT; i++) {
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if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
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break;
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DELAY(10);
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}
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/* Poll for buffer manager start indication */
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for (i = 0; i < BGE_TIMEOUT; i++) {
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if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
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break;
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DELAY(10);
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}
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if (i == BGE_TIMEOUT) {
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printf("%s: buffer manager failed to start\n",
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sc->bge_dev.dv_xname);
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return(ENXIO);
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if (i == BGE_TIMEOUT) {
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printf("%s: buffer manager failed to start\n",
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sc->bge_dev.dv_xname);
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return(ENXIO);
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}
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}
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/* Enable flow-through queues */
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@ -1347,7 +1362,12 @@ bge_blockinit(sc)
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rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
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bge_set_hostaddr(&rcb->bge_hostaddr,
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BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
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rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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rcb->bge_maxlen_flags =
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BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
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} else {
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rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
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}
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if (sc->bge_extram)
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rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
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else
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@ -1357,6 +1377,12 @@ bge_blockinit(sc)
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CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
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CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
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} else {
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sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
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}
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/*
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* Initialize the jumbo RX ring control block
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* We set the 'ring disabled' bit in the flags
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@ -1364,30 +1390,38 @@ bge_blockinit(sc)
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* using this ring (i.e. once we set the MTU
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* high enough to require it).
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*/
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rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
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bge_set_hostaddr(&rcb->bge_hostaddr,
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BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
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rcb->bge_maxlen_flags =
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BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED);
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if (sc->bge_extram)
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rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
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else
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rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
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if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
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rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
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bge_set_hostaddr(&rcb->bge_hostaddr,
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BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
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rcb->bge_maxlen_flags =
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BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
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BGE_RCB_FLAG_RING_DISABLED);
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if (sc->bge_extram)
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rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
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else
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rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
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rcb->bge_hostaddr.bge_addr_hi);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
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rcb->bge_hostaddr.bge_addr_lo);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
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rcb->bge_maxlen_flags);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
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CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
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/* Set up dummy disabled mini ring RCB */
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rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
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rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
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BGE_RCB_FLAG_RING_DISABLED);
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CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
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rcb->bge_maxlen_flags);
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/* Set up dummy disabled mini ring RCB */
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rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
|
||||
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
|
||||
BGE_RCB_FLAG_RING_DISABLED);
|
||||
CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
|
||||
|
||||
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
|
||||
offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib),
|
||||
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
||||
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
|
||||
offsetof(struct bge_ring_data, bge_info),
|
||||
sizeof (struct bge_gib),
|
||||
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the BD ring replentish thresholds. The recommended
|
||||
|
|
@ -1417,8 +1451,10 @@ bge_blockinit(sc)
|
|||
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
|
||||
BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
|
||||
BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
|
||||
BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
|
||||
}
|
||||
|
||||
/* Disable all unused RX return rings */
|
||||
rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
|
||||
|
|
@ -1426,7 +1462,7 @@ bge_blockinit(sc)
|
|||
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
|
||||
BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT,
|
||||
BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
|
||||
BGE_RCB_FLAG_RING_DISABLED));
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
|
||||
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
|
||||
|
|
@ -1451,7 +1487,7 @@ bge_blockinit(sc)
|
|||
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
|
||||
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
|
||||
BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT,0));
|
||||
BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
|
||||
|
||||
/* Set random backoff seed for TX */
|
||||
CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
|
||||
|
|
@ -1500,17 +1536,22 @@ bge_blockinit(sc)
|
|||
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
|
||||
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
|
||||
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
|
||||
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
|
||||
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
|
||||
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
|
||||
}
|
||||
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
|
||||
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
|
||||
|
||||
/* Set up address of statistics block */
|
||||
bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
bge_set_hostaddr(&taddr,
|
||||
BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
|
||||
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
|
||||
}
|
||||
|
||||
/* Set up address of status block */
|
||||
bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
|
||||
|
|
@ -1531,7 +1572,9 @@ bge_blockinit(sc)
|
|||
CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
|
||||
|
||||
/* Turn on RX list selector state machine. */
|
||||
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
|
||||
}
|
||||
|
||||
/* Turn on DMA, clear stats */
|
||||
CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
|
||||
|
|
@ -1561,7 +1604,9 @@ bge_blockinit(sc)
|
|||
CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
|
||||
|
||||
/* Turn on DMA completion state machine */
|
||||
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
|
||||
}
|
||||
|
||||
/* Turn on write DMA state machine */
|
||||
CSR_WRITE_4(sc, BGE_WDMA_MODE,
|
||||
|
|
@ -1581,7 +1626,9 @@ bge_blockinit(sc)
|
|||
CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
|
||||
|
||||
/* Turn on Mbuf cluster free state machine */
|
||||
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
|
||||
}
|
||||
|
||||
/* Turn on send BD completion state machine */
|
||||
CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
|
||||
|
|
@ -1700,6 +1747,10 @@ static const struct bge_revision {
|
|||
BGE_QUIRK_ONLY_PHY_1,
|
||||
"BCM5704 A2" },
|
||||
|
||||
{ BGE_ASICREV_BCM5705_A1,
|
||||
BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
|
||||
"BCM5705 A1" },
|
||||
|
||||
{ 0, 0, NULL }
|
||||
};
|
||||
|
||||
|
|
@ -1768,7 +1819,9 @@ static const struct bge_product {
|
|||
{ PCI_VENDOR_BROADCOM,
|
||||
PCI_PRODUCT_BROADCOM_BCM5704S,
|
||||
"Broadcom BCM5704S Dual Gigabit Ethernet" },
|
||||
|
||||
{ PCI_VENDOR_BROADCOM,
|
||||
PCI_PRODUCT_BROADCOM_BCM5705M,
|
||||
"Broadcom BCM5705M Gigabit Ethernet" },
|
||||
|
||||
{ PCI_VENDOR_SCHNEIDERKOCH,
|
||||
PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
|
||||
|
|
@ -2067,11 +2120,13 @@ bge_attach(parent, self, aux)
|
|||
memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
|
||||
|
||||
/* Try to allocate memory for jumbo buffers. */
|
||||
if (bge_alloc_jumbo_mem(sc)) {
|
||||
aprint_error("%s: jumbo buffer allocation failed\n",
|
||||
sc->bge_dev.dv_xname);
|
||||
} else
|
||||
sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
if (bge_alloc_jumbo_mem(sc)) {
|
||||
aprint_error("%s: jumbo buffer allocation failed\n",
|
||||
sc->bge_dev.dv_xname);
|
||||
} else
|
||||
sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
|
||||
}
|
||||
|
||||
/* Set default tuneable values. */
|
||||
sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
|
||||
|
|
@ -2234,7 +2289,9 @@ bge_reset(sc)
|
|||
bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
|
||||
|
||||
/* Enable memory arbiter. */
|
||||
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent PXE restart: write a magic number to the
|
||||
|
|
@ -2277,7 +2334,9 @@ bge_reset(sc)
|
|||
}
|
||||
|
||||
/* Enable memory arbiter. */
|
||||
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
||||
}
|
||||
|
||||
/* Fix up byte swapping */
|
||||
CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
|
||||
|
|
@ -2323,7 +2382,7 @@ bge_rxeof(sc)
|
|||
toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd));
|
||||
|
||||
if (tosync < 0) {
|
||||
tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) *
|
||||
tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) *
|
||||
sizeof (struct bge_rx_bd);
|
||||
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
|
||||
toff, tlen, BUS_DMASYNC_POSTREAD);
|
||||
|
|
@ -2344,7 +2403,7 @@ bge_rxeof(sc)
|
|||
bge_rx_return_ring[sc->bge_rx_saved_considx];
|
||||
|
||||
rxidx = cur_rx->bge_idx;
|
||||
BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT);
|
||||
BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
|
||||
|
||||
if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
|
||||
have_tag = 1;
|
||||
|
|
@ -2580,7 +2639,8 @@ bge_intr(xsc)
|
|||
bge_tick(sc);
|
||||
/* Clear the interrupt */
|
||||
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
|
||||
BGE_MACSTAT_CFG_CHANGED);
|
||||
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
|
||||
BGE_MACSTAT_LINK_CHANGED);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2653,7 +2713,21 @@ bge_stats_update(sc)
|
|||
{
|
||||
struct ifnet *ifp = &sc->ethercom.ec_if;
|
||||
bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
|
||||
bus_size_t rstats = BGE_RX_STATS;
|
||||
|
||||
#define READ_RSTAT(sc, stats, stat) \
|
||||
CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat))
|
||||
|
||||
if (sc->bge_quirks & BGE_QUIRK_5705_CORE) {
|
||||
ifp->if_collisions +=
|
||||
READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) +
|
||||
READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) +
|
||||
READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) +
|
||||
READ_RSTAT(sc, rstats, dot3StatsLateCollisions);
|
||||
return;
|
||||
}
|
||||
|
||||
#undef READ_RSTAT
|
||||
#define READ_STAT(sc, stats, stat) \
|
||||
CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
|
||||
|
||||
|
|
@ -3178,7 +3252,9 @@ bge_stop(sc)
|
|||
bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
|
||||
}
|
||||
bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
|
||||
|
|
@ -3191,7 +3267,9 @@ bge_stop(sc)
|
|||
bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
|
||||
}
|
||||
bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
|
||||
|
||||
/*
|
||||
|
|
@ -3200,13 +3278,17 @@ bge_stop(sc)
|
|||
*/
|
||||
bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
|
||||
}
|
||||
|
||||
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
|
||||
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
|
||||
|
||||
bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
||||
if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
|
||||
bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
|
||||
bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
||||
}
|
||||
|
||||
/* Disable host interrupts. */
|
||||
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: if_bgereg.h,v 1.10 2003/06/01 20:26:14 fvdl Exp $ */
|
||||
/* $NetBSD: if_bgereg.h,v 1.11 2003/07/17 11:44:27 hannken Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2001 Wind River Systems
|
||||
* Copyright (c) 1997, 1998, 1999, 2001
|
||||
|
|
@ -238,6 +238,10 @@
|
|||
#define BGE_ASICREV_BCM5704_A0 0x20000000
|
||||
#define BGE_ASICREV_BCM5704_A1 0x20010000
|
||||
#define BGE_ASICREV_BCM5704_A2 0x20020000
|
||||
#define BGE_ASICREV_BCM5705_A0 0x30000000
|
||||
#define BGE_ASICREV_BCM5705_A1 0x30010000
|
||||
#define BGE_ASICREV_BCM5705_A2 0x30020000
|
||||
#define BGE_ASICREV_BCM5705_A3 0x30030000
|
||||
|
||||
/* PCI DMA Read/Write Control register */
|
||||
#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
|
||||
|
|
@ -1917,6 +1921,7 @@ struct bge_status_block {
|
|||
#define BGE_JUMBO_RX_RING_CNT 256
|
||||
#define BGE_MINI_RX_RING_CNT 1024
|
||||
#define BGE_RETURN_RING_CNT 1024
|
||||
#define BGE_RETURN_RING_CNT_5705 512
|
||||
|
||||
/*
|
||||
* Possible TX ring sizes.
|
||||
|
|
@ -1936,6 +1941,44 @@ struct bge_status_block {
|
|||
/*
|
||||
* Tigon III statistics counters.
|
||||
*/
|
||||
|
||||
/* Stats counters access through registers */
|
||||
struct bge_mac_stats_regs {
|
||||
u_int32_t ifHCOutOctets;
|
||||
u_int32_t Reserved0;
|
||||
u_int32_t etherStatsCollisions;
|
||||
u_int32_t outXonSent;
|
||||
u_int32_t outXoffSent;
|
||||
u_int32_t Reserved1;
|
||||
u_int32_t dot3StatsInternalMacTransmitErrors;
|
||||
u_int32_t dot3StatsSingleCollisionFrames;
|
||||
u_int32_t dot3StatsMultipleCollisionFrames;
|
||||
u_int32_t dot3StatsDeferredTransmissions;
|
||||
u_int32_t Reserved2;
|
||||
u_int32_t dot3StatsExcessiveCollisions;
|
||||
u_int32_t dot3StatsLateCollisions;
|
||||
u_int32_t Reserved3[14];
|
||||
u_int32_t ifHCOutUcastPkts;
|
||||
u_int32_t ifHCOutMulticastPkts;
|
||||
u_int32_t ifHCOutBroadcastPkts;
|
||||
u_int32_t Reserved4[2];
|
||||
u_int32_t ifHCInOctets;
|
||||
u_int32_t Reserved5;
|
||||
u_int32_t etherStatsFragments;
|
||||
u_int32_t ifHCInUcastPkts;
|
||||
u_int32_t ifHCInMulticastPkts;
|
||||
u_int32_t ifHCInBroadcastPkts;
|
||||
u_int32_t dot3StatsFCSErrors;
|
||||
u_int32_t dot3StatsAlignmentErrors;
|
||||
u_int32_t xonPauseFramesReceived;
|
||||
u_int32_t xoffPauseFramesReceived;
|
||||
u_int32_t macControlFramesReceived;
|
||||
u_int32_t xoffStateEntered;
|
||||
u_int32_t dot3StatsFramesTooLong;
|
||||
u_int32_t etherStatsJabbers;
|
||||
u_int32_t etherStatsUndersizePkts;
|
||||
};
|
||||
|
||||
struct bge_stats {
|
||||
u_int8_t Reserved0[256];
|
||||
|
||||
|
|
@ -2235,6 +2278,7 @@ struct bge_softc {
|
|||
u_int8_t bge_extram; /* has external SSRAM */
|
||||
u_int8_t bge_tbi;
|
||||
u_int8_t bge_rx_alignment_bug;
|
||||
u_int32_t bge_return_ring_cnt;
|
||||
bus_dma_tag_t bge_dmatag;
|
||||
u_int32_t bge_asicrev;
|
||||
u_int32_t bge_quirks;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
$NetBSD: pcidevs,v 1.552 2003/07/14 08:00:43 jmmv Exp $
|
||||
$NetBSD: pcidevs,v 1.553 2003/07/17 11:44:27 hannken Exp $
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995, 1996 Christopher G. Demetriou
|
||||
|
|
@ -1035,6 +1035,7 @@ product BROADCOM BCM5703X 0x16a7 BCM5703X 10/100/1000 Ethernet
|
|||
product BROADCOM BCM5704C 0x1648 BCM5704C Gigabit Ethernet (1000BASE-T)
|
||||
product BROADCOM BCM5704S 0x16a8 BCM5704S Gigabit Ethernet (1000BASE-X)
|
||||
product BROADCOM BCM5705 0x1653 BCM5705 10/100/1000 Ethernet
|
||||
product BROADCOM BCM5705M 0x165d BCM5705M 10/100/1000 Ethernet
|
||||
product BROADCOM BCM4401 0x4401 BCM4401 10/100 Ethernet
|
||||
|
||||
/* Brooktree products */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pcidevs.h,v 1.553 2003/07/14 08:01:45 jmmv Exp $ */
|
||||
/* $NetBSD: pcidevs.h,v 1.554 2003/07/17 11:44:28 hannken Exp $ */
|
||||
|
||||
/*
|
||||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
|
|
@ -1042,6 +1042,7 @@
|
|||
#define PCI_PRODUCT_BROADCOM_BCM5704C 0x1648 /* BCM5704C Gigabit Ethernet (1000BASE-T) */
|
||||
#define PCI_PRODUCT_BROADCOM_BCM5704S 0x16a8 /* BCM5704S Gigabit Ethernet (1000BASE-X) */
|
||||
#define PCI_PRODUCT_BROADCOM_BCM5705 0x1653 /* BCM5705 10/100/1000 Ethernet */
|
||||
#define PCI_PRODUCT_BROADCOM_BCM5705M 0x165d /* BCM5705M 10/100/1000 Ethernet */
|
||||
#define PCI_PRODUCT_BROADCOM_BCM4401 0x4401 /* BCM4401 10/100 Ethernet */
|
||||
|
||||
/* Brooktree products */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pcidevs_data.h,v 1.551 2003/07/14 08:01:47 jmmv Exp $ */
|
||||
/* $NetBSD: pcidevs_data.h,v 1.552 2003/07/17 11:44:28 hannken Exp $ */
|
||||
|
||||
/*
|
||||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
|
|
@ -2187,6 +2187,12 @@ const struct pci_knowndev pci_knowndevs[] = {
|
|||
"Broadcom Corporation",
|
||||
"BCM5705 10/100/1000 Ethernet",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
|
||||
0,
|
||||
"Broadcom Corporation",
|
||||
"BCM5705M 10/100/1000 Ethernet",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
|
||||
0,
|
||||
|
|
|
|||
Loading…
Reference in New Issue