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Some fixes and enhancements: 

Both if_bge* and brgphy.[ch]:
    Check the parent's MAC and use the quirk code for the bug like OpenBSD and
    FreeBSD. Some bugs can't identify the PHY ID. For example, 5704 Ax has the
    ADC bug, but 5704 A3 and 5704 B0 have the same PHY ID and revision. Add
    BGE_PHY_CRC_BUG, BGE_PHY_ADC_BUG, BGE_PHY_5704_A0_BUG, BGE_PHY_JITTER_BUG,
    BGE_PHY_ADJUST_TRIM and BGE_PHY_BER_BUG for this flag. Some of the DSP
    patches are newly taken from OpenBSD and FreeBSD.

  if_bge*:
    Remove duplicated BGE_CHIPID_BCM5714_A0 entry in the known CHIPID table.
    Fix obsolete comments.

  brgphy.[ch]:
    Add some PHY IDs.

TODO:
  Add more three quirk code into bge and brgphy (the brgphy side's are
  currently #if0'ed).
  Add support for bnx into brgphy (currently #if0'ed)
This commit is contained in:
msaitoh 2009-04-19 11:10:36 +00:00
parent 559b0165b6
commit 4d9e9f6912
10 changed files with 341 additions and 188 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

392
sys/dev/mii/brgphy.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: brgphy.c,v 1.42 2009/04/07 18:05:54 dyoung Exp $ */
/* $NetBSD: brgphy.c,v 1.43 2009/04/19 11:10:36 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.42 2009/04/07 18:05:54 dyoung Exp $");
__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.43 2009/04/19 11:10:36 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -85,6 +85,11 @@ __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.42 2009/04/07 18:05:54 dyoung Exp $");
#include <dev/mii/brgphyreg.h>
#include <dev/pci/if_bgereg.h>
#if 0
#include <dev/pci/if_bnxreg.h>
#endif
static int brgphymatch(device_t, cfdata_t, void *);
static void brgphyattach(device_t, device_t, void *);
@ -96,48 +101,21 @@ static int brgphy_service(struct mii_softc *, struct mii_data *, int);
static void brgphy_status(struct mii_softc *);
static int brgphy_mii_phy_auto(struct mii_softc *);
static void brgphy_loop(struct mii_softc *);
static void brgphy_reset(struct mii_softc *);
static void brgphy_bcm5401_dspcode(struct mii_softc *);
static void brgphy_bcm5411_dspcode(struct mii_softc *);
static void brgphy_bcm5421_dspcode(struct mii_softc *);
static void brgphy_bcm54k2_dspcode(struct mii_softc *);
static void brgphy_adc_bug(struct mii_softc *);
static void brgphy_5704_a0_bug(struct mii_softc *);
static void brgphy_ber_bug(struct mii_softc *);
static void brgphy_crc_bug(struct mii_softc *);
static void brgphy_5401_reset(struct mii_softc *);
static void brgphy_5411_reset(struct mii_softc *);
static void brgphy_5703_reset(struct mii_softc *);
static void brgphy_5704_reset(struct mii_softc *);
static void brgphy_5705_reset(struct mii_softc *);
static void brgphy_5750_reset(struct mii_softc *);
static void brgphy_5755_reset(struct mii_softc *);
static const struct mii_phy_funcs brgphy_funcs = {
brgphy_service, brgphy_status, mii_phy_reset,
brgphy_service, brgphy_status, brgphy_reset,
};
static const struct mii_phy_funcs brgphy_5401_funcs = {
brgphy_service, brgphy_status, brgphy_5401_reset,
};
static const struct mii_phy_funcs brgphy_5411_funcs = {
brgphy_service, brgphy_status, brgphy_5411_reset,
};
static const struct mii_phy_funcs brgphy_5703_funcs = {
brgphy_service, brgphy_status, brgphy_5703_reset,
};
static const struct mii_phy_funcs brgphy_5704_funcs = {
brgphy_service, brgphy_status, brgphy_5704_reset,
};
static const struct mii_phy_funcs brgphy_5705_funcs = {
brgphy_service, brgphy_status, brgphy_5705_reset,
};
const struct mii_phy_funcs brgphy_5750_funcs = {
brgphy_service, brgphy_status, brgphy_5750_reset,
};
const struct mii_phy_funcs brgphy_5755_funcs = {
brgphy_service, brgphy_status, brgphy_5755_reset,
};
static const struct mii_phydesc brgphys[] = {
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400,
MII_STR_BROADCOM_BCM5400 },
@ -151,6 +129,12 @@ static const struct mii_phydesc brgphys[] = {
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421,
MII_STR_BROADCOM_BCM5421 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2,
MII_STR_BROADCOM_BCM54K2 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462,
MII_STR_BROADCOM_BCM5462 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701,
MII_STR_BROADCOM_BCM5701 },
@ -178,6 +162,9 @@ static const struct mii_phydesc brgphys[] = {
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C,
MII_STR_BROADCOM_BCM5708C },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722,
MII_STR_BROADCOM2_BCM5722 },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755,
MII_STR_BROADCOM2_BCM5755 },
@ -191,13 +178,6 @@ static const struct mii_phydesc brgphys[] = {
NULL },
};
static void bcm5401_load_dspcode(struct mii_softc *);
static void bcm5411_load_dspcode(struct mii_softc *);
static void bcm5703_load_dspcode(struct mii_softc *);
static void bcm5704_load_dspcode(struct mii_softc *);
static void bcm5750_load_dspcode(struct mii_softc *);
static void bcm5755_load_dspcode(struct mii_softc *);
static int
brgphymatch(struct device *parent, struct cfdata *match,
void *aux)
@ -226,67 +206,11 @@ brgphyattach(struct device *parent, struct device *self, void *aux)
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
sc->mii_mpd_rev = MII_REV(ma->mii_id2);
sc->mii_pdata = mii;
sc->mii_flags = ma->mii_flags;
sc->mii_anegticks = MII_ANEGTICKS;
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM_ALT1) {
sc->mii_funcs = &brgphy_5750_funcs;
aprint_normal_dev(self, "using BCM5750 DSP patch\n");
} else {
switch (MII_MODEL(ma->mii_id2)) {
case MII_MODEL_BROADCOM_BCM5400:
sc->mii_funcs = &brgphy_5401_funcs;
aprint_normal_dev(self, "using BCM5401 DSP patch\n");
break;
case MII_MODEL_BROADCOM_BCM5401:
if (MII_REV(ma->mii_id2) == 1 || MII_REV(ma->mii_id2) == 3) {
sc->mii_funcs = &brgphy_5401_funcs;
aprint_normal_dev(self, "using BCM5401 DSP patch\n");
} else
sc->mii_funcs = &brgphy_funcs;
break;
case MII_MODEL_BROADCOM_BCM5411:
sc->mii_funcs = &brgphy_5411_funcs;
aprint_normal_dev(self, "using BCM5411 DSP patch\n");
break;
#ifdef notyet /* unverified, untested */
case MII_MODEL_BROADCOM_BCM5703:
sc->mii_funcs = &brgphy_5703_funcs;
aprint_normal_dev(self, "using BCM5703 DSP patch\n");
break;
#endif
case MII_MODEL_BROADCOM_BCM5704:
sc->mii_funcs = &brgphy_5704_funcs;
aprint_normal_dev(self, "using BCM5704 DSP patch\n");
break;
case MII_MODEL_BROADCOM_BCM5705:
sc->mii_funcs = &brgphy_5705_funcs;
break;
case MII_MODEL_BROADCOM_BCM5714:
case MII_MODEL_BROADCOM_BCM5780:
case MII_MODEL_BROADCOM_BCM5708C:
case MII_MODEL_BROADCOM_BCM5750:
case MII_MODEL_BROADCOM_BCM5752:
sc->mii_funcs = &brgphy_5750_funcs;
break;
case MII_MODEL_BROADCOM2_BCM5754:
case MII_MODEL_BROADCOM2_BCM5755:
sc->mii_funcs = &brgphy_5755_funcs;
break;
default:
sc->mii_funcs = &brgphy_funcs;
break;
}
}
sc->mii_funcs = &brgphy_funcs;
PHY_RESET(sc);
@ -408,12 +332,22 @@ setit:
if (sc->mii_media_active != mii->mii_media_active ||
sc->mii_media_status != mii->mii_media_status ||
cmd == MII_MEDIACHG) {
mii_phy_update(sc, cmd);
if (sc->mii_funcs == &brgphy_5401_funcs)
bcm5401_load_dspcode(sc);
else if (sc->mii_funcs == &brgphy_5411_funcs)
bcm5411_load_dspcode(sc);
switch (sc->mii_mpd_model) {
case MII_MODEL_BROADCOM_BCM5400:
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5401:
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5411:
brgphy_bcm5411_dspcode(sc);
break;
}
}
/* Callback if something changed. */
mii_phy_update(sc, cmd);
return (0);
}
@ -540,65 +474,162 @@ brgphy_loop(struct mii_softc *sc)
}
static void
brgphy_5401_reset(struct mii_softc *sc)
brgphy_reset(struct mii_softc *sc)
{
struct bge_softc *bge_sc = NULL;
#if 0
struct bnx_softc *bnx_sc = NULL;
#endif
const char *devname;
devname = device_parent(sc->mii_dev)->dv_cfdriver->cd_name;
mii_phy_reset(sc);
bcm5401_load_dspcode(sc);
}
static void
brgphy_5411_reset(struct mii_softc *sc)
{
switch (sc->mii_mpd_model) {
case MII_MODEL_BROADCOM_BCM5400:
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5401:
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
brgphy_bcm5401_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5411:
brgphy_bcm5411_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM5421:
brgphy_bcm5421_dspcode(sc);
break;
case MII_MODEL_BROADCOM_BCM54K2:
brgphy_bcm54k2_dspcode(sc);
break;
}
mii_phy_reset(sc);
bcm5411_load_dspcode(sc);
}
/* Handle any bge (NetXtreme/NetLink) workarounds. */
if (strcmp(devname, "bge") == 0) {
if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
bge_sc = sc->mii_pdata->mii_ifp->if_softc;
if (bge_sc->bge_flags & BGE_PHY_ADC_BUG)
brgphy_adc_bug(sc);
if (bge_sc->bge_flags & BGE_PHY_5704_A0_BUG)
brgphy_5704_a0_bug(sc);
if (bge_sc->bge_flags & BGE_PHY_BER_BUG)
brgphy_ber_bug(sc);
else if (bge_sc->bge_flags & BGE_PHY_JITTER_BUG) {
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG,
0x000a);
static void
brgphy_5703_reset(struct mii_softc *sc)
{
if (bge_sc->bge_flags & BGE_PHY_ADJUST_TRIM) {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
0x110b);
PHY_WRITE(sc, BRGPHY_TEST1,
BRGPHY_TEST1_TRIM_EN | 0x4);
} else {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
0x010b);
}
mii_phy_reset(sc);
bcm5703_load_dspcode(sc);
}
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
}
if (bge_sc->bge_flags & BGE_PHY_CRC_BUG)
brgphy_crc_bug(sc);
static void
brgphy_5704_reset(struct mii_softc *sc)
{
#if 0
/* Set Jumbo frame settings in the PHY. */
if (bge_sc->bge_flags & BGE_JUMBO_CAP)
brgphy_jumbo_settings(sc);
#endif
mii_phy_reset(sc);
bcm5704_load_dspcode(sc);
}
/* Adjust output voltage */
if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
/*
* Hardware bug workaround. Do nothing since after
* reset the 5705 PHY would get stuck in 10/100 MII mode.
*/
#if 0
/* Enable Ethernet@Wirespeed */
if (!(bge_sc->bge_flags & BGE_NO_ETH_WIRE_SPEED))
brgphy_eth_wirespeed(sc);
static void
brgphy_5705_reset(struct mii_softc *sc)
{
}
/* Enable Link LED on Dell boxes */
if (bge_sc->bge_flags & BGE_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
& ~BRGPHY_PHY_EXTCTL_3_LED);
}
#endif
}
#if 0 /* not yet */
/* Handle any bnx (NetXtreme II) workarounds. */
} else if (strcmp(devname, "bnx") == 0) {
bnx_sc = sc->mii_pdata->mii_ifp->if_softc;
static void
brgphy_5750_reset(struct mii_softc *sc)
{
mii_phy_reset(sc);
bcm5750_load_dspcode(sc);
}
if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) {
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
static void
brgphy_5755_reset(struct mii_softc *sc)
{
mii_phy_reset(sc);
bcm5755_load_dspcode(sc);
/* Enable fiber mode and autodetection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
/* Enable parallel detection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
/* Advertise 2.5G support through next page during autoneg */
if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG)
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
/* Increase TX signal amplitude */
if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) ||
(BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) ||
(BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &
~BRGPHY_5708S_PG5_TXACTL1_VCM);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
(bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bnx_sc->bnx_port_hw_cfg &
BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
} else {
if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
brgphy_ber_bug(sc);
/* Set Jumbo frame settings in the PHY. */
brgphy_jumbo_settings(sc);
/* Enable Ethernet@Wirespeed */
brgphy_eth_wirespeed(sc);
}
}
#endif
}
}
/* Turn off tap power management on 5401. */
static void
bcm5401_load_dspcode(struct mii_softc *sc)
brgphy_bcm5401_dspcode(struct mii_softc *sc)
{
static const struct {
int reg;
@ -625,7 +656,7 @@ bcm5401_load_dspcode(struct mii_softc *sc)
}
static void
bcm5411_load_dspcode(struct mii_softc *sc)
brgphy_bcm5411_dspcode(struct mii_softc *sc)
{
static const struct {
int reg;
@ -642,8 +673,44 @@ bcm5411_load_dspcode(struct mii_softc *sc)
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
}
void
brgphy_bcm5421_dspcode(struct mii_softc *sc)
{
uint16_t data;
/* Set Class A mode */
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
/* Set FFE gamma override to -0.125 */
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
}
void
brgphy_bcm54k2_dspcode(struct mii_softc *sc)
{
static const struct {
int reg;
uint16_t val;
} dspcode[] = {
{ 4, 0x01e1 },
{ 9, 0x0300 },
{ 0, 0 },
};
int i;
for (i = 0; dspcode[i].reg != 0; i++)
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
}
static void
bcm5703_load_dspcode(struct mii_softc *sc)
brgphy_adc_bug(struct mii_softc *sc)
{
static const struct {
int reg;
@ -652,6 +719,9 @@ bcm5703_load_dspcode(struct mii_softc *sc)
{ BRGPHY_MII_AUXCTL, 0x0c00 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
{ BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
{ BRGPHY_MII_DSP_RW_PORT, 0x0323 },
{ BRGPHY_MII_AUXCTL, 0x0400 },
{ 0, 0 },
};
int i;
@ -661,7 +731,7 @@ bcm5703_load_dspcode(struct mii_softc *sc)
}
static void
bcm5704_load_dspcode(struct mii_softc *sc)
brgphy_5704_a0_bug(struct mii_softc *sc)
{
static const struct {
int reg;
@ -678,7 +748,7 @@ bcm5704_load_dspcode(struct mii_softc *sc)
}
static void
bcm5750_load_dspcode(struct mii_softc *sc)
brgphy_ber_bug(struct mii_softc *sc)
{
static const struct {
int reg;
@ -700,18 +770,18 @@ bcm5750_load_dspcode(struct mii_softc *sc)
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
}
static void
bcm5755_load_dspcode(struct mii_softc *sc)
/* BCM5701 A0/B0 CRC bug workaround */
void
brgphy_crc_bug(struct mii_softc *sc)
{
static const struct {
int reg;
uint16_t val;
} dspcode[] = {
{ BRGPHY_MII_AUXCTL, 0x0c00 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
{ BRGPHY_MII_DSP_RW_PORT, 0x010b },
{ BRGPHY_MII_AUXCTL, 0x0400 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
{ 0x1c, 0x8c68 },
{ 0x1c, 0x8d68 },
{ 0x1c, 0x8c68 },
{ 0, 0 },
};
int i;

30
sys/dev/mii/brgphyreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: brgphyreg.h,v 1.3 2008/08/25 08:15:05 cegger Exp $ */
/* $NetBSD: brgphyreg.h,v 1.4 2009/04/19 11:10:36 msaitoh Exp $ */
/*
* Copyright (c) 2000
@ -94,6 +94,7 @@
#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */
#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */
#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */
#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00
@ -195,6 +196,33 @@
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_IMR_CRCERR 0x0001 /* CEC error */
/*******************************************************/
/* Begin: PHY register values for the 5706 PHY */
/*******************************************************/
/*
* Shadow register 0x1C, bit 15 is write enable,
* bits 14-10 select function (0x00 to 0x1F).
*/
#define BRGPHY_MII_SHADOW_1C 0x1C
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
/* When set, Regs 0-0x0F are 1000X, else 1000T */
#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
#define BRGPHY_TEST1 0x1E
#define BRGPHY_TEST1_TRIM_EN 0x0010
#define BRGPHY_TEST1_CRC_EN 0x8000
#define BRGPHY_MII_TEST2 0x1F
/*******************************************************/
/* End: PHY register values for the 5706 PHY */
/*******************************************************/
#define BRGPHY_INTRS \
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)

6
sys/dev/mii/files.mii
View File

@ -1,4 +1,4 @@
# $NetBSD: files.mii,v 1.42 2009/01/16 21:06:24 cegger Exp $
# $NetBSD: files.mii,v 1.43 2009/04/19 11:10:36 msaitoh Exp $
defflag opt_mii.h MIIVERBOSE
@ -24,6 +24,10 @@ device amhphy: mii_phy
attach amhphy at mii
file dev/mii/amhphy.c amhphy
device bmphy: mii_phy
attach bmphy at mii
file dev/mii/bmphy.c bmphy
device bmtphy: mii_phy
attach bmtphy at mii
file dev/mii/bmtphy.c bmtphy

20
sys/dev/mii/makphy.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: makphy.c,v 1.29 2008/11/17 03:04:27 dyoung Exp $ */
/* $NetBSD: makphy.c,v 1.30 2009/04/19 11:10:36 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.29 2008/11/17 03:04:27 dyoung Exp $");
__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.30 2009/04/19 11:10:36 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -167,10 +167,24 @@ static void
makphy_reset(struct mii_softc *sc)
{
uint16_t pscr;
#if 0
uint16_t reg;
#endif
/* Assert CRS on transmit */
pscr = PHY_READ(sc, MII_MAKPHY_PSCR);
PHY_WRITE(sc, MII_MAKPHY_PSCR, pscr | PSCR_CRS_ON_TX);
pscr |= PSCR_CRS_ON_TX;
#if 0
pscr &= ~PSCR_MDI_XOVER_MODE(XOVER_MODE_AUTO | XOVER_MODE_MDIX);
#endif
PHY_WRITE(sc, MII_MAKPHY_PSCR, pscr);
#if 0
reg = PHY_READ(sc, MII_MAKPHY_EPSC);
reg &= ~(EPSC_MASTER_DOWNSHIFT_MASK | EPSC_SLABE_DOWNSHIFT_MASK);
reg |= EPSC_MASTER_DOWNSHIFT_1X | EPSC_SLABE_DOWNSHIFT_1X;
reg |= EPSC_TX_CLK_25;
PHY_WRITE(sc, MII_MAKPHY_EPSC, reg);
#endif
mii_phy_reset(sc);
}

12
sys/dev/mii/makphyreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: makphyreg.h,v 1.3 2008/04/28 20:23:53 martin Exp $ */
/* $NetBSD: makphyreg.h,v 1.4 2009/04/19 11:10:36 msaitoh Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -88,8 +88,14 @@
#define MII_MAKPHY_EPSC 0x14 /* extended PHY specific control */
#define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */
#define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */
#define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */
#define EPSC_TX_CLK_2_5 0x0060
#define EPSC_TX_CLK_25 0x0070
#define EPSC_TX_CLK_0 0x0000
#define EPSC_MASTER_DOWNSHIFT_MASK 0x0c00
#define EPSC_MASTER_DOWNSHIFT_1X 0x0000
#define EPSC_SLABE_DOWNSHIFT_MASK 0x0300
#define EPSC_SLABE_DOWNSHIFT_1X 0x0100
#define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */
#define MII_MAKPHY_REC 0x15 /* receive error counter */

3
sys/dev/mii/miidevs
View File

@ -1,4 +1,4 @@
$NetBSD: miidevs,v 1.85 2009/04/19 10:25:25 msaitoh Exp $
$NetBSD: miidevs,v 1.86 2009/04/19 11:10:36 msaitoh Exp $
/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@ -199,6 +199,7 @@ model yyINTEL I82562ET 0x0033 i82562ET 10/100 media interface
model yyINTEL I82553 0x0035 i82553 10/100 media interface
model yyINTEL I82566 0x0039 i82566 10/100/1000 media interface
model xxMARVELL I82563 0x000a i82563 10/100/1000 media interface
model xxMARVELL I82567 0x000b i82567 10/100/1000 media interface
model yyINTEL IGP01E1000 0x0038 Intel IGP01E1000 Gigabit PHY

6
sys/dev/mii/miidevs.h
View File

@ -1,10 +1,10 @@
/* $NetBSD: miidevs.h,v 1.87 2009/04/19 10:25:49 msaitoh Exp $ */
/* $NetBSD: miidevs.h,v 1.88 2009/04/19 11:10:36 msaitoh Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: miidevs,v 1.85 2009/04/19 10:25:25 msaitoh Exp
* NetBSD: miidevs,v 1.84 2009/03/25 06:49:56 cegger Exp
*/
/*-
@ -270,6 +270,8 @@
#define MII_STR_yyINTEL_I82566 "i82566 10/100/1000 media interface"
#define MII_MODEL_xxMARVELL_I82563 0x000a
#define MII_STR_xxMARVELL_I82563 "i82563 10/100/1000 media interface"
#define MII_MODEL_xxMARVELL_I82567 0x000b
#define MII_STR_xxMARVELL_I82567 "i82567 10/100/1000 media interface"
#define MII_MODEL_yyINTEL_IGP01E1000 0x0038
#define MII_STR_yyINTEL_IGP01E1000 "Intel IGP01E1000 Gigabit PHY"

5
sys/dev/mii/miidevs_data.h
View File

@ -1,10 +1,10 @@
/* $NetBSD: miidevs_data.h,v 1.77 2009/04/19 10:25:48 msaitoh Exp $ */
/* $NetBSD: miidevs_data.h,v 1.78 2009/04/19 11:10:36 msaitoh Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: miidevs,v 1.85 2009/04/19 10:25:25 msaitoh Exp
* NetBSD: miidevs,v 1.84 2009/03/25 06:49:56 cegger Exp
*/
/*-
@ -101,6 +101,7 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82553, MII_STR_yyINTEL_I82553 },
{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82566, MII_STR_yyINTEL_I82566 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I82563, MII_STR_xxMARVELL_I82563 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I82567, MII_STR_xxMARVELL_I82567 },
{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_IGP01E1000, MII_STR_yyINTEL_IGP01E1000 },
{ MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC250, MII_STR_JMICRON_JMC250 },
{ MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC260, MII_STR_JMICRON_JMC260 },

42
sys/dev/pci/if_bge.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_bge.c,v 1.161 2009/04/16 01:38:34 msaitoh Exp $ */
/* $NetBSD: if_bge.c,v 1.162 2009/04/19 11:10:36 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.161 2009/04/16 01:38:34 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.162 2009/04/19 11:10:36 msaitoh Exp $");
#include "bpfilter.h"
#include "vlan.h"
@ -536,7 +536,6 @@ static const struct bge_revision {
{ BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
{ BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
{ BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
{ BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
{ BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
{ BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
{ BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
@ -568,13 +567,14 @@ static const struct bge_revision bge_majorrevs[] = {
{ BGE_ASICREV_BCM5703, "unknown BCM5703" },
{ BGE_ASICREV_BCM5704, "unknown BCM5704" },
{ BGE_ASICREV_BCM5705, "unknown BCM5705" },
{ BGE_ASICREV_BCM5750, "unknown BCM575x family" },
{ BGE_ASICREV_BCM5750, "unknown BCM5750" },
{ BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
{ BGE_ASICREV_BCM5714, "unknown BCM5714" },
{ BGE_ASICREV_BCM5752, "unknown BCM5752 family" },
{ BGE_ASICREV_BCM5755, "unknown BCM5755" },
{ BGE_ASICREV_BCM5780, "unknown BCM5780" },
{ BGE_ASICREV_BCM5787, "unknown BCM5787" },
/* 5754 and 5787 share the same ASIC ID */
{ BGE_ASICREV_BCM5787, "unknown BCM5787/5787" },
{ BGE_ASICREV_BCM5906, "unknown BCM5906" },
{ 0, NULL }
};
@ -2423,8 +2423,7 @@ bge_attach(device_t parent, device_t self, void *aux)
DELAY(1000); /* 27 usec is allegedly sufficent */
/*
* Save ASIC rev. Look up any quirks associated with this
* ASIC.
* Save ASIC rev.
*/
sc->bge_chipid =
pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) &
@ -2445,6 +2444,27 @@ bge_attach(device_t parent, device_t self, void *aux)
BGE_PCISTATE_PCI_BUSMODE) == 0)
sc->bge_flags |= BGE_PCIX;
if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
sc->bge_flags |= BGE_PHY_CRC_BUG;
if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX ||
BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX)
sc->bge_flags |= BGE_PHY_ADC_BUG;
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
sc->bge_flags |= BGE_PHY_5704_A0_BUG;
if (BGE_IS_5705_OR_BEYOND(sc)) {
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
sc->bge_flags |= BGE_PHY_JITTER_BUG;
if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
sc->bge_flags |= BGE_PHY_ADJUST_TRIM;
} else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)
sc->bge_flags |= BGE_PHY_BER_BUG;
}
/* Try to reset the chip. */
DPRINTFN(5, ("bge_reset\n"));
bge_reset(sc);
@ -2617,8 +2637,7 @@ bge_attach(device_t parent, device_t self, void *aux)
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
/* Pretend the user requested this setting */
sc->bge_ifmedia.ifm_media =
sc->bge_ifmedia.ifm_cur->ifm_media;
sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
} else {
/*
* Do transceiver setup.
@ -2737,10 +2756,7 @@ bge_reset(struct bge_softc *sc)
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
/*
* Disable the firmware fastboot feature on 5752 ASIC
* to avoid firmware timeout.
*/
/* Disable fastboot on controllers that support it. */
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)

13
sys/dev/pci/if_bgereg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_bgereg.h,v 1.50 2009/04/16 01:38:34 msaitoh Exp $ */
/* $NetBSD: if_bgereg.h,v 1.51 2009/04/19 11:10:36 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
* Copyright (c) 1997, 1998, 1999, 2001
@ -62,6 +62,11 @@
* Flat mode consumes so much host address space that it is not
* recommended.
*/
#include <machine/bus.h>
#include <net/if_ether.h>
#include <dev/pci/pcivar.h>
#define BGE_PAGE_ZERO 0x00000000
#define BGE_PAGE_ZERO_END 0x000000FF
#define BGE_SEND_RING_RCB 0x00000100
@ -2466,6 +2471,12 @@ struct txdmamap_pool_entry {
#define BGE_PCIE 0x00000040
#define BGE_PHY_FIBER_TBI 0x00000800
#define BGE_PHY_FIBER_MII 0x00001000
#define BGE_PHY_CRC_BUG 0x00002000
#define BGE_PHY_ADC_BUG 0x00004000
#define BGE_PHY_5704_A0_BUG 0x00008000
#define BGE_PHY_JITTER_BUG 0x00010000
#define BGE_PHY_BER_BUG 0x00020000
#define BGE_PHY_ADJUST_TRIM 0x00040000
#define BGE_IS_5788 0x00100000
struct bge_softc {