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791 Commits

Author SHA1 Message Date
Robert Xiao
2b80ab425b Return new UC_ERR_OVERFLOW instead of UC_ERR_NOMEM when reg buffer is too small 2023-06-16 15:30:59 -07:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost. 
Single reg_read/reg_write is now about 25% faster.
 2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication. 
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
 2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs. 
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
 2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
fa1f26138e
Fix missing stdint 
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
 2023-06-10 23:48:18 +02:00
mio
49ccbde2d0
Leave out essential files 
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
 2023-06-10 23:44:05 +02:00
mio
8dffbc159c
Add uc_ctl_get/set_tcg_buffer_size 
We still need this API because the virtual memory address space of

32 bits os is only 4GB and we default need 1G per instance

Credits to @ZehMatt for original idea

Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
 2023-06-10 23:36:02 +02:00
mio
f8c7969d65
Revert "Add uc_ctl_get/set_tcg_buffer_size" 
This reverts commit 3145e3c426 because not
properly co-authoer-ed.
 2023-06-10 23:29:56 +02:00
mio
3145e3c426
Add uc_ctl_get/set_tcg_buffer_size 2023-06-10 16:08:29 +02:00
mio
5057f9925b
Fix typo 2023-06-10 15:26:29 +02:00
mio
9de80cb625
Correct calling convention 2023-06-10 15:03:59 +02:00
mio
3d5b2643f0
Support demand paging via closures and seh 
Reverts 12a79192ee which exploits normal tcg mechanism

This uses a trampoline to pass extra data to seh handlers
 2023-06-10 14:04:56 +02:00
Takacs, Philipp
fa457a3a97 fix UC_MEM_WRITE_PROT callback 
callbacks work on the physical address.
 2023-05-22 15:38:37 +02:00
mio
994813a0e5
Also check cpu->stopped 2023-05-19 23:24:42 +02:00
mio
be2f092179
Merge remote-tracking branch 'phl/issuevtlb' into dev 2023-05-19 23:22:23 +02:00
mio
a24e53d794
Rebuild flags after writing to cp registers 
This is buggy as this momemt per https://github.com/unicorn-engine/unicorn/issues/1789#issuecomment-1546807410

We need either doc this or save more information for a context
 2023-05-14 13:35:31 +02:00
Takacs, Philipp
4a7b3b7a3a fixup! load_helper only call cpu_loop_exit() when emulation is running 2023-05-12 12:36:16 +02:00
Takacs, Philipp
073c4b74ca load_helper only call cpu_loop_exit() when emulation is running 
The load_helper is sometimes called from register writes. When the load
fails check if emulation is running before jump out of the emulated code.
 2023-05-09 14:58:40 +02:00
Takacs, Philipp
7bb1501bc2 use int128_get64 in memory_unmap 
This fixes build errors introduced by bbbc7856ac
 2023-04-17 17:48:58 +02:00
Mio
bbbc7856ac
Invalidate tb cache once mapping is removed 2023-04-12 20:56:54 +08:00
Matheus C. França
2d94e30988 Fix clang/mingw - missing getpagesize 
Based on msys2-packages patch:
https://github.com/msys2/MINGW-packages/pull/10543
 2023-04-03 11:08:27 -03:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks 
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
 2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb 
this virtuall tlb allows to use mmu indipendent of the architectur
 2023-03-28 13:50:11 +02:00
Takacs, Philipp
901034577a i386 call internal helper on special porpese register write 
Some registers writes have side effects. i.e. write to cr3 flush the tlb,
if the PG bit is set.
 2023-03-28 13:50:11 +02:00
Takacs, Philipp
f2eb1f4711 i386 mmu hack: Allow emulate usermode without mmu 
This basicaly mappes virtual addresses to physical addresses 1:1 when
the mmu is disabled in the cpu. So you can use the full 64 bit addressspace
without required to configure the mmu.
 2023-03-28 13:50:11 +02:00
Takacs, Philipp
4b327baaf7 make unicorn use the physical addresses 
This allows to emulate code witch fully uses the MMU. This is necesary
to allow full system emulation.
 2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request 
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
 2023-03-07 14:38:49 +01:00
Takacs, Philipp
14404ef04b [x86] don't hardcode cpuid results 
The cpuid results are set by the selected cpu.

CLOSES #1787
 2023-02-27 12:34:38 +01:00
mio
133504b504
Fix wrong IP in x86_16 because of cs_base not substracted 2023-02-20 20:21:56 +01:00
mio
3199dd88de
Detect AVX2 correctly for MSVC 2023-02-07 01:07:53 +01:00
Nguyen Anh Quynh
eb118528b1 rename memory_mapping() to find_memory_region() and simplify mem_map() 2023-02-06 17:59:16 +08:00
mio
a25adf84f0
Rename flags to avoid confusion 2023-01-28 22:18:39 +01:00
mio
513e797d46
Update comments of the page count 2023-01-28 22:10:39 +01:00
mio
12a79192ee
Demand paging on Windows 2023-01-28 22:04:43 +01:00
Nguyen Anh Quynh
9dc001d686 remove unused code in PPC & dis-asm.h 2022-12-07 01:36:44 +08:00
mio
9c5358c759
Respect QEMU ZMM_Q to work on big endian hosts 2022-10-28 17:37:02 +02:00
mio
6162708bb2
Hack more to support BE32 2022-10-21 11:30:22 +02:00
mio
3ea7857be3
Exit early when invalid read happens 
In this way, the target register won't be overwritten
 2022-10-20 21:57:28 +02:00
mio
13b8e2625f
Check PC range for mem hooks 2022-10-20 21:25:21 +02:00
mio
a5d4d30a31
Sync PC for mem ldst on aarch64 2022-10-20 21:19:18 +02:00
mio
35010035d7
Fix macro typo 
Thanks @roehling
 2022-10-20 20:10:27 +02:00
TSR Berry
442dd437e1
aarch64: Move FPCR and FPSR registers to not break compatibility 
Co-authored-by: merry <git@mary.rs>
 2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086
aarch64: Add FPCR and FPSR registers 
Co-authored-by: merry <git@mary.rs>
 2022-10-14 15:18:14 +02:00
mio
19d8876e23
Deep copy for arm cpu state 2022-10-01 00:14:08 +02:00
lazymio
5e060513a0
Merge pull request #1687 from relapids/clang_cl_support 
Allow building with clang-cl (using MSVC config) on Windows.
 2022-09-27 23:02:21 +02:00
mio
32a3a6865a
Don't resize user alloc-ed memory 2022-09-25 17:41:33 +02:00
Mio
a0e119c6f0
Format code 2022-08-31 23:27:24 +08:00
Mio
092014a6cc
Don't sync pc if user requests a restart 2022-08-31 23:27:05 +08:00
lazymio
a63002872f
Merge pull request #1688 from relapids/tricore_leak 
Fix memory leaks in TriCore target. (#1681)
 2022-08-31 22:07:10 +08:00