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aarch64: Add FPCR and FPSR registers

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Co-authored-by: merry <git@mary.rs>
This commit is contained in:
TSR Berry 2022-10-14 15:15:48 +02:00
parent b99ec09c90
commit 12fd4fc086
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GPG Key ID: 52353C0A4CCA15E2
2 changed files with 16 additions and 0 deletions
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4
include/unicorn/arm64.h
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@ -313,6 +313,10 @@ typedef enum uc_arm64_reg {
UC_ARM64_REG_PSTATE,
//> floating point control and status registers
UC_ARM64_REG_FPCR,
UC_ARM64_REG_FPSR,
//> exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
UC_ARM64_REG_ELR_EL0,
UC_ARM64_REG_ELR_EL1,

12
qemu/target/arm/unicorn_aarch64.c
View File

@ -210,6 +210,12 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value)
case UC_ARM64_REG_PSTATE:
*(uint32_t *)value = pstate_read(env);
break;
case UC_ARM64_REG_FPCR:
*(uint32_t *)value = vfp_get_fpcr(env);
break;
case UC_ARM64_REG_FPSR:
*(uint32_t *)value = vfp_get_fpsr(env);
break;
case UC_ARM64_REG_TTBR0_EL1:
*(uint64_t *)value = env->cp15.ttbr0_el[1];
break;
@ -303,6 +309,12 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value)
case UC_ARM64_REG_PSTATE:
pstate_write(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPCR:
vfp_set_fpcr(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPSR:
vfp_set_fpsr(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_TTBR0_EL1:
env->cp15.ttbr0_el[1] = *(uint64_t *)value;
break;