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Author SHA1 Message Date
Richard Henderson
e9efd4bcdc target/hppa: Decode d for cmpb instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
84e224d422 target/hppa: Decode d for bb instructions 
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
63c427c615 target/hppa: Decode d for sub instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
faf97ba157 target/hppa: Decode d for add instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
345aa35f15 target/hppa: Decode d for cmpclr instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
af24075333 target/hppa: Decode d for unit instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
fa8e3bed38 target/hppa: Decode d for logical instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
08db178544 target/hppa: Remove TARGET_HPPA64 
Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
e207b4aa71 target/hppa: Drop attempted gdbstub support for hppa64 
There is no support for hppa64 in gdb.  Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Mask CR_SAR writes to the width of the register: 5 or 6 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
0c01f9ba2d linux-user/hppa: Fixes for TARGET_ABI32 
Avoid target_ulong and use abi_* types.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
59963d8fdf target/hppa: Pass d to do_unit_cond 
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
4fa52edf91 target/hppa: Pass d to do_sed_cond 
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
b5af84233d target/hppa: Pass d to do_log_cond 
Hoist the resolution of d up one level above do_log_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
4fe9533acc target/hppa: Pass d to do_sub_cond 
Hoist the resolution of d up one level above do_sub_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
a751eb31b6 target/hppa: Pass d to do_cond 
Hoist the resolution of d up one level above do_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Helge Deller
f3618f59f3 target/hppa: sar register allows only 5 bits on 32-bit CPU 
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>
 2023-11-06 18:49:33 -08:00
Richard Henderson
f13bf343cc target/hppa: Mask inputs in copy_iaoq_entry 
Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
9a91dd8452 target/hppa: Use copy_iaoq_entry for link in do_ibranch 
We need to make sure the link is masked properly along the
use_nullify_skip path.  The other three settings of a link
register already use this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
a01809737e target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] 
This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.

Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
741322f471 target/hppa: Pass DisasContext to copy_iaoq_entry 
Interface change only, no functional effect.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
698240d19b target/hppa: Fix hppa64 addressing 
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
5718fe4cfe target/hppa: Adjust hppa_cpu_dump_state for hppa64 
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
ccdf741c48 target/hppa: Handle absolute addresses for pa2.0 
With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
931adff314 target/hppa: Update cpu_hppa_get/put_psw for hppa64 
With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
ca4c2008f5 target/hppa: Implement hppa_cpu_class_by_name 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
d3ae32d4d2 target/hppa: Implement cpu_list 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
9cf2112be4 target/hppa: Make HPPA_BTLB_ENTRIES variable 
Depend on hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
bd6243a33f target/hppa: Introduce TYPE_HPPA64_CPU 
Prepare for the qemu binary supporting both pa10 and pa20
at the same time.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
d781cb7798 target/hppa: Fix extrw and depw with sar for hppa64 
These are 32-bit operations regardless of processor.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
1e9ab9fbe0 target/hppa: Fix bb_sar for hppa64 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
bdcccc17ac target/hppa: Fix do_add, do_sub for hppa64 
Select the proper carry bit for input to the arithmetic
and for output for the condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
72ca87535e target/hppa: Fix trans_ds for hppa64 
This instruction always uses the input carry from bit 32,
but produces all 16 output carry bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
e1d635e871 target/hppa: Truncate rotate count in trans_shrpw_sar 
When forcing rotate by i32, the shift count must be as well.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
c1f55d9795 target/hppa: Fix load in do_load_32 
The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32
not tcg_gen_qemu_ld_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
0238e678eb target/hppa: Fix hppa64 case in machine.c 
Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
d4e5803316 target/hppa: Remove load_const 
Replace with tcg_constant_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
a6779861fd target/hppa: Remove get_temp_tl 
Replace with tcg_temp_new_tl without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
e12c63090b target/hppa: Remove get_temp 
Replace with tcg_temp_new without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
d7553f3591 target/hppa: Populate an interval tree with valid tlb entries 
Complete the data structure conversion started earlier.  This reduces
the perf overhead of hppa_get_physical_address from ~5% to ~0.25%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
09cae8255f target/hppa: Split out hppa_flush_tlb_range 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
f8cda28b8d target/hppa: Always report one page to tlb_set_page 
No need to trigger the large_page_mask code unnecessarily.
Drop the now unused HPPATLBEntry.page_size field.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
66866cc74f target/hppa: Use IntervalTreeNode in HPPATLBEntry 
Replace the va_b and va_b fields with the interval tree node.
The actual interval tree is not yet used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
729cd3506d target/hppa: Rename hppa_tlb_entry to HPPATLBEntry 
Rename to CamelCase per coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
bb67ec32a0 target/hppa: Include PSW_P in tb flags and mmu index 
Use a separate mmu index for PSW_P enabled vs disabled.
This means we can elide the tlb flush in cpu_hppa_put_psw
when PSW_P changes.  This turns out to be the majority
of all tlb flushes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Stefan Hajnoczi
3e01f1147a target/sparc: Explicitly compute condition codes 
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Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging

target/sparc: Explicitly compute condition codes

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# gpg: Signature made Mon 06 Nov 2023 04:09:46 HKT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu: (21 commits)
  target/sparc: Check for invalid cond in gen_compare_reg
  target/sparc: Implement UDIV inline
  target/sparc: Implement UDIVX and SDIVX inline
  target/sparc: Discard cpu_cond at the end of each insn
  target/sparc: Record entire jump condition in DisasContext
  target/sparc: Merge gen_op_next_insn into only caller
  target/sparc: Pass displacement to advance_jump_cond
  target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond
  target/sparc: Merge gen_branch2 into advance_pc
  target/sparc: Do flush_cond in advance_jump_cond
  target/sparc: Always copy conditions into a new temporary
  target/sparc: Change DisasCompare.c2 to int
  target/sparc: Remove DisasCompare.is_bool
  target/sparc: Remove CC_OP leftovers
  target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV
  target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB
  target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD
  target/sparc: Remove CC_OP_DIV
  target/sparc: Remove CC_OP_LOGIC
  target/sparc: Split psr and xcc into components
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2023-11-06 09:34:22 +08:00
Stefan Hajnoczi
f3604191e2 Migration Pull request (20231103) 
Hi
 
 In this PULL:
 - dirty limit fixes (hyman)
 - coverity issues (juan)
 
 Please apply.
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Merge tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quintela/qemu into staging

Migration Pull request (20231103)

Hi

In this PULL:
- dirty limit fixes (hyman)
- coverity issues (juan)

Please apply.

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# gpg: Signature made Fri 03 Nov 2023 20:04:40 HKT
# gpg:                using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full]
# gpg:                 aka "Juan Quintela <quintela@trasno.org>" [full]
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03  4B82 F487 EF18 5872 D723

* tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quintela/qemu:
  migration: Unlock mutex in error case
  docs/migration: Add the dirty limit section
  tests/migration: Introduce dirty-limit into guestperf
  tests/migration: Introduce dirty-ring-size option into guestperf
  tests: Add migration dirty-limit capability test
  system/dirtylimit: Drop the reduplicative check
  system/dirtylimit: Fix a race situation

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2023-11-06 08:37:22 +08:00
Stefan Hajnoczi
1d6e13c1c7 dump queue 
Hi
 
 The "dump" queue, with:
 - [PATCH v3 qemu 0/3] Allow dump-guest-memory to output standard kdump format
 - [PATCH v2 0/5] dump: Minor fixes & improvements
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Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging

dump queue

Hi

The "dump" queue, with:
- [PATCH v3 qemu 0/3] Allow dump-guest-memory to output standard kdump format
- [PATCH v2 0/5] dump: Minor fixes & improvements

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# 8A3lN6WaAT9dvM33pkeswZvGxg==
# =eSbp
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 03 Nov 2023 15:01:21 HKT
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg:                issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
  dump: Drop redundant check for empty dump
  dump: Improve some dump-guest-memory error messages
  dump: Recognize "fd:" protocols on Windows hosts
  dump: Fix g_array_unref(NULL) in dump-guest-memory
  dump: Rename qmp_dump_guest_memory() parameter to match QAPI schema
  dump: Add command interface for kdump-raw formats
  dump: Allow directly outputting raw kdump format
  dump: Pass DumpState to write_ functions

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2023-11-06 08:36:47 +08:00
Stefan Hajnoczi
9477a89c14 pull-loongarch-20231103 
-----BEGIN PGP SIGNATURE-----
 
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 =9RMx
 -----END PGP SIGNATURE-----

Merge tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20231103

# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZUSQIgAKCRBAov/yOSY+
# 31aIBADj5FzdUxyFB813SouAiEiyMdI4bN98AunomAk3Kt8PF1XPoP8kPzcjxcMI
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# J4uxs3Lv8nwPEvRb4zITAt8JQllLey1100j/uu4fU0Rx7vUcMA==
# =9RMx
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 03 Nov 2023 14:16:02 HKT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu:
  linux-user/loongarch64: Add LASX sigcontext save/restore
  linux-user/loongarch64: Add LSX sigcontext save/restore
  linux-user/loongarch64: Use abi_{ulong,uint} types
  linux-user/loongarch64: setup_sigframe() set 'end' context size 0
  linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context size
  linux-user/loongarch64: Use traps to track LSX/LASX usage
  target/loongarch: Support 4K page size
  target/loongarch: Implement query-cpu-model-expansion
  target/loongarch: Allow user enable/disable LSX/LASX features
  target/loongarch: Add cpu model 'max'

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2023-11-06 08:35:47 +08:00
Richard Henderson
2c4f56c9aa target/sparc: Check for invalid cond in gen_compare_reg 
Consolidate the test here; drop the "inverted logic".
Fix MOVr and FMOVR, which were missing the invalid test.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-05 12:07:21 -08:00
Richard Henderson
3a6b8de3e2 target/sparc: Implement UDIV inline 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-05 12:07:17 -08:00