target/hppa: Fix bb_sar for hppa64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -3073,14 +3073,21 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
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{
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TCGv_reg tmp, tcg_r;
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DisasCond cond;
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bool d = false;
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nullify_over(ctx);
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tmp = tcg_temp_new();
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tcg_r = load_gpr(ctx, a->r);
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tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
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if (cond_need_ext(ctx, d)) {
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/* Force shift into [32,63] */
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tcg_gen_ori_reg(tmp, cpu_sar, 32);
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tcg_gen_shl_reg(tmp, tcg_r, tmp);
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} else {
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tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
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}
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cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
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cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
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return do_cbranch(ctx, a->disp, a->n, &cond);
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}
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@ -3088,12 +3095,15 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
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{
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TCGv_reg tmp, tcg_r;
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DisasCond cond;
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bool d = false;
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int p;
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nullify_over(ctx);
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tmp = tcg_temp_new();
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tcg_r = load_gpr(ctx, a->r);
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tcg_gen_shli_reg(tmp, tcg_r, a->p);
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p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
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tcg_gen_shli_reg(tmp, tcg_r, p);
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cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
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return do_cbranch(ctx, a->disp, a->n, &cond);
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