mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/hppa: Decode d for add instructions

Browse Source 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 20:51:13 -07:00
parent 345aa35f15
commit faf97ba157
2 changed files with 19 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
target/hppa/insns.decode
View File

@ -62,7 +62,7 @@
&rr_cf_d t r cf d
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh
&rrr_cf_d_sh t r1 r2 cf d sh
&rri_cf t r i cf
&rri_cf_d t r i cf d
@ -76,8 +76,8 @@
@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
@ -166,11 +166,11 @@ uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh
add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh
add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0
add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0
add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
sub 000010 ..... ..... .... 010000 - ..... @rrr_cf
sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf

21
target/hppa/translate.c
View File

@ -1186,12 +1186,11 @@ static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res,
static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned shift, bool is_l,
bool is_tsv, bool is_tc, bool is_c, unsigned cf)
bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d)
{
TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp;
unsigned c = cf >> 1;
DisasCond cond;
bool d = false;
dest = tcg_temp_new();
cb = NULL;
@ -1256,7 +1255,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
ctx->null_cond = cond;
}
static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a,
static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a,
bool is_l, bool is_tsv, bool is_tc, bool is_c)
{
TCGv_reg tcg_r1, tcg_r2;
@ -1266,7 +1265,8 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a,
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf);
do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l,
is_tsv, is_tc, is_c, a->cf, a->d);
return nullify_end(ctx);
}
@ -1280,7 +1280,8 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
}
tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf);
/* All ADDI conditions are 32-bit. */
do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false);
return nullify_end(ctx);
}
@ -2635,27 +2636,27 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a)
return true;
}
static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a)
static bool trans_add(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, false, false, false);
}
static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a)
static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, true, false, false, false);
}
static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a)
static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, true, false, false);
}
static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a)
static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, false, false, true);
}
static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a)
static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, true, false, true);
}