- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers
using value of DMMU primary and secondary context registers, so we need to
flush softmmu translations when context registers are changed
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed
- stop translation block after writing to pstate and tl registers
- stop translation block after writing to alternate space
this can be optimized to stop only if address translation can be changed
by write operation (e.g. by comparing with MMU ASI values)
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
macros supervisor() and hypervisor() adjusted as well
- disable sparcv8 registers for TARGET_SPARC64
- fix cpu_mmu_index to use sparcv9 bits only
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- separate PRIV and PROT handling
- DPRINTF_MMU macro to clean up debug code
- dump mmu_idx, trap level and mmu context registers
along with address translation values
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Computing carry is trivial for some inputs. By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern).
Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use int32 types instead of target_ulong when computing ICC. This
simplifies the generated code for 32-bit host and 64-bit guest.
Use the same simplified expressions for ICC as were already used
for XCC in carry flag generation.
Simplify the ADD carry generation to not consider a possible carry-in.
Use the more complex carry computation for ADDX only. Use the same
carry algorithm for the XCC result of ADDX. Similarly for SUB/SUBX.
Use the ADD carry generation functions for TADD/TADDTV. Similarly
for SUB and TSUB/TSUBTV.
Tidy the code with respect to CODING_STYLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Return a target_ulong from compute_C_icc to match the width of the users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- fix off by one error in spill trap number bit for other window (must be bit 5)
- fixes invalid instruction issue with HelenOS
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- must use store address operand to demap, not store value
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu_get_ccr() returns a target_ulong, so a type cast is needed to avoid
wrong output on big endian hosts. We could also use TARGET_FMT_lx,
but that would print 8 instead of 2 digits.
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier
flags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actual
functions to op_helper.c.
Thanks to Igor Kovalenko for reporting.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Calculate only the carry flag for ADDX/SUBX instead of full
set of flags.
Thanks to Igor Kovalenko for spotting a bug with an earlier
version.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix errors missed in 2065061ede:
CC sparc64-softmmu/helper.o
cc1: warnings being treated as errors
/src/qemu/target-sparc/helper.c: In function 'get_physical_address':
/src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function
/src/qemu/target-sparc/helper.c:426: note: 'context' was declared here
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- increase max supported MMU modes to 6
- handle nucleus context asi
- handle secondary context asi
- handle non-faulting loads from secondary context
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- match global tte against any context
- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb
- should fix gcc warning about uninitialized context variable
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Single-stepping was not properly updating npc, resulting in some
instructions being executed twice. In addition, we were emitting
dead code at the end of the TB.
Fix both by teaching gen_goto_tb to avoid goto_tb for single-step
and removing the special-case code in gen_intermediate_code_internal.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use address_mask on both addr and addr+8 in both these routines,
rather than explicit masking with 0xffffffff.
Reformulate address_mask to return a result, rather than masking
a pass-by-reference argument.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
These clang errors are harmless but worth fixing:
CC ppc-softmmu/usb-ohci.o
/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body]
ohci->ctrl_head, ohci->ctrl_cur);
/src/qemu/hw/usb-ohci.c:1371:57: error: if statement has empty body [-Wempty-body]
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
CC sparc64-softmmu/translate.o
/src/qemu/target-sparc/translate.c:3173:37: error: if statement has empty body [-Wempty-body]
; // XXX
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Rather than creating new temporaries for constants, use the
ones created in disas_sparc_insn. Remember the temps created
there so that they can be freed at the end of the function.
Profile data collected by TCG while booting sparc-test kernel:
-avg temps/TB 70.61 max=421
+avg temps/TB 62.75 max=66
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The 32 and 64-bit definitions were swapped in the ifdef.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix a case where an exception happens with the
instruction in the delay slot.
Recovery of branch condition in the exception handling
code was not converted to TCG. Because the condition
was bogus, wrong NPC could be selected from the two
candidates.
A nice bug report with a test case can be found in:
https://bugs.launchpad.net/qemu/+bug/551814
Fix based on patch by Fabrice Bellard.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page. However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.
Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages. If the guest invalidates this region then flush the
whole TLB.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.
Signed-off-by: Richard Henderson <rth@twiddle.net>
b551ec04ca fixed
the compilation for 32 bit hosts, but introduced
a new error for 64 bit hosts:
tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use 32-bit arithmetic for the address offset calculation to fix a
build failure on 32-bit hosts.
Signed-off-by: Jay Foad <jay.foad@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
if the access check fails, the page can not be modified
and shouldn't be marked dirty.
The patch fixes the "hsfs_putpage: dirty HSFS page"
error in Solaris guests.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64 timer has tick counter which can be set and read,
and tick compare value used as deadline to fire timer interrupt.
The timer is not used as periodic timer, instead deadline
is set each time new timer interrupt is needed.
v3 -> v4:
- coding style
v2 -> v3:
- added missing timer debug output macro
- CPUTimer struct and typedef moved to cpu.h
- change CPU_SAVE_VERSION to 6, older save formats not supported
v1 -> v2:
- new conversion helpers cpu_to_timer_ticks and timer_to_cpu_ticks
- save offset from clock source to implement cpu_tick_set_count
- renamed struct sun4u_timer to CPUTimer
- load and save cpu timers
v0 -> v1:
- coding style
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- correctly fit to cwp if provided window number is out of range
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Common:
* Remove unnecessary 0x prefix
* Print %y
* Fix NZVC flag print order to match CPU bit order
Sparc64 specific:
* Print registers without line wrapping
* Print %f40-%f63
* Pretty print CCR flags
* Print %fsr and %fprs in full precision
* More consistent formatting
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
According to pages 9-31 - 9-34 of "SuperSPARC & MultiCache Controller
User's Manual":
1. "A lower priority fault may not overwrite the
MFSR status of a higher priority fault."
2. The MFAR is overwritten according to the policy defined for the MFSR
3. The overwrite bit is asserted if the fault status register (MFSR)
has been written more than once by faults of the same class
4. SuperSPARC will never place instruction fault addresses in the MFAR.
Implementation of points 1-3 allows booting Solaris 2.6 and 2.5.1.
v2: CODING_STYLE fixes
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu_check_irqs
- handle SOFTINT register TICK and STICK timer bits
- only check interrupt levels greater than PIL value
- handle preemption by higher level traps
cpu_exec
- handle CPU_INTERRUPT_HARD only if interrupts are enabled
- PIL 15 is not special level on sparcv9
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- pstate is 32bit variable, no need to pass 64bit value around
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
