The use of "tl" functions and a tmp64 is logically incompatible.
Use cpu_tmp0 instead.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
In all cases we don't have write-before-read problems.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove the last uses of cpu_tmp32. Unify the code between sparc64
and sparc32 by using the proper "tl" functions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
We don't need another temporary here. Load directly into the
register we want to set.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Now that get_temp_tl is used for get_src[12], we don't need to
pre-allocate these temporaries.
Fallout from this is moving some assignments around cas/casx to
avoid uninitialized variable warnings.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
All users of gen_movl_{reg_TN,TN_reg} are removed. At the same time,
make cpu_val a local variable for load/store disassembly.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Push the DisasContext down so that we can use gen_load/store_gpr
in sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This means we can avoid the incoming temporary, though the cleanup
of the existing temporaries is not performed in this patch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Only handle the easy cases directly within disas_sparc_insn.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Infrastructure to be used to clean up handling of temporaries.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Avoid speculatively computing flags before every potentially trapping
operation and instead do the flags computation when a trap actually
occurs. This gives approximately 30% speedup in emulation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Now that save_state never ends a BB, we don't need to copy
values into local temps around it.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Aka "normal" comparisons. We now have the infrastructure to
pass back non-boolean results from gen_compare. This will
automatically get used by both branches and conditional moves.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Now that we've cleaned up global temporary allocation, we can
continue translating the fallthru path of a conditional trap.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
There are 6 temporaries that disas_sparc_insn relies on having been
allocated. Now that they are no longer referenced across branches,
they need not be allocated as local temps.
Move the allocation/free of these temporaries to make it clear that
they are local to the translation of a single insn.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.
Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Share more code between unconditional and conditional paths.
Move the computation of the trap number into the conditional BB;
avoid using temporaries that have gone out of scope (cpu_tmp32)
or rely on local temps (cpu_dst).
Fully fold the exception number when the trap number is %g0+imm.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
For the moment gen_cond et al retain their existing interface,
using setcond to turn a (potential) comparison back into a boolean.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The arguments passed are always the same.
Pass down just DisasContext instead.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use the cpu_cond global register directly instead of passing it down.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use the cpu_cond global register directly instead of passing it down.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use the cpu_cond global register directly instead of passing it down.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
We always pass cpu_cond to the cond parameter. Use that global
register directly instead of passing it down.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
We always pass cpu_cond to the cond parameter. Use that global
register directly instead of passing it down.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
We always pass cpu_cond to the r_cond parameter. Use that global
register directly instead of passing it down.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
According to UltraSPARC - IIi User's manual:
14.1.11 Address Masking (Impdep #125)
When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps
transmit zero in the high-order 32-bits of the PC to their specified
destination registers.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Adjust generation of load and store templates so that the functions
take a parameter for CPUState instead of relying on global env.
Remove wrappers. Move remaining memory helpers to ldst_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make memory access helpers take a parameter for CPUState instead
of relying on global env. Introduce wrappers for load and store ops.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Scripted conversion:
sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc]
sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This patch replace the previous implementation with this simplified and
more complete version (no shutdown when psret == 1).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not
implemeneted at all. However, this is a very simple operation
so we're better off doing this inline.
Signed-off-by: Richard Henderson <rth@twiddle.net>
This reduces the size of the individual translation blocks, since
we only emit a single call for each FOP rather than three. In
addition, clear_float_exceptions expands inline to a single byte store.
Signed-off-by: Richard Henderson <rth@twiddle.net>
This allows a more efficient representation for 64-bit hosts.
It should be about the same for 32-bit hosts, as we can still
access the individual pieces of the double.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Begin using i64 quantities to manipulate double-precision values.
On a 64-bit host this will, for the moment, generate less efficient
code; on a 32-bit host code quality should be largely unchanged.
Code quality for 64-bit will be adjusted with a subsequent patch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Load, store, and "create destination". This version attempts to
change the behaviour of the translator as little as possible. We
previously used cpu_tmp32 as the temporary destination, and we
continue to use that. This will eventually allow a change in
representation of the fprs.
Change the name of the cpu_fpr array to make certain that all
instances are converted.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Make [su]div{,cc} helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make softint op helpers and Leon cache irq manager take a parameter
for CPUState instead of relying on global env. Move the functions
to int{32,64}_helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make CWP and PSTATE helpers take a parameter for CPUState instead
of relying on global env. Remove wrapper functions.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The MinGW-w64 gcc complains about wrong parameters for
gen_helper_fpadd16_s and three other functions.
gen_helper_fpadd16_s is declared like this (hidden in lots of macros):
static inline void
gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1,
TCGv_i32 arg2, TCGv_i32 arg3);
So it looks like cpu_env should be the 2nd parameter.
Please review this patch as I have no environment to test it
(maybe the 1st parameter should be cpu_dst?).
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make lazy condition code helpers take a parameter for CPUState instead
of relying on global env.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make floating point and VIS ops take a parameter for CPUState instead
of relying on global env.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Make raise_exception() and helper_debug() take a parameter for
CPUState instead of relying on global env. Move the functions
to helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Check whether dc->npc is dynamic before using its value for branch.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Implement %fprs.DU/DL bits.
The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31
and %f32-63 respectively.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix the problem that result values are not assigned to the destination
registers.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The destination registers of SIMD signed compare instructions
(fcmp*<16|32>) are not FP registers but general purpose r registers.
Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Translation used incorrectly CPUState fields directly to check
for FPU enable state and 32 bit address masking on Sparc64.
Fix by using TB flags instead.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
udivx and sdvix don't modify condition flags, so they shall not
overwrite cpu_cc_*
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tb_invalidate_page_range() was intended to be used to invalidate an
area of a TB which the guest explicitly flushes from i-cache. However,
QEMU detects writes to code areas where TBs have been generated, so
his has never been useful.
Delete the function, adjust callers.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix wrong number of bits used when sign extending the branch offset of BPcc
instructions.
Reported-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use TCG local to work around TCG register flush due to a branch.
Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Function gen_pc_load was introduced in commit
d2856f1ad4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c.
Parameter puc was needed by target-sparc until
commit d7da2a1040.
Remove searched_pc from the debug statement and remove both
parameters from the parameter list of gen_pc_load.
As the function name gen_pc_load was also misleading,
it is now called restore_state_to_opc. This new name
was suggested by Peter Maydell, thanks.
v2: Remove last parameter, too, and rename the function.
v3: Fix [] typo in target-arm/translate.c.
Fix wrong SHA1 object name in commit message (copy+paste error).
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where
sizeof(long) != sizeof(void *), especially for w64.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more
information on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager.
You can find code for these peripherals in the grlib_* files.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Since commit 5a4bb580cd, Xorg crashes on
a Debian Etch image. The commit itself is fine, but it triggers a bug
due to wrong computation of flags for udiv(cc) and sdiv(cc).
This patch only compute cc_src2 for the cc version of udiv/sdiv. It
also moves the update of cc_dst and cc_op to the helper, as it is
faster doing it here when there is already an helper.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- truncate and sign or zero extend operands before multiplication
- factor out common code to gen_op_multiply() with parameter to sign/zero extend
- call gen_op_multiply from gen_op_umul and gen_op_smul
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- rearrange code to break from switch when appropriate
- allow deprecated ldfsr insn
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- address masking for ldqf and stqf insns
- address masking for lddf and stdf insns
- address masking for translating ASI (Ultrasparc IIi)
v0->v1:
- move arch-specific code to helpers and drop more ifdefs at call sites
using new helper asi_address_mask()
- change user emulation to use asi_address_mask()
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed
- stop translation block after writing to pstate and tl registers
- stop translation block after writing to alternate space
this can be optimized to stop only if address translation can be changed
by write operation (e.g. by comparing with MMU ASI values)
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
macros supervisor() and hypervisor() adjusted as well
- disable sparcv8 registers for TARGET_SPARC64
- fix cpu_mmu_index to use sparcv9 bits only
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Computing carry is trivial for some inputs. By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern).
Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Calculate only the carry flag for ADDX/SUBX instead of full
set of flags.
Thanks to Igor Kovalenko for spotting a bug with an earlier
version.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Single-stepping was not properly updating npc, resulting in some
instructions being executed twice. In addition, we were emitting
dead code at the end of the TB.
Fix both by teaching gen_goto_tb to avoid goto_tb for single-step
and removing the special-case code in gen_intermediate_code_internal.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
These clang errors are harmless but worth fixing:
CC ppc-softmmu/usb-ohci.o
/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body]
ohci->ctrl_head, ohci->ctrl_cur);
/src/qemu/hw/usb-ohci.c:1371:57: error: if statement has empty body [-Wempty-body]
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
CC sparc64-softmmu/translate.o
/src/qemu/target-sparc/translate.c:3173:37: error: if statement has empty body [-Wempty-body]
; // XXX
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Rather than creating new temporaries for constants, use the
ones created in disas_sparc_insn. Remember the temps created
there so that they can be freed at the end of the function.
Profile data collected by TCG while booting sparc-test kernel:
-avg temps/TB 70.61 max=421
+avg temps/TB 62.75 max=66
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
