target-sparc: Make the cpu_addr variable local to load/store handling
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -48,7 +48,7 @@ static TCGv cpu_y;
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#ifndef CONFIG_USER_ONLY
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static TCGv cpu_tbr;
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#endif
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static TCGv cpu_cond, cpu_dst, cpu_addr;
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static TCGv cpu_cond, cpu_dst;
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#ifdef TARGET_SPARC64
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static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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static TCGv cpu_gsr;
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@ -4596,20 +4596,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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case 3: /* load/store instructions */
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{
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unsigned int xop = GET_FIELD(insn, 7, 12);
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/* ??? gen_address_mask prevents us from using a source
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register directly. Always generate a temporary. */
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TCGv cpu_addr = get_temp_tl(dc);
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cpu_src1 = get_src1(dc, insn);
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if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
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tcg_gen_mov_tl(cpu_addr, cpu_src1);
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tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
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if (xop == 0x3c || xop == 0x3e) {
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/* V9 casa/casxa : no offset */
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} else if (IS_IMM) { /* immediate */
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_addi_tl(cpu_addr, cpu_src1, simm);
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if (simm != 0) {
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tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
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}
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} else { /* register */
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rs2 = GET_FIELD(insn, 27, 31);
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if (rs2 != 0) {
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cpu_src2 = gen_load_gpr(dc, rs2);
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tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
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} else {
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tcg_gen_mov_tl(cpu_addr, cpu_src1);
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tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
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}
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}
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if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
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@ -5251,12 +5253,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
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cpu_tmp32 = tcg_temp_new_i32();
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cpu_tmp64 = tcg_temp_new_i64();
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cpu_dst = tcg_temp_new();
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cpu_addr = tcg_temp_new();
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disas_sparc_insn(dc, insn);
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num_insns++;
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tcg_temp_free(cpu_addr);
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tcg_temp_free(cpu_dst);
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tcg_temp_free_i64(cpu_tmp64);
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tcg_temp_free_i32(cpu_tmp32);
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