mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Sparc: avoid AREG0 for memory access helpers

Browse Source 
Make memory access helpers take a parameter for CPUState instead
of relying on global env. Introduce wrappers for load and store ops.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-07-04 20:34:28 +00:00
parent 57d585f7d1
commit fe8d8f0f1c
6 changed files with 389 additions and 227 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile.target
View File

@ -103,7 +103,7 @@ $(libobj-y): $(GENERATED_HEADERS)
# HELPER_CFLAGS is used for all the code compiled with static register
# variables
op_helper.o ldst_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
# Note: this is a workaround. The real fix is to avoid compiling
# cpu_signal_handler() in user-exec.c.

84
target-sparc/cpu.h
View File

@ -586,8 +586,90 @@ void cpu_unassigned_access(CPUSPARCState *env1, target_phys_addr_t addr,
#if defined(TARGET_SPARC64)
target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx);
#endif
#define WRAP_LD(rettype, fn) \
rettype cpu_ ## fn (CPUSPARCState *env1, target_ulong addr)
WRAP_LD(uint32_t, ldub_kernel);
WRAP_LD(uint32_t, lduw_kernel);
WRAP_LD(uint32_t, ldl_kernel);
WRAP_LD(uint64_t, ldq_kernel);
WRAP_LD(uint32_t, ldub_user);
WRAP_LD(uint32_t, lduw_user);
WRAP_LD(uint32_t, ldl_user);
WRAP_LD(uint64_t, ldq_user);
WRAP_LD(uint64_t, ldfq_kernel);
WRAP_LD(uint64_t, ldfq_user);
#ifdef TARGET_SPARC64
WRAP_LD(uint32_t, ldub_hypv);
WRAP_LD(uint32_t, lduw_hypv);
WRAP_LD(uint32_t, ldl_hypv);
WRAP_LD(uint64_t, ldq_hypv);
WRAP_LD(uint64_t, ldfq_hypv);
WRAP_LD(uint32_t, ldub_nucleus);
WRAP_LD(uint32_t, lduw_nucleus);
WRAP_LD(uint32_t, ldl_nucleus);
WRAP_LD(uint64_t, ldq_nucleus);
WRAP_LD(uint32_t, ldub_kernel_secondary);
WRAP_LD(uint32_t, lduw_kernel_secondary);
WRAP_LD(uint32_t, ldl_kernel_secondary);
WRAP_LD(uint64_t, ldq_kernel_secondary);
WRAP_LD(uint32_t, ldub_user_secondary);
WRAP_LD(uint32_t, lduw_user_secondary);
WRAP_LD(uint32_t, ldl_user_secondary);
WRAP_LD(uint64_t, ldq_user_secondary);
#endif
#undef WRAP_LD
#define WRAP_ST(datatype, fn) \
void cpu_ ## fn (CPUSPARCState *env1, target_ulong addr, datatype val)
WRAP_ST(uint32_t, stb_kernel);
WRAP_ST(uint32_t, stw_kernel);
WRAP_ST(uint32_t, stl_kernel);
WRAP_ST(uint64_t, stq_kernel);
WRAP_ST(uint32_t, stb_user);
WRAP_ST(uint32_t, stw_user);
WRAP_ST(uint32_t, stl_user);
WRAP_ST(uint64_t, stq_user);
WRAP_ST(uint64_t, stfq_kernel);
WRAP_ST(uint64_t, stfq_user);
#ifdef TARGET_SPARC64
WRAP_ST(uint32_t, stb_hypv);
WRAP_ST(uint32_t, stw_hypv);
WRAP_ST(uint32_t, stl_hypv);
WRAP_ST(uint64_t, stq_hypv);
WRAP_ST(uint64_t, stfq_hypv);
WRAP_ST(uint32_t, stb_nucleus);
WRAP_ST(uint32_t, stw_nucleus);
WRAP_ST(uint32_t, stl_nucleus);
WRAP_ST(uint64_t, stq_nucleus);
WRAP_ST(uint32_t, stb_kernel_secondary);
WRAP_ST(uint32_t, stw_kernel_secondary);
WRAP_ST(uint32_t, stl_kernel_secondary);
WRAP_ST(uint64_t, stq_kernel_secondary);
WRAP_ST(uint32_t, stb_user_secondary);
WRAP_ST(uint32_t, stw_user_secondary);
WRAP_ST(uint32_t, stl_user_secondary);
WRAP_ST(uint64_t, stq_user_secondary);
#endif
#undef WRAP_ST
#endif
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

20
target-sparc/helper.h
View File

@ -18,11 +18,11 @@ DEF_HELPER_1(rdcwp, tl, env)
DEF_HELPER_2(wrcwp, void, env, tl)
DEF_HELPER_FLAGS_2(array8, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
DEF_HELPER_1(popc, tl, tl)
DEF_HELPER_3(ldda_asi, void, tl, int, int)
DEF_HELPER_4(ldf_asi, void, tl, int, int, int)
DEF_HELPER_4(stf_asi, void, tl, int, int, int)
DEF_HELPER_4(cas_asi, tl, tl, tl, tl, i32)
DEF_HELPER_4(casx_asi, tl, tl, tl, tl, i32)
DEF_HELPER_4(ldda_asi, void, env, tl, int, int)
DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int)
DEF_HELPER_5(stf_asi, void, env, tl, int, int, int)
DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32)
DEF_HELPER_5(casx_asi, tl, env, tl, tl, tl, i32)
DEF_HELPER_2(set_softint, void, env, i64)
DEF_HELPER_2(clear_softint, void, env, i64)
DEF_HELPER_2(write_softint, void, env, i64)
@ -30,7 +30,7 @@ DEF_HELPER_2(tick_set_count, void, ptr, i64)
DEF_HELPER_1(tick_get_count, i64, ptr)
DEF_HELPER_2(tick_set_limit, void, ptr, i64)
#endif
DEF_HELPER_2(check_align, void, tl, i32)
DEF_HELPER_3(check_align, void, env, tl, i32)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(save, void, env)
DEF_HELPER_1(restore, void, env)
@ -38,11 +38,11 @@ DEF_HELPER_3(udiv, tl, env, tl, tl)
DEF_HELPER_3(udiv_cc, tl, env, tl, tl)
DEF_HELPER_3(sdiv, tl, env, tl, tl)
DEF_HELPER_3(sdiv_cc, tl, env, tl, tl)
DEF_HELPER_2(ldqf, void, tl, int)
DEF_HELPER_2(stqf, void, tl, int)
DEF_HELPER_3(ldqf, void, env, tl, int)
DEF_HELPER_3(stqf, void, env, tl, int)
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
DEF_HELPER_4(ld_asi, i64, tl, int, int, int)
DEF_HELPER_4(st_asi, void, tl, i64, int, int)
DEF_HELPER_5(ld_asi, i64, env, tl, int, int, int)
DEF_HELPER_5(st_asi, void, env, tl, i64, int, int)
#endif
DEF_HELPER_2(ldfsr, void, env, i32)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)

356
target-sparc/ldst_helper.c
View File

@ -18,13 +18,8 @@
*/
#include "cpu.h"
#include "dyngen-exec.h"
#include "helper.h"
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
//#define DEBUG_MMU
//#define DEBUG_MXCC
//#define DEBUG_UNALIGNED
@ -69,16 +64,6 @@
#define QT0 (env->qt0)
#define QT1 (env->qt1)
#if !defined(CONFIG_USER_ONLY)
static void do_unassigned_access(target_phys_addr_t addr, int is_write,
int is_exec, int is_asi, int size);
#else
#ifdef TARGET_SPARC64
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
int is_asi, int size);
#endif
#endif
#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
/* Calculates TSB pointer value for fault page size 8k or 64k */
static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
@ -300,7 +285,7 @@ static inline int is_translating_asi(int asi)
#endif
}
static inline target_ulong asi_address_mask(CPUSPARCState *env1,
static inline target_ulong asi_address_mask(CPUSPARCState *env,
int asi, target_ulong addr)
{
if (is_translating_asi(asi)) {
@ -310,7 +295,7 @@ static inline target_ulong asi_address_mask(CPUSPARCState *env1,
}
}
void helper_check_align(target_ulong addr, uint32_t align)
void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
{
if (addr & align) {
#ifdef DEBUG_UNALIGNED
@ -372,7 +357,8 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
/* Leon3 cache control */
static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
uint64_t val, int size)
{
DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
addr, val, size);
@ -404,7 +390,8 @@ static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
};
}
static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
int size)
{
uint64_t ret = 0;
@ -436,14 +423,15 @@ static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
return ret;
}
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int sign)
{
uint64_t ret = 0;
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_addr = addr;
#endif
helper_check_align(addr, size - 1);
helper_check_align(env, addr, size - 1);
switch (asi) {
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
switch (addr) {
@ -451,7 +439,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
ret = leon3_cache_control_ld(addr, size);
ret = leon3_cache_control_ld(env, addr, size);
}
break;
case 0x01c00a00: /* MXCC control register */
@ -552,34 +540,34 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0xa: /* User data access */
switch (size) {
case 1:
ret = ldub_user(addr);
ret = cpu_ldub_user(env, addr);
break;
case 2:
ret = lduw_user(addr);
ret = cpu_lduw_user(env, addr);
break;
default:
case 4:
ret = ldl_user(addr);
ret = cpu_ldl_user(env, addr);
break;
case 8:
ret = ldq_user(addr);
ret = cpu_ldq_user(env, addr);
break;
}
break;
case 0xb: /* Supervisor data access */
switch (size) {
case 1:
ret = ldub_kernel(addr);
ret = cpu_ldub_kernel(env, addr);
break;
case 2:
ret = lduw_kernel(addr);
ret = cpu_lduw_kernel(env, addr);
break;
default:
case 4:
ret = ldl_kernel(addr);
ret = cpu_ldl_kernel(env, addr);
break;
case 8:
ret = ldq_kernel(addr);
ret = cpu_ldq_kernel(env, addr);
break;
}
break;
@ -669,7 +657,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
cpu_unassigned_access(env, addr, 0, 0, asi, size);
ret = 0;
break;
}
@ -694,9 +682,10 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
return ret;
}
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
int size)
{
helper_check_align(addr, size - 1);
helper_check_align(env, addr, size - 1);
switch (asi) {
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
switch (addr) {
@ -704,7 +693,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
leon3_cache_control_st(addr, val, size);
leon3_cache_control_st(env, addr, val, size);
}
break;
@ -902,34 +891,34 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 0xa: /* User data access */
switch (size) {
case 1:
stb_user(addr, val);
cpu_stb_user(env, addr, val);
break;
case 2:
stw_user(addr, val);
cpu_stw_user(env, addr, val);
break;
default:
case 4:
stl_user(addr, val);
cpu_stl_user(env, addr, val);
break;
case 8:
stq_user(addr, val);
cpu_stq_user(env, addr, val);
break;
}
break;
case 0xb: /* Supervisor data access */
switch (size) {
case 1:
stb_kernel(addr, val);
cpu_stb_kernel(env, addr, val);
break;
case 2:
stw_kernel(addr, val);
cpu_stw_kernel(env, addr, val);
break;
default:
case 4:
stl_kernel(addr, val);
cpu_stl_kernel(env, addr, val);
break;
case 8:
stq_kernel(addr, val);
cpu_stq_kernel(env, addr, val);
break;
}
break;
@ -952,8 +941,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
uint32_t src = val & ~3, dst = addr & ~3, temp;
for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
temp = ldl_kernel(src);
stl_kernel(dst, temp);
temp = cpu_ldl_kernel(env, src);
cpu_stl_kernel(env, dst, temp);
}
}
break;
@ -965,7 +954,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
uint32_t dst = addr & 7;
for (i = 0; i < 32; i += 8, dst += 8) {
stq_kernel(dst, val);
cpu_stq_kernel(env, dst, val);
}
}
break;
@ -1056,7 +1045,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
do_unassigned_access(addr, 1, 0, asi, size);
cpu_unassigned_access(env, addr, 1, 0, asi, size);
break;
}
#ifdef DEBUG_ASI
@ -1068,7 +1057,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
#else /* TARGET_SPARC64 */
#ifdef CONFIG_USER_ONLY
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int sign)
{
uint64_t ret = 0;
#if defined(DEBUG_ASI)
@ -1079,7 +1069,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
helper_raise_exception(env, TT_PRIV_ACT);
}
helper_check_align(addr, size - 1);
helper_check_align(env, addr, size - 1);
addr = asi_address_mask(env, asi, addr);
switch (asi) {
@ -1174,7 +1164,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
return ret;
}
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, int size)
{
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
@ -1183,7 +1174,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
helper_raise_exception(env, TT_PRIV_ACT);
}
helper_check_align(addr, size - 1);
helper_check_align(env, addr, size - 1);
addr = asi_address_mask(env, asi, addr);
/* Convert to little endian */
@ -1238,14 +1229,15 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
case 0x8a: /* Primary no-fault LE, RO */
case 0x8b: /* Secondary no-fault LE, RO */
default:
do_unassigned_access(addr, 1, 0, 1, size);
helper_raise_exception(env, TT_DATA_ACCESS);
return;
}
}
#else /* CONFIG_USER_ONLY */
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int sign)
{
uint64_t ret = 0;
#if defined(DEBUG_ASI)
@ -1261,7 +1253,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
helper_raise_exception(env, TT_PRIV_ACT);
}
helper_check_align(addr, size - 1);
helper_check_align(env, addr, size - 1);
addr = asi_address_mask(env, asi, addr);
/* process nonfaulting loads first */
@ -1302,17 +1294,17 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
if (cpu_hypervisor_mode(env)) {
switch (size) {
case 1:
ret = ldub_hypv(addr);
ret = cpu_ldub_hypv(env, addr);
break;
case 2:
ret = lduw_hypv(addr);
ret = cpu_lduw_hypv(env, addr);
break;
case 4:
ret = ldl_hypv(addr);
ret = cpu_ldl_hypv(env, addr);
break;
default:
case 8:
ret = ldq_hypv(addr);
ret = cpu_ldq_hypv(env, addr);
break;
}
} else {
@ -1320,33 +1312,33 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
if (asi & 1) {
switch (size) {
case 1:
ret = ldub_kernel_secondary(addr);
ret = cpu_ldub_kernel_secondary(env, addr);
break;
case 2:
ret = lduw_kernel_secondary(addr);
ret = cpu_lduw_kernel_secondary(env, addr);
break;
case 4:
ret = ldl_kernel_secondary(addr);
ret = cpu_ldl_kernel_secondary(env, addr);
break;
default:
case 8:
ret = ldq_kernel_secondary(addr);
ret = cpu_ldq_kernel_secondary(env, addr);
break;
}
} else {
switch (size) {
case 1:
ret = ldub_kernel(addr);
ret = cpu_ldub_kernel(env, addr);
break;
case 2:
ret = lduw_kernel(addr);
ret = cpu_lduw_kernel(env, addr);
break;
case 4:
ret = ldl_kernel(addr);
ret = cpu_ldl_kernel(env, addr);
break;
default:
case 8:
ret = ldq_kernel(addr);
ret = cpu_ldq_kernel(env, addr);
break;
}
}
@ -1356,33 +1348,33 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
if (asi & 1) {
switch (size) {
case 1:
ret = ldub_user_secondary(addr);
ret = cpu_ldub_user_secondary(env, addr);
break;
case 2:
ret = lduw_user_secondary(addr);
ret = cpu_lduw_user_secondary(env, addr);
break;
case 4:
ret = ldl_user_secondary(addr);
ret = cpu_ldl_user_secondary(env, addr);
break;
default:
case 8:
ret = ldq_user_secondary(addr);
ret = cpu_ldq_user_secondary(env, addr);
break;
}
} else {
switch (size) {
case 1:
ret = ldub_user(addr);
ret = cpu_ldub_user(env, addr);
break;
case 2:
ret = lduw_user(addr);
ret = cpu_lduw_user(env, addr);
break;
case 4:
ret = ldl_user(addr);
ret = cpu_ldl_user(env, addr);
break;
default:
case 8:
ret = ldq_user(addr);
ret = cpu_ldq_user(env, addr);
break;
}
}
@ -1420,17 +1412,17 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
{
switch (size) {
case 1:
ret = ldub_nucleus(addr);
ret = cpu_ldub_nucleus(env, addr);
break;
case 2:
ret = lduw_nucleus(addr);
ret = cpu_lduw_nucleus(env, addr);
break;
case 4:
ret = ldl_nucleus(addr);
ret = cpu_ldl_nucleus(env, addr);
break;
default:
case 8:
ret = ldq_nucleus(addr);
ret = cpu_ldq_nucleus(env, addr);
break;
}
break;
@ -1559,7 +1551,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x5f: /* D-MMU demap, WO */
case 0x77: /* Interrupt vector, WO */
default:
do_unassigned_access(addr, 0, 0, 1, size);
cpu_unassigned_access(env, addr, 0, 0, 1, size);
ret = 0;
break;
}
@ -1612,7 +1604,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
return ret;
}
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, int size)
{
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
@ -1627,7 +1620,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
helper_raise_exception(env, TT_PRIV_ACT);
}
helper_check_align(addr, size - 1);
helper_check_align(env, addr, size - 1);
addr = asi_address_mask(env, asi, addr);
/* Convert to little endian */
@ -1671,17 +1664,17 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
if (cpu_hypervisor_mode(env)) {
switch (size) {
case 1:
stb_hypv(addr, val);
cpu_stb_hypv(env, addr, val);
break;
case 2:
stw_hypv(addr, val);
cpu_stw_hypv(env, addr, val);
break;
case 4:
stl_hypv(addr, val);
cpu_stl_hypv(env, addr, val);
break;
case 8:
default:
stq_hypv(addr, val);
cpu_stq_hypv(env, addr, val);
break;
}
} else {
@ -1689,33 +1682,33 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
if (asi & 1) {
switch (size) {
case 1:
stb_kernel_secondary(addr, val);
cpu_stb_kernel_secondary(env, addr, val);
break;
case 2:
stw_kernel_secondary(addr, val);
cpu_stw_kernel_secondary(env, addr, val);
break;
case 4:
stl_kernel_secondary(addr, val);
cpu_stl_kernel_secondary(env, addr, val);
break;
case 8:
default:
stq_kernel_secondary(addr, val);
cpu_stq_kernel_secondary(env, addr, val);
break;
}
} else {
switch (size) {
case 1:
stb_kernel(addr, val);
cpu_stb_kernel(env, addr, val);
break;
case 2:
stw_kernel(addr, val);
cpu_stw_kernel(env, addr, val);
break;
case 4:
stl_kernel(addr, val);
cpu_stl_kernel(env, addr, val);
break;
case 8:
default:
stq_kernel(addr, val);
cpu_stq_kernel(env, addr, val);
break;
}
}
@ -1725,33 +1718,33 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
if (asi & 1) {
switch (size) {
case 1:
stb_user_secondary(addr, val);
cpu_stb_user_secondary(env, addr, val);
break;
case 2:
stw_user_secondary(addr, val);
cpu_stw_user_secondary(env, addr, val);
break;
case 4:
stl_user_secondary(addr, val);
cpu_stl_user_secondary(env, addr, val);
break;
case 8:
default:
stq_user_secondary(addr, val);
cpu_stq_user_secondary(env, addr, val);
break;
}
} else {
switch (size) {
case 1:
stb_user(addr, val);
cpu_stb_user(env, addr, val);
break;
case 2:
stw_user(addr, val);
cpu_stw_user(env, addr, val);
break;
case 4:
stl_user(addr, val);
cpu_stl_user(env, addr, val);
break;
case 8:
default:
stq_user(addr, val);
cpu_stq_user(env, addr, val);
break;
}
}
@ -1789,17 +1782,17 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
{
switch (size) {
case 1:
stb_nucleus(addr, val);
cpu_stb_nucleus(env, addr, val);
break;
case 2:
stw_nucleus(addr, val);
cpu_stw_nucleus(env, addr, val);
break;
case 4:
stl_nucleus(addr, val);
cpu_stl_nucleus(env, addr, val);
break;
default:
case 8:
stq_nucleus(addr, val);
cpu_stq_nucleus(env, addr, val);
break;
}
break;
@ -1991,13 +1984,13 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
case 0x8a: /* Primary no-fault LE, RO */
case 0x8b: /* Secondary no-fault LE, RO */
default:
do_unassigned_access(addr, 1, 0, 1, size);
cpu_unassigned_access(env, addr, 1, 0, 1, size);
return;
}
}
#endif /* CONFIG_USER_ONLY */
void helper_ldda_asi(target_ulong addr, int asi, int rd)
void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
{
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
|| (cpu_has_hypervisor(env)
@ -2012,22 +2005,22 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
#if !defined(CONFIG_USER_ONLY)
case 0x24: /* Nucleus quad LDD 128 bit atomic */
case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
helper_check_align(addr, 0xf);
helper_check_align(env, addr, 0xf);
if (rd == 0) {
env->gregs[1] = ldq_nucleus(addr + 8);
env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
if (asi == 0x2c) {
bswap64s(&env->gregs[1]);
}
} else if (rd < 8) {
env->gregs[rd] = ldq_nucleus(addr);
env->gregs[rd + 1] = ldq_nucleus(addr + 8);
env->gregs[rd] = cpu_ldq_nucleus(env, addr);
env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
if (asi == 0x2c) {
bswap64s(&env->gregs[rd]);
bswap64s(&env->gregs[rd + 1]);
}
} else {
env->regwptr[rd] = ldq_nucleus(addr);
env->regwptr[rd + 1] = ldq_nucleus(addr + 8);
env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
if (asi == 0x2c) {
bswap64s(&env->regwptr[rd]);
bswap64s(&env->regwptr[rd + 1]);
@ -2036,26 +2029,27 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
break;
#endif
default:
helper_check_align(addr, 0x3);
helper_check_align(env, addr, 0x3);
if (rd == 0) {
env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
} else if (rd < 8) {
env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
} else {
env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
}
break;
}
}
void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int rd)
{
unsigned int i;
target_ulong val;
helper_check_align(addr, 3);
helper_check_align(env, addr, 3);
addr = asi_address_mask(env, asi, addr);
switch (asi) {
@ -2067,9 +2061,9 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(addr, 0x3f);
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
env->fpr[rd/2].ll = helper_ld_asi(addr, asi & 0x8f, 8, 0);
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
}
return;
@ -2085,9 +2079,9 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(addr, 0x3f);
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 4) {
env->fpr[rd/2].ll = helper_ld_asi(addr, asi & 0x19, 8, 0);
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
}
return;
@ -2098,29 +2092,30 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
switch (size) {
default:
case 4:
val = helper_ld_asi(addr, asi, size, 0);
val = helper_ld_asi(env, addr, asi, size, 0);
if (rd & 1) {
env->fpr[rd/2].l.lower = val;
env->fpr[rd / 2].l.lower = val;
} else {
env->fpr[rd/2].l.upper = val;
env->fpr[rd / 2].l.upper = val;
}
break;
case 8:
env->fpr[rd/2].ll = helper_ld_asi(addr, asi, size, 0);
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
break;
case 16:
env->fpr[rd/2].ll = helper_ld_asi(addr, asi, 8, 0);
env->fpr[rd/2 + 1].ll = helper_ld_asi(addr + 8, asi, 8, 0);
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
break;
}
}
void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int rd)
{
unsigned int i;
target_ulong val;
helper_check_align(addr, 3);
helper_check_align(env, addr, 3);
addr = asi_address_mask(env, asi, addr);
switch (asi) {
@ -2134,9 +2129,9 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(addr, 0x3f);
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
helper_st_asi(addr, env->fpr[rd/2].ll, asi & 0x8f, 8);
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
}
return;
@ -2152,9 +2147,9 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(addr, 0x3f);
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
helper_st_asi(addr, env->fpr[rd/2].ll, asi & 0x19, 8);
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
}
return;
@ -2166,71 +2161,72 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
default:
case 4:
if (rd & 1) {
val = env->fpr[rd/2].l.lower;
val = env->fpr[rd / 2].l.lower;
} else {
val = env->fpr[rd/2].l.upper;
val = env->fpr[rd / 2].l.upper;
}
helper_st_asi(addr, val, asi, size);
helper_st_asi(env, addr, val, asi, size);
break;
case 8:
helper_st_asi(addr, env->fpr[rd/2].ll, asi, size);
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
break;
case 16:
helper_st_asi(addr, env->fpr[rd/2].ll, asi, 8);
helper_st_asi(addr + 8, env->fpr[rd/2 + 1].ll, asi, 8);
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
break;
}
}
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
target_ulong val2, uint32_t asi)
target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val1, target_ulong val2, uint32_t asi)
{
target_ulong ret;
val2 &= 0xffffffffUL;
ret = helper_ld_asi(addr, asi, 4, 0);
ret = helper_ld_asi(env, addr, asi, 4, 0);
ret &= 0xffffffffUL;
if (val2 == ret) {
helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
}
return ret;
}
target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
target_ulong val2, uint32_t asi)
target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val1, target_ulong val2,
uint32_t asi)
{
target_ulong ret;
ret = helper_ld_asi(addr, asi, 8, 0);
ret = helper_ld_asi(env, addr, asi, 8, 0);
if (val2 == ret) {
helper_st_asi(addr, val1, asi, 8);
helper_st_asi(env, addr, val1, asi, 8);
}
return ret;
}
#endif /* TARGET_SPARC64 */
void helper_ldqf(target_ulong addr, int mem_idx)
void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
{
/* XXX add 128 bit load */
CPU_QuadU u;
helper_check_align(addr, 7);
helper_check_align(env, addr, 7);
#if !defined(CONFIG_USER_ONLY)
switch (mem_idx) {
case MMU_USER_IDX:
u.ll.upper = ldq_user(addr);
u.ll.lower = ldq_user(addr + 8);
u.ll.upper = cpu_ldq_user(env, addr);
u.ll.lower = cpu_ldq_user(env, addr + 8);
QT0 = u.q;
break;
case MMU_KERNEL_IDX:
u.ll.upper = ldq_kernel(addr);
u.ll.lower = ldq_kernel(addr + 8);
u.ll.upper = cpu_ldq_kernel(env, addr);
u.ll.lower = cpu_ldq_kernel(env, addr + 8);
QT0 = u.q;
break;
#ifdef TARGET_SPARC64
case MMU_HYPV_IDX:
u.ll.upper = ldq_hypv(addr);
u.ll.lower = ldq_hypv(addr + 8);
u.ll.upper = cpu_ldq_hypv(env, addr);
u.ll.lower = cpu_ldq_hypv(env, addr + 8);
QT0 = u.q;
break;
#endif
@ -2245,29 +2241,29 @@ void helper_ldqf(target_ulong addr, int mem_idx)
#endif
}
void helper_stqf(target_ulong addr, int mem_idx)
void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
{
/* XXX add 128 bit store */
CPU_QuadU u;
helper_check_align(addr, 7);
helper_check_align(env, addr, 7);
#if !defined(CONFIG_USER_ONLY)
switch (mem_idx) {
case MMU_USER_IDX:
u.q = QT0;
stq_user(addr, u.ll.upper);
stq_user(addr + 8, u.ll.lower);
cpu_stq_user(env, addr, u.ll.upper);
cpu_stq_user(env, addr + 8, u.ll.lower);
break;
case MMU_KERNEL_IDX:
u.q = QT0;
stq_kernel(addr, u.ll.upper);
stq_kernel(addr + 8, u.ll.lower);
cpu_stq_kernel(env, addr, u.ll.upper);
cpu_stq_kernel(env, addr + 8, u.ll.lower);
break;
#ifdef TARGET_SPARC64
case MMU_HYPV_IDX:
u.q = QT0;
stq_hypv(addr, u.ll.upper);
stq_hypv(addr + 8, u.ll.lower);
cpu_stq_hypv(env, addr, u.ll.upper);
cpu_stq_hypv(env, addr + 8, u.ll.lower);
break;
#endif
default:
@ -2281,10 +2277,10 @@ void helper_stqf(target_ulong addr, int mem_idx)
#endif
}
#ifndef TARGET_SPARC64
#if !defined(CONFIG_USER_ONLY)
static void do_unassigned_access(target_phys_addr_t addr, int is_write,
int is_exec, int is_asi, int size)
#ifndef TARGET_SPARC64
void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
int fault_type;
@ -2342,15 +2338,9 @@ static void do_unassigned_access(target_phys_addr_t addr, int is_write,
tlb_flush(env, 1);
}
}
#endif
#else
#if defined(CONFIG_USER_ONLY)
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
int is_asi, int size)
#else
static void do_unassigned_access(target_phys_addr_t addr, int is_write,
int is_exec, int is_asi, int size)
#endif
void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
@ -2364,16 +2354,4 @@ static void do_unassigned_access(target_phys_addr_t addr, int is_write,
}
}
#endif
#if !defined(CONFIG_USER_ONLY)
void cpu_unassigned_access(CPUSPARCState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
CPUSPARCState *saved_env;
saved_env = env;
env = env1;
do_unassigned_access(addr, is_write, is_exec, is_asi, size);
env = saved_env;
}
#endif

102
target-sparc/op_helper.c
View File

@ -3,6 +3,7 @@
#include "helper.h"
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
void *retaddr);
@ -71,4 +72,103 @@ void tlb_fill(CPUSPARCState *env1, target_ulong addr, int is_write, int mmu_idx,
env = saved_env;
}
#endif /* !CONFIG_USER_ONLY */
#define WRAP_LD(rettype, fn) \
rettype cpu_ ## fn (CPUSPARCState *env1, target_ulong addr) \
{ \
CPUSPARCState *saved_env; \
rettype ret; \
\
saved_env = env; \
env = env1; \
ret = fn(addr); \
env = saved_env; \
return ret; \
}
WRAP_LD(uint32_t, ldub_kernel)
WRAP_LD(uint32_t, lduw_kernel)
WRAP_LD(uint32_t, ldl_kernel)
WRAP_LD(uint64_t, ldq_kernel)
WRAP_LD(uint32_t, ldub_user)
WRAP_LD(uint32_t, lduw_user)
WRAP_LD(uint32_t, ldl_user)
WRAP_LD(uint64_t, ldq_user)
WRAP_LD(uint64_t, ldfq_kernel)
WRAP_LD(uint64_t, ldfq_user)
#ifdef TARGET_SPARC64
WRAP_LD(uint32_t, ldub_hypv)
WRAP_LD(uint32_t, lduw_hypv)
WRAP_LD(uint32_t, ldl_hypv)
WRAP_LD(uint64_t, ldq_hypv)
WRAP_LD(uint64_t, ldfq_hypv)
WRAP_LD(uint32_t, ldub_nucleus)
WRAP_LD(uint32_t, lduw_nucleus)
WRAP_LD(uint32_t, ldl_nucleus)
WRAP_LD(uint64_t, ldq_nucleus)
WRAP_LD(uint32_t, ldub_kernel_secondary)
WRAP_LD(uint32_t, lduw_kernel_secondary)
WRAP_LD(uint32_t, ldl_kernel_secondary)
WRAP_LD(uint64_t, ldq_kernel_secondary)
WRAP_LD(uint32_t, ldub_user_secondary)
WRAP_LD(uint32_t, lduw_user_secondary)
WRAP_LD(uint32_t, ldl_user_secondary)
WRAP_LD(uint64_t, ldq_user_secondary)
#endif
#undef WRAP_LD
#define WRAP_ST(datatype, fn) \
void cpu_ ## fn (CPUSPARCState *env1, target_ulong addr, datatype val) \
{ \
CPUSPARCState *saved_env; \
\
saved_env = env; \
env = env1; \
fn(addr, val); \
env = saved_env; \
}
WRAP_ST(uint32_t, stb_kernel)
WRAP_ST(uint32_t, stw_kernel)
WRAP_ST(uint32_t, stl_kernel)
WRAP_ST(uint64_t, stq_kernel)
WRAP_ST(uint32_t, stb_user)
WRAP_ST(uint32_t, stw_user)
WRAP_ST(uint32_t, stl_user)
WRAP_ST(uint64_t, stq_user)
WRAP_ST(uint64_t, stfq_kernel)
WRAP_ST(uint64_t, stfq_user)
#ifdef TARGET_SPARC64
WRAP_ST(uint32_t, stb_hypv)
WRAP_ST(uint32_t, stw_hypv)
WRAP_ST(uint32_t, stl_hypv)
WRAP_ST(uint64_t, stq_hypv)
WRAP_ST(uint64_t, stfq_hypv)
WRAP_ST(uint32_t, stb_nucleus)
WRAP_ST(uint32_t, stw_nucleus)
WRAP_ST(uint32_t, stl_nucleus)
WRAP_ST(uint64_t, stq_nucleus)
WRAP_ST(uint32_t, stb_kernel_secondary)
WRAP_ST(uint32_t, stw_kernel_secondary)
WRAP_ST(uint32_t, stl_kernel_secondary)
WRAP_ST(uint64_t, stq_kernel_secondary)
WRAP_ST(uint32_t, stb_user_secondary)
WRAP_ST(uint32_t, stw_user_secondary)
WRAP_ST(uint32_t, stl_user_secondary)
WRAP_ST(uint64_t, stq_user_secondary)
#endif
#undef WRAP_ST
#endif

52
target-sparc/translate.c
View File

@ -1955,7 +1955,7 @@ static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(size);
r_sign = tcg_const_i32(sign);
gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign);
gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free_i32(r_sign);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
@ -1967,7 +1967,7 @@ static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(size);
gen_helper_st_asi(addr, src, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
}
@ -1979,7 +1979,7 @@ static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(size);
r_rd = tcg_const_i32(rd);
gen_helper_ldf_asi(addr, r_asi, r_size, r_rd);
gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
tcg_temp_free_i32(r_rd);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
@ -1992,7 +1992,7 @@ static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(size);
r_rd = tcg_const_i32(rd);
gen_helper_stf_asi(addr, r_asi, r_size, r_rd);
gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
tcg_temp_free_i32(r_rd);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
@ -2005,9 +2005,9 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(4);
r_sign = tcg_const_i32(0);
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free_i32(r_sign);
gen_helper_st_asi(addr, dst, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, dst, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
@ -2019,7 +2019,7 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
r_asi = gen_get_asi(insn, addr);
r_rd = tcg_const_i32(rd);
gen_helper_ldda_asi(addr, r_asi, r_rd);
gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
tcg_temp_free_i32(r_rd);
tcg_temp_free_i32(r_asi);
}
@ -2032,7 +2032,7 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(8);
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
}
@ -2046,7 +2046,7 @@ static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
r_val1 = tcg_temp_new();
gen_movl_reg_TN(rd, r_val1);
r_asi = gen_get_asi(insn, addr);
gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi);
gen_helper_cas_asi(dst, cpu_env, addr, r_val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
tcg_temp_free(r_val1);
}
@ -2058,7 +2058,7 @@ static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
gen_movl_reg_TN(rd, cpu_tmp64);
r_asi = gen_get_asi(insn, addr);
gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi);
gen_helper_casx_asi(dst, cpu_env, addr, cpu_tmp64, val2, r_asi);
tcg_temp_free_i32(r_asi);
}
@ -2072,7 +2072,7 @@ static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(size);
r_sign = tcg_const_i32(sign);
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free(r_sign);
tcg_temp_free(r_size);
tcg_temp_free(r_asi);
@ -2086,7 +2086,7 @@ static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
tcg_gen_extu_tl_i64(cpu_tmp64, src);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(size);
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
tcg_temp_free(r_size);
tcg_temp_free(r_asi);
}
@ -2099,11 +2099,11 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(4);
r_sign = tcg_const_i32(0);
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free(r_sign);
r_val = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(r_val, dst);
gen_helper_st_asi(addr, r_val, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
tcg_temp_free_i64(r_val);
tcg_temp_free(r_size);
tcg_temp_free(r_asi);
@ -2117,7 +2117,7 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
r_sign = tcg_const_i32(0);
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free(r_sign);
tcg_temp_free(r_size);
tcg_temp_free(r_asi);
@ -2136,7 +2136,7 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
tcg_temp_free(r_size);
tcg_temp_free(r_asi);
}
@ -2153,7 +2153,7 @@ static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
r_val = tcg_const_i64(0xffULL);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(1);
gen_helper_st_asi(addr, r_val, r_asi, r_size);
gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
tcg_temp_free_i64(r_val);
@ -4547,7 +4547,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_helper_restore(cpu_env);
gen_mov_pc_npc(dc, cpu_cond);
r_const = tcg_const_i32(3);
gen_helper_check_align(cpu_dst, r_const);
gen_helper_check_align(cpu_env, cpu_dst, r_const);
tcg_temp_free_i32(r_const);
tcg_gen_mov_tl(cpu_npc, cpu_dst);
dc->npc = DYNAMIC_PC;
@ -4577,7 +4577,7 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_temp_free(r_pc);
gen_mov_pc_npc(dc, cpu_cond);
r_const = tcg_const_i32(3);
gen_helper_check_align(cpu_dst, r_const);
gen_helper_check_align(cpu_env, cpu_dst, r_const);
tcg_temp_free_i32(r_const);
tcg_gen_mov_tl(cpu_npc, cpu_dst);
dc->npc = DYNAMIC_PC;
@ -4592,7 +4592,7 @@ static void disas_sparc_insn(DisasContext * dc)
goto priv_insn;
gen_mov_pc_npc(dc, cpu_cond);
r_const = tcg_const_i32(3);
gen_helper_check_align(cpu_dst, r_const);
gen_helper_check_align(cpu_env, cpu_dst, r_const);
tcg_temp_free_i32(r_const);
tcg_gen_mov_tl(cpu_npc, cpu_dst);
dc->npc = DYNAMIC_PC;
@ -4696,7 +4696,8 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
r_const = tcg_const_i32(7);
gen_helper_check_align(cpu_addr, r_const); // XXX remove
/* XXX remove alignment check */
gen_helper_check_align(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
@ -4921,7 +4922,7 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_FPU_FEATURE(dc, FLOAT128);
r_const = tcg_const_i32(dc->mem_idx);
gen_address_mask(dc, cpu_addr);
gen_helper_ldqf(cpu_addr, r_const);
gen_helper_ldqf(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(QFPREG(rd));
@ -4961,7 +4962,8 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_address_mask(dc, cpu_addr);
r_const = tcg_const_i32(7);
gen_helper_check_align(cpu_addr, r_const); // XXX remove
/* XXX remove alignment check */
gen_helper_check_align(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_movl_reg_TN(rd + 1, cpu_tmp0);
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
@ -5065,7 +5067,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_load_fpr_QT0(QFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
gen_address_mask(dc, cpu_addr);
gen_helper_stqf(cpu_addr, r_const);
gen_helper_stqf(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
break;
@ -5108,7 +5110,7 @@ static void disas_sparc_insn(DisasContext * dc)
goto jmp_insn;
}
r_const = tcg_const_i32(7);
gen_helper_check_align(cpu_addr, r_const);
gen_helper_check_align(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
}