Commit Graph

832 Commits

Author SHA1 Message Date
Marcelo Tosatti
75b10c4336 kvm: factor out kvm_has_msr_star
And add kvm_has_msr_hsave_pa(), to avoid warnings on older
kernels without support.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-10-21 13:37:29 -02:00
Marcelo Tosatti
aa851e365b kvm: add save/restore of MSR_VM_HSAVE_PA
commit 2bba4446746add456ceeb0e8359a43032a2ea333
Author: Alexander Graf <agraf@suse.de>
Date:   Thu Dec 18 15:38:32 2008 +0100

    Enable nested SVM support in userspace

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-10-21 13:37:17 -02:00
Hidetoshi Seto
d8da8574b1 Fix build on !KVM_CAP_MCE
This patch removes following warnings:

target-i386/kvm.c: In function 'kvm_put_msrs':
target-i386/kvm.c:782: error: unused variable 'i'
target-i386/kvm.c: In function 'kvm_get_msrs':
target-i386/kvm.c:1083: error: label at end of compound statement

Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-10-21 13:12:14 -02:00
Hidetoshi Seto
f71ac88fe9 x86, mce: broadcast mce depending on the cpu version
There is no reason why SRAO event received by the main thread
is the only one that being broadcasted.

According to the x86 ASDM vol.3A 15.10.4.1,
MCE signal is broadcast on processor version 06H_EH or later.

This change is required to handle SRAR in smp guests.

Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-10-21 13:11:38 -02:00
Hidetoshi Seto
f8502cfbbf x86, mce: ignore SRAO only when MCG_SER_P is available
And restruct this block to call kvm_mce_in_exception() only when it is
required.

Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-10-21 13:09:06 -02:00
Marcelo Tosatti
0f53994f7a Fix memory leak in register save load due to xsave support
From: Avi Kivity <avi@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-10-20 16:15:04 -05:00
Marcelo Tosatti
577804958a Add savevm/loadvm support for MCE
Port qemu-kvm's

commit 1bab5d11545d8de5facf46c28630085a2f9651ae
Author: Huang Ying <ying.huang@intel.com>
Date:   Wed Mar 3 16:52:46 2010 +0800

    Add savevm/loadvm support for MCE

    MCE registers are saved/load into/from CPUState in
    kvm_arch_save/load_regs. To simulate the MCG_STATUS clearing upon
    reset, MSR_MCG_STATUS is set to 0 for KVM_PUT_RESET_STATE.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-10-20 16:15:04 -05:00
Marcelo Tosatti
c0532a76b4 MCE: Relay UCR MCE to guest
Port qemu-kvm's

commit 4b62fff1101a7ad77553147717a8bd3bf79df7ef
Author: Huang Ying <ying.huang@intel.com>
Date:   Mon Sep 21 10:43:25 2009 +0800

    MCE: Relay UCR MCE to guest

    UCR (uncorrected recovery) MCE is supported in recent Intel CPUs,
    where some hardware error such as some memory error can be reported
    without PCC (processor context corrupted). To recover from such MCE,
    the corresponding memory will be unmapped, and all processes accessing
    the memory will be killed via SIGBUS.

    For KVM, if QEMU/KVM is killed, all guest processes will be killed
    too. So we relay SIGBUS from host OS to guest system via a UCR MCE
    injection. Then guest OS can isolate corresponding memory and kill
    necessary guest processes only. SIGBUS sent to main thread (not VCPU
    threads) will be broadcast to all VCPU threads as UCR MCE.

aliguori: fix build

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-10-20 16:15:04 -05:00
Marcelo Tosatti
e7701825e1 kvm: x86: add mce support
Port qemu-kvm's MCE support

commit c68b2374c9048812f488e00ffb95db66c0bc07a7
Author: Huang Ying <ying.huang@intel.com>
Date:   Mon Jul 20 10:00:53 2009 +0800

    Add MCE simulation support to qemu/kvm

    KVM ioctls are used to initialize MCE simulation and inject MCE. The
    real MCE simulation is implemented in Linux kernel. The Kernel part
    has been merged.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-10-20 16:15:04 -05:00
Joerg Roedel
296acb643b Add svm cpuid features
This patch adds the svm cpuid feature flags to the qemu
intialization path. It also adds the svm features available
on phenom to its cpu-definition and extends the host cpu
type to support all svm features KVM can provide.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-10-20 16:15:04 -05:00
Joerg Roedel
db0ad1ba04 Set cpuid definition to 0 before initializing it
This patch cleans the (stack-allocated) cpuid definition to
0 before actually initializing it.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-10-20 16:15:04 -05:00
Blue Swirl
4581cbcdc3 i386: avoid a write only variable
Compiling with GCC 4.6.0 20100925 produced warnings:
/src/qemu/target-i386/op_helper.c: In function 'switch_tss':
/src/qemu/target-i386/op_helper.c:283:53: error: variable 'new_trap' set but not used [-Werror=unused-but-set-variable]

Fix by adding a dummy cast so that the variable is not unused. Add also
pointer to docs.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13 18:43:19 +00:00
Gerd Hoffmann
3329f07b7a QemuOpts: make most qemu_*_opts static
Switch tree to lookup-by-name using qemu_find_opts().
Also hook up virtfs options so qemu_find_opts works for them too.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-08-22 17:11:06 -05:00
Adam Lackorzynski
583cd3cb93 target-i386: svm: Fix MSRPM check
Correct the calculation of the offset in the msrpm
for the MSR range 0 - 0x1fff.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-08-22 16:19:00 -05:00
Blue Swirl
66fe09eebb Use ARRAY_SIZE macro
Replace array size calculations with ARRAY_SIZE macro.

Implemented with this Coccinelle semantic patch, adapted from
Linux kernel:
@@
type T;
T[] E;
@@

- (sizeof(E)/sizeof(*E))
+ ARRAY_SIZE(E)

@@
type T;
T[] E;
@@

- (sizeof(E)/sizeof(E[...]))
+ ARRAY_SIZE(E)

@@
type T;
T[] E;
@@

- (sizeof(E)/sizeof(T))
+ ARRAY_SIZE(E)

Some files (*-dis.c, tests/*) had to be filtered out.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-20 21:03:24 +00:00
Jun Koi
728d803baa target-i386: use gen_update_cc_op()
This patch simplifies target-i386/translate.c a bit by replacing some
code with gen_update_cc_op()

Signed-off-by: Jun Koi <junkoi2004@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-25 17:04:07 +02:00
Jun Koi
5779406a24 use symbol for DisasContext->is_jmp
This patch replaces constant value assigned for (DisasContext
*)->is_jmp with DISAS_TB_JUMP.

Signed-off-by: Jun Koi <junkoi2004@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-07-24 14:34:15 +02:00
Paolo Bonzini
a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini
10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Paolo Bonzini
83dae09588 remove unused stuff from */exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 06:47:13 +00:00
Andi Kleen
8713f8ffb8 Don't declare XSAVE as supported
i386 cpuid.c currently claims XSAVE is supported in the CPUID filter,
but that's not true: Only FXSAVE is supported. Remove that bit
from the filter.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-02 01:55:38 +02:00
Andi Kleen
c045af25a5 Add more boundary checking to sse3/4 parsing
ssse3 uses tables with only two entries per op, but it is indexed
with b1 which can contain variables upto 3. This happens when ssse3
or sse4 are used with REP* prefixes.

Add boundary checking for this case.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-02 01:53:37 +02:00
Richard Henderson
7418027ea4 target-i386: fix xchg rax,r8
We were ignoring REX_B while special-casing NOP, i.e. xchg eax,eax.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:28 +02:00
Jan Kiszka
ab5ea55805 x86: svm: Always clear event_inj on vmexit
We currently only clear SVM_EVTINJ_VALID after successful interrupt
delivery. This apparently does not match real hardware which clears the
whole event_inj field on every vmexit, including unsuccessful interrupt
delivery.

Reported-by: Erik van der Kouwe <vdkouwe@cs.vu.nl>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-30 20:59:53 +02:00
Sheng Yang
408392b30d kvm: Fix cpu_is_bsp() compilation warning
Signed-off-by: Sheng Yang <sheng@linux.intel.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-06-28 13:06:03 -03:00
Marcelo Tosatti
ddced198cd kvm: init mp_state
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-06-28 13:06:03 -03:00
Sheng Yang
f1665b21f1 kvm: Enable XSAVE live migration support
Signed-off-by: Sheng Yang <sheng@linux.intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-06-28 13:06:03 -03:00
Sheng Yang
51e49430c0 Enable XSAVE related CPUID
We can support it in KVM now. The 0xd leaf is queried from KVM.

Signed-off-by: Sheng Yang <sheng@linux.intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-06-28 13:06:03 -03:00
Sheng Yang
c958a8bd9b kvm: Extend kvm_arch_get_supported_cpuid() to support index
Would use it later for XSAVE related CPUID.

Signed-off-by: Sheng Yang <sheng@linux.intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-06-28 13:06:03 -03:00
Andre Przywara
8935499831 fix CPUID vendor override
the meaning of vendor_override is actually the opposite of how it
is currently used :-(
Fix it to allow KVM to export the non-native CPUID vendor if
explicitly requested by the user.

The intended behavior is:
With TCG:
  - always inject the configured vendor (either hard-coded, in config
    files or via ",vendor=" commandline)
With KVM:
  - by default inject the host's vendor
  - if the user specifies ",vendor=" on the commandline, use this
    instead of the host's vendor
  - all pre-configured vendors (hard-coded, config file) are ignored

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-06-28 13:06:03 -03:00
Jan Kiszka
052be86bc3 x86: Fix INIT processing
This fixes a regression of 0e26b7b892: Reset halted also on INIT.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-27 19:07:45 +03:00
Blue Swirl
92a16d7a9a apic: qdev conversion cleanup
Make APICState completely private to apic.c by using DeviceState
in external APIs.

Move apic_init() to pc.c.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19 07:47:42 +00:00
Blue Swirl
0e26b7b892 apic: avoid using CPUState internals
Move the actual CPUState contents handling to cpu.h and cpuid.c.

Handle CPU reset and set env->halted in pc.c.

Add a function to get the local APIC state of the current
CPU for the MMIO.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19 10:42:34 +03:00
Blue Swirl
4a942ceac7 apic: avoid passing CPUState from CPU code
Pass only APICState when accessing APIC from CPU code.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19 10:42:31 +03:00
Richard Henderson
2bece2c883 tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments.  Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be
zero-extended to 64-bits.

To effect this, extend the "sizemask" parameter to tcg_gen_callN
to include the signedness of the type of each parameter.  If the
tcg target requires it, extend each 32-bit argument into a 64-bit
temp and pass that to the function call.

This ABI feature is required by sparc64, ppc64 and s390x.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-16 11:29:11 +02:00
Paolo Bonzini
8c0e6340fb target-i386: fix decoding of negative 4-byte displacements
Negative four byte displacements need to be sign-extended after
c086b783eb.  Do so.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Richard Henderson  <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-04 19:48:53 +00:00
Andre Przywara
eafaf1e5ab resent: x86/cpuid: Add kvm32 CPU model
Create a kvm32 CPU model that describes a least common denominator
for KVM capable guest CPUs. Useful for migration purposes.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-06-01 12:53:09 -05:00
Gleb Natapov
c1667e4097 kvm: fix 80000001.EDX supported bit filtering
On AMD some bits from 1.EDX are reported in 80000001.EDX. The mask used
to copy bits from 1.EDX to 80000001.EDX is incorrect resulting in
unsupported features passed into a guest.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-05-11 17:07:36 -03:00
Gleb Natapov
4513d9232b Do not stop VM if emulation failed in userspace.
Continue vcpu execution in case emulation failure happened while vcpu
was in userspace. In this case #UD will be injected into the guest
allowing guest OS to kill offending process and continue.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-05-11 14:03:44 -03:00
Marcelo Tosatti
0af691d779 kvm: enable smp > 1
Process INIT/SIPI requests and enable -smp > 1.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-05-11 14:02:22 -03:00
Jan Kiszka
dbaa07c404 kvm: validate context for kvm cpu get/put operations
Validate that KVM vcpu state is only read/written from cpu thread itself
or that cpu is stopped.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-05-11 14:02:22 -03:00
Richard Henderson
6e9cc3ed0e target-i386: Remove duplicate CPU log.
The proper logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Sheng Yang
204204308b kvm: allow qemu to set EPT identity mapping address
If we use larger BIOS image than current 256KB, we would need move reserved
TSS and EPT identity mapping pages. Currently TSS support this, but not
EPT.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-04-26 11:28:35 -03:00
Marcelo Tosatti
b5e5a93417 target-i386: print EFER in cpu_dump_state
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-04-26 11:28:35 -03:00
Jan Kiszka
ff44f1a373 KVM: x86: Add debug register saving and restoring
Make use of the new KVM_GET/SET_DEBUGREGS to save/restore the x86 debug
registers.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-04-26 11:28:35 -03:00
Blue Swirl
7f5b7d3e2c x86: remove dead assignments, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 18:58:25 +00:00
Blue Swirl
8c0d577eb5 kvm: avoid collision with dprintf macro in stdio.h, spotted by clang
Fixes clang errors:
  CC    i386-softmmu/kvm.o
/src/qemu/target-i386/kvm.c:40:9: error: 'dprintf' macro redefined
In file included from /src/qemu/target-i386/kvm.c:21:
In file included from /src/qemu/qemu-common.h:27:
In file included from /usr/include/stdio.h:910:
/usr/include/bits/stdio2.h:189:12: note: previous definition is here
  CC    i386-softmmu/kvm-all.o
/src/qemu/kvm-all.c:39:9: error: 'dprintf' macro redefined
In file included from /src/qemu/kvm-all.c:23:
In file included from /src/qemu/qemu-common.h:27:
In file included from /usr/include/stdio.h:910:
/usr/include/bits/stdio2.h:189:12: note: previous definition is here

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18 14:22:14 +00:00
Adam Lackorzynski
9bd5494e57 target-i386: Fix variable in (disabled) debugging code
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:44:40 +02:00
Stefan Weil
e5c15efff6 target-i386: Fix compiler warning
With argument checking for cpu_fprintf, gcc throws this warning:

  CC    i386-softmmu/helper.o
cc1: warnings being treated as errors
/qemu/ar7/target-i386/helper.c: In function ‘cpu_x86_dump_seg_cache’:
/qemu/ar7/target-i386/helper.c:220: error: format not a string literal and no format arguments

The code is correct, but current gcc versions don't detect this.
Therefore the patch rewrites the statement to satisfy the compiler.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:42:26 +02:00
Paolo Bonzini
1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00
Paul Brook
d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Aurelien Jarno
2f7a21c4a5 x86/cpuid: fix indentation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Aurelien Jarno
8560efed6a x86/cpuid: Enable all features of real CPU
Enable all features of real CPU, unsupported features will be
trimmed depending on TCG or KVM capabilities.

Move the list of unsupported TCG features near the TCG capabilities
masks.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
58012d66dc x86/cpuid: fix CPUID levels
Bump up the xlevel number for qemu32 to allow parsing of the processor
name string for this model.
Similiarly the 486 processor should have at least the feature bit
leaf enabled.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
d3bf59157c x86/cpuid: Always expose 32 and 64-bit CPUs
Since 64-bit capability is just another CPUID bit we now properly
mask, there is no reason anymore to hide the 64-bit capable CPU
models from a 32-bit only QEMU. All 64-bit CPUs can be used
perfectly in 32-bit legacy mode anyway, so these models also make
sense for 32-bit.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
551a2dec8f x86/cpuid: add TCG feature bit trimming
In KVM we trim the user provided CPUID bits to match the host CPU's
one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's
capabilities and apply it to the user bits.
This allows to let the CPU models reflect their native archetypes.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
457dfed614 x86/cpuid: remove unnecessary kvm_trim function
Correct me if I am wrong, but kvm_trim looks like a really bloated
implementation of a bitwise AND. So remove this function and replace
it with the real stuff(TM).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
ed2c54d4cc x86/cpuid: add "host" to the list of supported CPU models
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
e117f7725a x86/cpuid: add missing CPUID feature flag names
Some CPUID feature flags had no string value, so they could not be
switched on or off from the command line.
Add names for the missing ones mentioned in the current public CPUID
specification from both Intel and AMD. Those only mentioned in the
Linux kernel source I put as comments.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
bdde476a9c x86/cpuid: moved host_cpuid function and remove prototype
the host_cpuid function was located at the end of the file and had
a prototype before it's first use. Move it up and remove the
prototype.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
4d067ed7a7 x86/cpuid: fix missing feature set bits
This one was accidently removed with commit
bb0300dc57

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
42673936d1 x86/cpuid: replace magic number with named constant
CPUID leaf Fn8000_0001.EDX contains a copy of many Fn0000_0001.EDX bits.
Define a name for this mask to improve readability and avoid typos.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara
c6dc6f63bf x86/cpuid: move CPUID functions into separate file
about half of target-i386/helper.c consist of CPUID related functions.
Only one of them is a real TCG helper function. So move the whole
CPUID stuff out of this into a separate file to get better
maintainable parts.
This is only code reordering and should not affect QEMU's
functionality.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
TeLeMan
2e21e7491f target-i386: fix commit c22549204a
The commit c22549204a led movntps &
movntdq to be translated incorrectly.

Signed-off-by: TeLeMan <geleman@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:35:55 +01:00
Paul Brook
4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson
5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Aurelien Jarno
b16f827bdf target-i386: fix SIB decoding with index = 4
A SIB byte with an index of 4 means "no scaled index", even if the scale
value is not 0. In 64-bit mode, if REX.X is used, an index of 4 selects
%r12. This is correctly handled by the computation of the index variable,
which includes the index bits, and also the REX.X prefix:

    index = ((code >> 3) & 7) | REX_X(s);

Thanks to Avi Kivity, Jamie Lokier and Malc for the analysis of the
problem and the initial patch.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-10 08:43:43 +01:00
malc
41b1e61f51 target-i386: Fix long jumps/calls in long mode with REX.W set
Signed-off-by: malc <av1474@comtv.ru>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 19:20:04 +01:00
Aurelien Jarno
c22549204a target-i386: fix lddqu SSE instruction
This instruction load data from memory to register and not the reverse.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 18:33:53 +01:00
Jan Kiszka
ea64305139 KVM: x86: Restrict writeback of VCPU state
Do not write nmi_pending, sipi_vector, and mpstate unless we at least go
through a reset. And TSC as well as KVM wallclocks should only be
written on full sync, otherwise we risk to drop some time on state
read-modify-write.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:30 -03:00
Jan Kiszka
ea375f9ab8 KVM: Rework VCPU state writeback API
This grand cleanup drops all reset and vmsave/load related
synchronization points in favor of four(!) generic hooks:

- cpu_synchronize_all_states in qemu_savevm_state_complete
  (initial sync from kernel before vmsave)
- cpu_synchronize_all_post_init in qemu_loadvm_state
  (writeback after vmload)
- cpu_synchronize_all_post_init in main after machine init
- cpu_synchronize_all_post_reset in qemu_system_reset
  (writeback after system reset)

These writeback points + the existing one of VCPU exec after
cpu_synchronize_state map on three levels of writeback:

- KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run)
- KVM_PUT_RESET_STATE   (on synchronous system reset, all VCPUs stopped)
- KVM_PUT_FULL_STATE    (on init or vmload, all VCPUs stopped as well)

This level is passed to the arch-specific VCPU state writing function
that will decide which concrete substates need to be written. That way,
no writer of load, save or reset functions that interact with in-kernel
KVM states will ever have to worry about synchronization again. That
also means that a lot of reasons for races, segfaults and deadlocks are
eliminated.

cpu_synchronize_state remains untouched, just as Anthony suggested. We
continue to need it before reading or writing of VCPU states that are
also tracked by in-kernel KVM subsystems.

Consequently, this patch removes many cpu_synchronize_state calls that
are now redundant, just like remaining explicit register syncs.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:28 -03:00
Jan Kiszka
b0b1d69079 KVM: Rework of guest debug state writing
So far we synchronized any dirty VCPU state back into the kernel before
updating the guest debug state. This was a tribute to a deficite in x86
kernels before 2.6.33. But as this is an arch-dependent issue, it is
better handle in the x86 part of KVM and remove the writeback point for
generic code. This also avoids overwriting the flushed state later on if
user space decides to change some more registers before resuming the
guest.

We furthermore need to reinject guest exceptions via the appropriate
mechanism. That is KVM_SET_GUEST_DEBUG for older kernels and
KVM_SET_VCPU_EVENTS for recent ones. Using both mechanisms at the same
time will cause state corruptions.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:26 -03:00
Paul Brook
35bed8ee91 Move ioport.h out of cpu-all.h
Only include ioport.h where it is actually needed.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-01 03:29:21 +00:00
Jason Wessel
63a54736f3 target-i386: fix crash on x86 32bit linux host with hw breakpoint exceptions
If you make use of hw breakpoints on a 32bit x86 linux host, qemu
will segmentation fault when processing the exception.

The problem is that the value of env is stored in $ebp in the op_helper
raise_exception() function, and it can have the wrong value when
calling it from non generated code.

It is possible to work around the problem by restoring the value of
env before calling raise_exception() using a new helper function that
takes (CPUState *) as one of the arguments.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:20:02 +01:00
Blue Swirl
d354899c82 Fix OpenBSD linker warning
helper.o(.text+0x11e0): In function `listflags':
/src/qemu/target-i386/helper.c:661: warning: sprintf() is often misused, please use snprintf()

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-23 22:01:36 +00:00
Blue Swirl
161717d2cb Fix i386-bsd-user build
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-23 21:46:32 +00:00
Anthony Liguori
724c689357 Merge remote branch 'qemu-kvm/uq/master' into staging 2010-02-22 16:16:22 -06:00
john cooper
b5ec5ce0e3 Add cpu model configuration support..
This is a reimplementation of prior versions which adds
the ability to define cpu models for contemporary processors.
The added models are likewise selected via -cpu <name>,
and are intended to displace the existing convention
of "-cpu qemu64" augmented with a series of feature flags.

A primary motivation was determination of a least common
denominator within a given processor class to simplify guest
migration.  It is still possible to modify an arbitrary model
via additional feature flags however the goal here was to
make doing so unnecessary in typical usage.  The other
consideration was providing models names reflective of
current processors.  Both AMD and Intel have reviewed the
models in terms of balancing generality of migration vs.
excessive feature downgrade relative to released silicon.

This version of the patch replaces the prior hard wired
definitions with a configuration file approach for new
models.  Existing models are thus far left as-is but may
easily be transitioned to (or may be overridden by) the
configuration file representation.

Proposed new model definitions are provided here for current
AMD and Intel processors.  Each model consists of a name
used to select it on the command line (-cpu <name>), and a
model_id which corresponds to a least common denominator
commercial instance of the processor class.

A table of names/model_ids may be queried via "-cpu ?model":

        :
    x86       Opteron_G3  AMD Opteron 23xx (Gen 3 Class Opteron)
    x86       Opteron_G2  AMD Opteron 22xx (Gen 2 Class Opteron)
    x86       Opteron_G1  AMD Opteron 240 (Gen 1 Class Opteron)
    x86          Nehalem  Intel Core i7 9xx (Nehalem Class Core i7)
    x86           Penryn  Intel Core 2 Duo P9xxx (Penryn Class Core 2)
    x86           Conroe  Intel Celeron_4x0 (Conroe/Merom Class Core 2)
        :

Also added is "-cpu ?dump" which exhaustively outputs all config
data for all defined models, and "-cpu ?cpuid" which enumerates
all qemu recognized CPUID feature flags.

The pseudo cpuid flag 'check' when added to the feature flag list
will warn when feature flags (either implicit in a cpu model or
explicit on the command line) would have otherwise been quietly
unavailable to a guest:

    # qemu-system-x86_64 ... -cpu Nehalem,check
    warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000]
    warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000]

A similar 'enforce' pseudo flag exists which in addition
to the above causes qemu to error exit if requested flags are
unavailable.

Configuration data for a cpu model resides in the target config
file which by default will be installed as:

    /usr/local/etc/qemu/target-<arch>.conf

The format of this file should be self explanatory given the
definitions for the above six models and essentially mimics
the structure of the static x86_def_t x86_defs.

Encoding of cpuid flags names now allows aliases for both the
configuration file and the command line which reconciles some
Intel/AMD/Linux/Qemu naming differences.

This patch was tested relative to qemu.git.

Signed-off-by: john cooper <john.cooper@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-02-22 16:16:17 -06:00
Jes Sorensen
62f734a0d5 kvm: Kill CR3_CACHE feature references
Remove all references to KVM_CR3_CACHE as it was never implemented.

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-02-21 11:41:07 +02:00
Jes Sorensen
4c5b10b7b6 QEMU e820 reservation patch
Hi,

Kevin and I have agreed on the approach for this one now. So here is
the latest version of the patch for QEMU, submitting e820 reservation
entries via fw_cfg.

Cheers,
Jes

Use qemu-cfg to provide the BIOS with an optional table of e820 entries.

Notify the BIOS of the location of the TSS+EPT range to by reserving
it via the e820 table.

This matches a corresponding patch for Seabios, however older versions
of Seabios will default to the hardcoded address range and stay
compatible with current QEMU.

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-02-19 15:53:54 -06:00
Anthony Liguori
8217d94586 Merge remote branch 'qemu-kvm/uq/master' into staging-tmp 2010-02-08 10:06:54 -06:00
Paolo Bonzini
5e398dd2f0 remove two dead assignments in target-i386/translate.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-05 18:13:14 +00:00
Jan Kiszka
19ccb8ea17 KVM: x86: Fix up misreported CPU features
From qemu-kvm: Kernels before 2.6.30 misreported some essential CPU
features via KVM_GET_SUPPORTED_CPUID. Fix them up.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2010-02-03 19:47:34 -02:00
Jan Kiszka
aee028b95d KVM: Request setting of nmi_pending and sipi_vector
The final version of VCPU events in 2.6.33 will allow to skip
nmi_pending and sipi_vector on KVM_SET_VCPU_EVENTS. For now let's write
them unconditionally, which is unproblematic for upstream due to missing
SMP support. Future version which enable SMP will write them only on
reset.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-02-03 19:47:33 -02:00
Paolo Bonzini
49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Paolo Bonzini
baee019f64 remove dead code from target-i386/exec.h
These are unused since edea5f0 (no need to define global registers in
cpu-exec.c, 2008-05-10).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Gleb Natapov
bb0300dc57 Add KVM paravirt cpuid leaf
Initialize KVM paravirt cpuid leaf and allow user to control guest
visible PV features through -cpu flag.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-13 17:14:16 -06:00
Amit Shah
d7209371b1 x86: translate.c: remove dead assignment
clang-analyzer points out a redundant assignment.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-13 17:14:15 -06:00
Gleb Natapov
e73223a584 remove pending exception on vcpu reset.
Without this qemu can even start on kvm modules with events support
since default value of exception_injected in zero and this is #DE
exception.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-11 09:56:30 -06:00
Huang Ying
af364b418c MCE: Fix bug of IA32_MCG_STATUS after system reset
Now, if we inject a fatal MCE into guest OS, for example Linux, Linux
will go panic and then reboot. But if we inject another MCE now,
system will reset directly instead of go panic firstly, because
MCG_STATUS.MCIP is set to 1 and not cleared after reboot. This is does
not follow the behavior in real hardware.

This patch fixes this via set env->mcg_status to 0 during system reset.

Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-11 09:56:30 -06:00
Aurelien Jarno
995963852c target-i386: Fix "call im" on x86_64 when executing 32-bit code
Similarly to what is done in 32938e127f
for "jmp im", trunc the immediate to 32-bit when not running in 64-bit
mode.

Reported-by: Kevin O'Connor <kevin@koconnor.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-03 03:14:41 +01:00
Gleb Natapov
c84bd4f104 Intel CPUs starting from pentium have apic
Intel CPUs starting from pentium have apic. Lets advertise it.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-24 19:39:53 +01:00
Anthony Liguori
acb6685fea Revert "kvm: x86: Save/restore exception_index"
This reverts commit ebbc8a3d8e.

As suggested by Jan Kiszka,

  "It was obsoleted by d1793b836f8f123b961c613de1bb1c0c185c84cc and now
   saves/restores a useless field."

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18 11:26:33 -06:00
Jan Kiszka
d46272c774 target-i386: Fix evaluation of DR7 register
hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplier
to extract type and len.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18 11:26:25 -06:00
Jan Kiszka
31827373f0 kvm: x86: Use separate exception_injected CPUState field
Marcelo correctly remarked that there are usage conflicts between QEMU
core code and KVM /wrt exception_index. So spend a separate field and
also save/restore it properly.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18 11:26:25 -06:00
Andre Przywara
f1e00a9cf3 target-i386: Update CPUID feature set for TCG
The CPUID features QEMU presented to the guest were not up-to-date
with QEMU's emulated feature set.
Add the missing bits of recent (and not so recent) additions to
QEMU's emulation engine.
For stability reasons only the user mode usable bits are exposed for
now, features like Monitor or CR8LEG are left out.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:48:20 +01:00
Glauber Costa
1a03675db1 v2: properly save kvm system time msr registers
Currently, the msrs involved in setting up pvclock are not saved over
migration and/or save/restore. This patch puts their value in special
fields in our CPUState, and deal with them using vmstate.

kvm also has to account for it, by including them in the msr list
for the ioctls.

This is a backport from qemu-kvm.git

[v2: sucessfully build without kerneldir ]

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-12 07:59:49 -06:00
Jan Kiszka
4d6e3ac5d4 kvm: x86: Save/restore exception_index
As KVM now makes use of exception_index to keep pending exceptions, we
have to save&restore this field as well.

NOTE: We have to nail the arch-independent exception_index down to a
certain bit width for proper vmstate processing, namely to 32 bit.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-12 07:59:39 -06:00
Andre Przywara
6d9fef1a02 cpuid: Fix multicore setup on Intel
The multicore CPUID code detects whether the guest is an Intel or an
AMD CPU, because the Linux kernel is picky about the CmpLegacy bit.
KVM by default passes through the host's vendor, which was not
catched by the code. So fork out the vendor determining bits into a
separate function to be used from both places and always get the real
vendor.
This fixes KVM's multicore setup on Intel CPUs.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Reported-by: Dietmar Maurer <dietmar@proxmox.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-07 11:13:42 -06:00
Jan Kiszka
6fb6d24554 kvm: x86: Fix initial kvm_has_msr_star
KVM_GET_MSR_INDEX_LIST returns -E2BIG when the provided space is too
small for all MSRs. But this is precisely the error we trigger with the
initial request in order to obtain that size. Do not fail in that case.

This caused a subtle corruption of the guest state as MSR_STAR was not
properly saved/restored. The corruption became visible with latest kvm
optimizing the MSR updates.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-07 08:45:47 -06:00
Jan Kiszka
a0fb002c64 kvm: x86: Add support for VCPU event states
This patch extends the qemu-kvm state sync logic with support for
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception,
interrupt and NMI states.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-03 15:25:57 -06:00
Jan Kiszka
5a2e3c2e11 kvm: x86: Fix merge artifact of f8d926e9 about mp_state
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-03 15:25:56 -06:00
Jan Kiszka
0e607a80d3 kvm: x86: Refactor use of interrupt_bitmap
Drop interrupt_bitmap from the cpustate and solely rely on the integer
interupt_injected. This prepares us for the new injected-interrupt
interface, which will deprecate the bitmap, while preserving
compatibility.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-17 08:49:37 -06:00
Jan Kiszka
caa5af0ff3 kvm: Add arch reset handler
Will be required by succeeding changes.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-17 08:49:37 -06:00
Hollis Blanchard
9bdbe550f0 kvm: Move KVM mp_state accessors to i386-specific code
Unbreaks PowerPC and S390 KVM builds.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-12 11:23:55 -06:00
Blue Swirl
b55a37c981 user: move CPU reset call to main.c for x86/PPC/Sparc
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 10:37:06 +00:00
Glauber Costa
c169998802 v3: don't call reset functions on cpu initialization
There is absolutely no need to call reset functions when initializing
devices. Since we are already registering them, calling qemu_system_reset()
should suffice. Actually, it is what happens when we reboot the machine,
and using the same process instead of a special case semantics will even
allow us to find bugs easier.

Furthermore, the fact that we initialize things like the cpu quite early,
leads to the need to introduce synchronization stuff like qemu_system_cond.
This patch removes it entirely. All we need to do is call qemu_system_reset()
only when we're already sure the system is up and running

I tested it with qemu (with and without io-thread) and qemu-kvm, and it
seems to be doing okay - although qemu-kvm uses a slightly different patch.

[ v2: user mode still needs cpu_reset, so put it in ifdef. ]
[ v3: leave qemu_system_cond for now. ]

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 08:06:58 +00:00
Juan Quintela
d4829d4992 vmstate: Add version arg to VMSTATE_SINGLE_TEST()
This allows to define VMSTATE_SINGLE with VMSTATE_SINGLE_TEST
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-27 12:28:51 -05:00
Andre Przywara
31501a714b target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:10:36 +02:00
Blue Swirl
976b2037e5 x86: add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18 14:51:10 +00:00
Laurent Desnogues
49d9fdcca6 target-i386: fix ARPL
The arpl implementation in target-i386/translate.c uses cpu_A0
temporary across a brcond op.  This patch fixes that issue.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-06 22:01:00 +02:00
Aurelien Jarno
5a2d0e57ad target-i386: move recently added vmstate fields at the end of the structure
This reduce the impact on hosts that have addressing modes with limited
offsets. Suggested by Laurent Desnogues.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-05 22:41:04 +02:00
Juan Quintela
1e7fbc6d3c x86: fix miss merge
There was a missmerge, and then we got a tail recursive call to cpu_post_load
without case base :)

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 14:01:16 -05:00
Jan Kiszka
5f30fa18ad gdbstub: x86: Switch 64/32 bit registers dynamically
Commit 56aebc8916 changed gdbstub in way
that debugging 32 or 16-bit guest code is no longer possible with qemu
for x86_64 guest CPUs. Since that commit, qemu only provides registers
sets for 64-bit, forcing current and foreseeable gdb to also switch its
architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit.

No question, this is a gdb issue. But, as it was confirmed in several
discusssions with gdb people, it is a non-trivial thing to fix. So until
qemu finds a gdb version attach with a rework x86 support, we have to
work around it by switching the register layout as the guest switches
its execution mode between 16/32 and 64 bit.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:45 -05:00
Juan Quintela
0cb892aa26 x86: port cpu to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:43 -05:00
Juan Quintela
3c8ce630c5 x86: factor out cpu_get/put_fpreg()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:43 -05:00
Juan Quintela
216c07c3a8 x86: factor out cpu_get/put_mttr_var()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
fc3b0aa23e x86: factor out cpu_get/put_xmm_reg()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
468f65814e x86: factor out cpu_pre/post_load()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
c4c38c8c72 x86: factor out cpu_pre_save()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
66e6d55b75 x86: port segments to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
c1a54d573b x86: split MTRRVar union
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
acc6883679 x86: split FPReg union
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
e5cc6429de x86: mcg_cap is never 0
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela
496eb021d8 x86: send mce_banks as an array
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela
ac74d0f1fc x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change

CC: Huang Ying <ying.huang@intel.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela
60a902f1c3 x86: add fpregs_format_vmstate
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela
bfc179b60c x86: add pending_irq_vmstate to the state
It is needed to save the interrupt_bitmap

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela
cdc0c58fa9 x86: add fptag_vmstate to the state
It is needed to store fptags

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela
67b8f41957 x86: fpus is uint16_t not unsigned int
We save more that fpus on that 16 bits (fpstt), we need an additional field

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela
eb83162311 x86: fpuc is uint16_t not unsigned int
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela
5ee0ffaa42 x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactly
what we need (namely, sign extend to 64 bits when used with 64bit addresess.

Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax.

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:39 -05:00
Juan Quintela
1f76b9b9b3 x86: hflags is not modified at all, just save it directly
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:39 -05:00
Kevin Wolf
09d85fb843 target-i386: Fix exceptions for fxsave/fxrstor
This patch corrects the following aspects of exception generation in
fxsave/fxrstor:

* Generate #GP if the operand is not aligned to a 16 byte boundary
* Generate #UD if the LOCK prefix is used
* For CR0.EM = 1 #NM is generated, not #UD

Signed-off-by: Kevin Wolf <mail@kevin-wolf.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 23:10:22 +02:00
Andre Przywara
1b050077d2 target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:46:34 +02:00
Andre Przywara
d9f4bb27db target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:09:41 +02:00
Andre Przywara
ccd59d09a9 target-i386: add lock mov cr0 = cr8
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode.
If you use the LOCK prefix with "mov CR0", it accesses CR8 instead.
This behavior is guarded by the CR8_LEGACY CPUID bit
(Fn8000_0001:ECX[1]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:04:40 +02:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Laurent Desnogues
cc739bb0c4 x86: use globals for CPU registers
Use globals for the 8 or 16 CPU registers on i386 and x86_64.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 22:53:05 +02:00
Aurelien Jarno
bedda79c1e target-i386: kill a tmp register
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 00:57:41 +02:00
Aurelien Jarno
5b207c007c target-i386: use subfi instead of sub with a non-freed constant
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 00:57:28 +02:00
Juan Quintela
3897293825 gcc wants 1st static and then const
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-25 19:52:06 +00:00
Blue Swirl
afcea8cbde ioports: remove unused env parameter and compile only once
The CPU state parameter is not used, remove it and adjust callers. Now we
can compile ioport.c once for all targets.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-20 16:05:47 +00:00
Jan Kiszka
2305411129 i386: Drop redundant kvm_enabled test
cpu_synchronize_state already does this.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 15:52:13 +00:00
Blue Swirl
aba1d00a41 Work around OpenSolaris sys/regset.h namespace pollution
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 12:36:11 +00:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Gleb Natapov
2637c754cc kvm_arch_get_registers() shouldn't be called directly
Direct call to kvm_arch_get_registers() bypass logic in
cpu_synchronize_state()

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-09-11 11:10:09 -05:00
Blue Swirl
1e6eec8b33 Fix Sparse warnings: add "static"
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-05 10:14:07 +00:00
Avi Kivity
4c0960c0c4 kvm: Simplify cpu_synchronize_state()
cpu_synchronize_state() is a little unreadable since the 'modified'
argument isn't self-explanatory.  Simplify it by making it always
synchronize the kernel state into qemu, and automatically flush the
registers back to the kernel if they've been synchronized on this
exit.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 20:35:30 -05:00
Andre Przywara
d1cd4bf419 introduce kvm64 CPU
In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type,
which is the least common denominator of all KVM-capable x86-CPUs
(based on Intel Pentium 4 Prescott). It can be used as a base type
for migration.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Andre Przywara
a8a358bf35 allow overriding of CPUID level on command line
The CPUID level determines how many CPUID leafs are exposed to the guest.
Some features (like multi-core) cannot be propagated without the proper
level, but guests maybe confused by bogus entries in some leafs.
So add level= and xlevel= to the list of -cpu options to allow the user to
override the default settings. While at it, merge unnecessary local
variables into one and allow hexadecimal arguments.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Andre Przywara
400281af34 set CPUID bits to present cores and threads topology
Controlled by the enhanced -smp option set the CPUID bits to present the
guest the desired topology. This is vendor specific, but (with the exception
of the CMP_LEGACY bit) not conflicting, so we set all bits everytime.
There is no real multithreading support for AMD CPUs, so report cores
instead.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Andre Przywara
ac72472b5f push CPUID level to 4 to allow Intel multicore decoding
Intel CPUs store the number of cores in CPUID leaf 4. So push
the maxleaf value to 4 to allow the guests access to this leaf.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-27 19:33:15 -05:00
Nathan Froyd
0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Anthony Liguori
4a1418e07b Unbreak large mem support by removing kqemu
kqemu introduces a number of restrictions on the i386 target.  The worst is that
it prevents large memory from working in the default build.

Furthermore, kqemu is fundamentally flawed in a number of ways.  It relies on
the TSC as a time source which will not be reliable on a multiple processor
system in userspace.  Since most modern processors are multicore, this severely
limits the utility of kqemu.

kvm is a viable alternative for people looking to accelerate qemu and has the
benefit of being supported by the upstream Linux kernel.  If someone can
implement work arounds to remove the restrictions introduced by kqemu, I'm
happy to avoid and/or revert this patch.

N.B. kqemu will still function in the 0.11 series but this patch removes it from
the 0.12 series.

Paul, please Ack or Nack this patch.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:02:55 -05:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Anthony Liguori
5e65000260 Only allow -cpu host when KVM is enabled
-cpu host is not at all useful when using tcg.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16 22:20:22 -05:00
Anthony Liguori
e6f9e6b496 Initialize cpuid variables
This causes a build break when !KVM.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16 22:04:02 -05:00
Andre Przywara
09ac35ac31 omit 3DNOW! CPUID bits from qemu64 CPU model
Since we recently do not disable 3DNOW! support anymore, we should
avoid setting the bits in the default qemu64 CPU model to ease
migration. TCG does not support it anyway and even AMD deprecates
it's usage nowadays.
If you want to use it in KVM, use the phenom, athlon or host CPU
model.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16 17:28:49 -05:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Jan Kiszka
84273177f2 gdbstub: x86: Support for setting segment registers
This allows to set segment registers via gdb also in system emulation
mode. Basic sanity checks are applied and nothing is changed if they
fail. But screwing up the target via this interface will never be
complicated, so I avoided being too paranoid here.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16 08:28:13 -05:00
Jan Kiszka
d9db889faf kvm: Work around borken MSR_GET_INDEX_LIST
Allocate enough memory for KVM_GET_MSR_INDEX_LIST as older kernels shot
far beyond their limits, corrupting user space memory.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-10 13:44:30 -05:00
Anthony Liguori
e6a0575e98 Make sure to mark MCE defines as ULL
Fixes build on 32-bit

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-10 13:41:20 -05:00
Huang Ying
79c4f6b080 QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.
- A monitor command "mce" is added to inject a MCE.
- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.

aliguori: fix build for linux-user

Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-09 16:04:53 -05:00
Jan Kiszka
6ad8702a77 Use ctz64 in favor of ffsll
Not all host platforms support ffsll.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2009-07-02 17:07:08 +00:00
Blue Swirl
97b35e359c Suppress a GCC warning
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-01 19:30:50 +00:00
Jan Kiszka
059b8b1eb6 KVM: x86: Refactor persistent CPU state
This patch aligns the KVM-related layout and encoding of the CPU state
to be saved to disk or migrated with qemu-kvm. The major differences are
reordering of fields and a compressed interrupt_bitmap into a single
number as there can be no more than one pending IRQ at a time.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 14:18:08 -05:00
Andre Przywara
6c0d7ee895 preserve the hypervisor bit while KVM trims the CPUID bits
The KVM kernel will disable all bits in CPUID which are not present in
the host. As this is mostly true for the hypervisor bit (1.ecx),
preserve its value before the trim and restore it afterwards.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 13:52:12 -05:00
Andre Przywara
671e467607 remove CPUID host hacks
KVM provides an in-kernel feature to disable CPUID bits that are not
present in the current host. So there is no need here to duplicate this
work. Additionally allows 3DNow! on capable processors, since the
restriction seems to apply to QEMU/TCG only.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 13:52:11 -05:00
Andre Przywara
6c1f42fe83 fix KVMs GET_SUPPORTED_CPUID feature usage
If we want to trim the user provided CPUID bits for KVM to be not greater
than that of the host, we should not remove the bits _after_ we sent
them to the kernel.
This fixes the masking of features that are not present on the host by
moving the trim function and it's call from helper.c to kvm.c.
It helps to use -cpu host.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 13:52:11 -05:00
Andre Przywara
f441bee871 CPUID Fn8000_0001.EAX is family/model/stepping, not features
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 13:52:11 -05:00
Andre Przywara
fe4bce09b6 introduce -cpu host target
Although the guest's CPUID bits can be controlled in a fine grained way
in QEMU, a simple way to inject the host CPU is missing. This is handy
for KVM desktop virtualization, where one wants the guest to support the
full host feature set.
Introduce another CPU type called 'host', which will propagate the host's
CPUID bits to the guest. Unwanted bits can still be turned off by using
the existing syntax (-cpu host,-skinit)

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 13:52:11 -05:00
Andre Przywara
6d2edc4373 allow hypervisor CPUID bit to be overriden
KVM defaults to the hypervisor CPUID bit to be set, whereas pure
QEMU clears it. On some occasions one wants to set or clear it the
other way round (for instance to get HyperV running inside a guest).

Move the bit-set to be done before the command line parsing and
enable it by default. One can disable it by using: -cpu qemu64,-hypervisor
Fix some whitespace damage on the way.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-29 13:52:11 -05:00
Gleb Natapov
b09ea7d55c Handle init/sipi in a main cpu exec loop. (v2)
This should fix compilation problem in case of CONFIG_USER_ONLY.

Currently INIT/SIPI is handled in the context of CPU that sends IPI.
This patch changes this to handle them like all other events in a main
cpu exec loop. When KVM will gain thread per vcpu capability it will
be much more clear to handle those event by cpu thread itself and not
modify one cpu's state from the context of the other.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-22 10:15:28 -05:00
Nitin A Kamble
538f368612 QEMU KVM: i386: Fix the cpu reset state
As per the IA32 processor manual, the accessed bit is set to 1 in the
processor state after reset. qemu pc cpu_reset code was missing this
accessed bit setting.

Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-16 15:36:47 -05:00
Andre Przywara
ef7681389f allow CPUID vendor override
KVM-enabled QEMU will always report the vendor ID of the physical CPU it is
running on. Allow to override this if explicitly requested on the
command line. It will not suffice to name a CPU type (like -cpu phenom),
but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-16 15:36:47 -05:00
Jan Kiszka
a23978077b x86: Add support for resume flag
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2009-05-22 10:50:37 -05:00
Jan Kiszka
f8d926e9cd kvm: x86: Save/restore KVM-specific CPU states
Save and restore all so far neglected KVM-specific CPU states. Handling
the TSC stabilizes migration in KVM mode. The interrupt_bitmap and
mp_state are currently unused, but will become relevant for in-kernel
irqchip support. By including proper saving/restoring already, we avoid
having to increment CPU_SAVE_VERSION later on once again.

v2:
 - initialize mp_state runnable (for the boot CPU)

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-22 10:50:34 -05:00
Jan Kiszka
b0a46a333a kvm: Add missing bits to support live migration
This patch adds the missing hooks to allow live migration in KVM mode.
It adds proper synchronization before/after saving/restoring the VCPU
states (note: PPC is untested), hooks into
cpu_physical_memory_set_dirty_tracking() to enable dirty memory logging
at KVM level, and synchronizes that drity log into QEMU's view before
running ram_live_save().

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-22 10:50:33 -05:00
Anthony Liguori
f80f9ec9a6 Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-21 08:47:55 -05:00
Mark McLoughlin
76ae317f7c kvm: work around supported cpuid ioctl() brokenness
KVM_GET_SUPPORTED_CPUID has been known to fail to return -E2BIG
when it runs out of entries. Detect this by always trying again
with a bigger table if the ioctl() fills the table.

Signed-off-by: Mark McLoughlin <markmc@redhat.com>
2009-05-20 09:12:57 -05:00
Paul Brook
5561650587 Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13 20:54:26 +01:00
Blue Swirl
001faf3269 Replace gcc variadic macro extension with C99 version
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13 17:53:17 +00:00
Anthony Liguori
989cebff75 Remove noisy printf when KVM masks CPU features
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-08 15:51:28 -05:00
Avi Kivity
e8a6aec9b5 kvm: Trim cpu features not supported by kvm
Remove cpu features that are not supported by kvm from the cpuid features
reported to the guest.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-08 15:42:52 -05:00
Avi Kivity
02b049df49 Fix x86 feature modifications for features that set multiple bits
QEMU allows adding or removing cpu features by using the syntax '-cpu +feature'
or '-cpu -feature'.  Some cpuid features cause more than one bit to be set or
cleared; but QEMU stops after just one bit has been modified, causing the
feature bits to be inconsistent.

Fix by allowing all feature bits corresponding to a given name to be set.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-08 15:42:52 -05:00
Avi Kivity
c6fa82c4e9 Make x86 cpuid feature names available in file scope
To be used later.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-08 15:42:52 -05:00
Avi Kivity
b827df585b kvm: Add support for querying supported cpu features
kvm does not support all cpu features; add support for dunamically querying
the supported feature set.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-08 15:42:52 -05:00
aliguori
0bf46a40a1 qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:41 +00:00
aliguori
6a4955a813 qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:20 +00:00
aliguori
00ea18d19e Fix i386-linux-user build (Laurent Desnogues)
This broke due to r7230.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7233 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-23 13:16:56 +00:00
aliguori
2ed51f5bfd put valid data into exit_int_info if needed (Gleb Natapov)
If fault happened during event delivery exit_int_info should contain
valid info about the event on vm exit.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7230 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-22 20:20:07 +00:00
aliguori
e37630ca4f xen: groundwork for xen support (Gerd Hoffmann)
- configure script and build system changes.
- wind up new machine type.
- add -xen-* command line options.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7219 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-22 15:19:10 +00:00
blueswir1
640f42e4e9 kqemu: merge CONFIG_KQEMU and USE_KQEMU
Basically a recursive ":%s/USE_KQEMU/CONFIG_KQEMU/g".

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7189 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-19 10:18:01 +00:00
aliguori
a3867ed24c x86: Enhanced dump of segment registers (Jan Kiszka)
Parse the descriptor flags that segment registers refer to and show the
result in a more human-friendly format. The output of info registers eg.
then looks like this:

[...]
ES =007b 00000000 ffffffff 00cff300 DPL=3 DS   [-WA]
CS =0060 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0068 00000000 ffffffff 00c09300 DPL=0 DS   [-WA]
DS =007b 00000000 ffffffff 00cff300 DPL=3 DS   [-WA]
FS =0000 00000000 00000000 00000000
GS =0033 b7dd66c0 ffffffff b7dff3dd DPL=3 DS   [-WA]
LDT=0000 00000000 00000000 00008200 DPL=0 LDT
TR =0080 c06da700 0000206b 00008900 DPL=0 TSS32-avl
[...]

Changes in this version:
 - refactoring so that only a single helper is used for dumping the
   segment descriptor cache
 - tiny typo fixed that broke 64-bit segment type names

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7179 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-18 15:36:11 +00:00
aliguori
a33609cae0 kvm: Fix cpuid initialization (Jan Kiszka)
Fix (more or less) spurious guest boot failures due to corrupted cpuid
states. The reason was insufficient initialization of cpuid entries
before passing them to the kernel.

At this chance also fix improper entry pointer progression and simplify
the code a bit.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7167 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17 20:50:54 +00:00
aurel32
1b530a6dfc Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05 20:08:59 +00:00
malc
8cd6345d00 Immediate versions of ro[lr]
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6968 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-02 22:54:35 +00:00
aliguori
64bf3f4eec kvm: Drop kvm_patch_opcode_byte (Jan Kiszka)
As cpu_memory_rw_debug is now capable of modifying ROM, we can drop our
own patch function.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6906 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-28 17:51:40 +00:00
aliguori
dc1ded53b8 x86: Add NULL check to lsl (Jan Kiszka)
According to the Intel specs, lsl performs a check against NULL for the
provided selector, just like lar does. helper_lar() includes the
corresponding code, helper_lsl() was lacking it so far.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6863 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-20 16:13:41 +00:00
aurel32
8777643e48 target-i386: use the new bswap* TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6836 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:35:41 +00:00
aurel32
66896cb803 tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:34:48 +00:00
aliguori
e22a25c936 Guest debugging support for KVM (Jan Kiszka)
This is a backport of the guest debugging support for the KVM
accelerator that is now part of the KVM tree. It implements the reworked
KVM kernel API for guest debugging (KVM_CAP_SET_GUEST_DEBUG) which is
not yet part of any mainline kernel but will probably be 2.6.30 stuff.
So far supported is x86, but PPC is expected to catch up soon.

Core features are:
 - unlimited soft-breakpoints via code patching
 - hardware-assisted x86 breakpoints and watchpoints

Changes in this version:
 - use generic hook cpu_synchronize_state to transfer registers between
   user space and kvm
 - push kvm_sw_breakpoints into KVMState

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6825 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-12 20:12:48 +00:00
pbrook
c276471991 The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications.  Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.


Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:24:59 +00:00
aliguori
b36d24b6c3 Fix cpuid KVM crash on i386 (Lubomir Rintel)
Cpuid should return into vec, not overwrite past address in count.
Changeset 6565 broke this.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6689 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-05 19:01:28 +00:00
balrog
ff3c01ca0a Fix "info registers" under kvm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6684 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-04 21:00:07 +00:00
aliguori
680c30692d x86: use qemu_log_mask on triple faults (Chris Wright)
replace open coded qemu_log_mask with proper macro

Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6649 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-27 20:05:13 +00:00
aliguori
b136a4c6ef KVM: cpuid function 2: store all values (Amit Shah)
Incrementing the array index was missed in the previous series which causes
us to not store all the values.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6617 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-11 21:00:43 +00:00
aliguori
a36b1029e2 KVM: Get all cpuid values from function 2 (Amit Shah)
cpuid function 2 can have multiple values to describe cache behaviour.
Loop till we have fetched all the values.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6567 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 15:50:36 +00:00
aliguori
486bd5a2f2 KVM: Fetch sub-leaf cpuid values for functions 4, 0xb, 0xd. (Amit Shah)
CPUID functions 4, 0xb and 0xd have sub-leaf values which depend on the
input value of ECX. Store these values as well.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6566 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 15:50:31 +00:00
aliguori
e00b6f8099 KVM: CPUID takes ecx as input value for some functions (Amit Shah)
The CPUID instruction takes the value of ECX as an input parameter
in addition to the value of EAX as the count for functions 4, 0xb
and 0xd. Make sure we pass the value to the instruction.

Also convert to the qemu-style whitespace for the surrounding code.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6565 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 15:50:08 +00:00
aliguori
0d0266a53b targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:06:11 +00:00
aliguori
9bdba1b67b Add phenom CPU descriptor (Alexander Graf)
As part of my ongoing effort to make nested SVM useful, I started working to get
VMware ESX run inside KVM.

VMware couples itself pretty tightly to the CPUID, so it's a good idea to emulate
a machine that officially supports SVM and should thus exploit the powers of
nested virtualization.

This patch adds a Phenom CPU identifier, that resembles a real-world phenom
CPU as closely as possible.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6501 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-02 17:10:57 +00:00
aliguori
eef26553c7 Implement FFXSR (Alexander Graf)
Newer AMD CPUs have the FFXSR capability. This leaves out XMM
register in FXSAVE/FXRESTORE when in CPL=0 and 64-bit mode.

This is required for Hyper-V.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6500 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-02 17:10:52 +00:00
malc
a5e50b263a Replace noreturn with QEMU_NORETURN
Thanks to Robert Riebisch for analysis [1]

[1] http://marc.info/?l=qemu-devel&m=123352293319271&w=2

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6492 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-01 22:19:27 +00:00
aliguori
33049de782 Fix a typo in ext2_feature_name (Carl-Daniel Hailfinger)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6474 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-29 19:45:28 +00:00
aliguori
6e48a40da5 Use new logging API in reset handling (Jan Kiszka)
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6473 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-29 17:02:21 +00:00
aliguori
dd5e3b1771 MTRR support on x86, part 2 (Carl-Daniel Hailfinger)
Load and save MTRR state together with machine state.

Add support for the MTRRcap MSR which is used by the latest Bochs BIOS
and some operating systems.

Fix a typo in ext2_feature_name.

With this patch, MTRR emulation should be good enough to not trigger any
sanity checks in well behaved BIOS/kernel code.
Some corner cases for BIOS/firmware usage remain to be implemented, but
that can be deferred to another patch.
Also, MTRR accesses on hardware not supporting MTRRs should cause #GP.
That can be enforced by another patch as well.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6472 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-29 17:02:17 +00:00
aliguori
8c6c919e28 kvm-x86: Remove eflags conversion into emulator format (Jan Kiszka)
It seems that the conversion of the kernel-delivered eflags state into
qemu's internal split representation was once needed in an older kvm
design (register read-back may have taken place from inside cpu_exec).
Today it is plain wrong and causes incorrect cpu state reporting (gdb,
monitor) and should also corrupt its saving (savevm, migration). Drop
the related lines.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6461 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 20:32:22 +00:00
aliguori
f55761a0c4 x86: Issue reset on triple faults (Jan Kiszka)
As discussed a few times on this list: A triple fault causes a system
reset on x86, and some guests make use of this (e.g. 386BSD). To keep
the chance of tracing unexpected resets, log them if CPU_LOG_RESET is
set.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6453 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 19:54:36 +00:00
aliguori
eca1bdf415 Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 19:54:31 +00:00
aliguori
165d9b82eb MTRR support on x86 (Carl-Daniel Hailfinger)
The current codebase ignores MTRR (Memory Type Range Register)
configuration writes and reads because Qemu does not implement caching.
All BIOS/firmware in know of for x86 do implement a mode called
Cache-as-RAM (CAR) which locks down the CPU cache lines and uses the CPU
cache like RAM before RAM is enabled. Qemu assumes RAM is accessible
from the start, but it would be nice to be able to run real
BIOS/firmware in Qemu. For that, we need CAR support and for CAR support
we have to support MTRRs.

This patch is a first step in that direction. MTRRs are MSRs supported
by all recent x86 CPUs, even old i586. Besides influencing cache, the
MTRRs can be written and read back, so discarding MTRR writes violates
the expectations of existing code out there.

An added benefit of this patch is that it fixes the following Linux
kernel error message present in recent kernels (provided the BIOS has
the recent MTRR patches applied):
 ------------[ cut here ]------------
WARNING: at arch/x86/kernel/cpu/mtrr/main.c:1500 mtrr_trim_uncached_memory+0x382/0x384()
WARNING: strange, CPU MTRRs all blank?
Modules linked in:
Supported: Yes
Pid: 0, comm: swapper Not tainted 2.6.27.7-9-default #1
 [<c0106570>] dump_trace+0x6b/0x249
 [<c01070a5>] show_trace+0x20/0x39
 [<c0343c02>] dump_stack+0x71/0x76
 [<c012acb2>] warn_slowpath+0x6f/0x90
 [<c0542f8f>] mtrr_trim_uncached_memory+0x382/0x384
 [<c053f24d>] setup_arch+0x40d/0x639
 [<c053a6ac>] start_kernel+0x6b/0x31f
 =======================
 ---[ end trace 4eaa2a86a8e2da22 ]---

Handle common x86 MTRR reads and writes, but don't act on them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6449 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 17:53:04 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:34:14 +00:00
aliguori
d12d51d5ba Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:48:06 +00:00
blueswir1
1c918eba9a Suppress i386 warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6304 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:27:02 +00:00
blueswir1
7d99a001df Add noreturn function attribute
Introduce noreturn attribute and attach it to cpu_loop_exit as well as
interrupt/exception helpers for i386. This avoids a bunch of gcc4
warnings.

[ Note that this patch comes with a workaround to include qemu-common.h
even in cases where is currently causes conflicts with dyngen-exec.h.
I've been told that these conflicts will get resolved in the future
(/me will try to have a look as well - as time permits). ]

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6303 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:00:36 +00:00
aurel32
fad6cb1a56 Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:05:52 +00:00
malc
b1503cda1e Use the ARRAY_SIZE() macro where appropriate.
Change from v1:
  Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22 20:33:55 +00:00
aliguori
55308450d4 Initialize msr list size properly in KVM
Hollis Blanchard noticed that the last commit was not sufficient.  We also need
to initialize the msr size in our newly allocated list.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6018 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 20:49:31 +00:00
aliguori
4c9f7372fc Correctly initialize msr list in KVM
I believe this was spotted by Gerd Hoffman but I can't find his patch 
now.  This will cause very subtle corruption on the heap because we 
don't allocate the appropriately sized buffer.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6017 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 20:41:58 +00:00
malc
f60d2728cc Fix smsw for x86_64 guest and bigendian host case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6009 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 15:51:14 +00:00
blueswir1
d9957a8b0f x86 cleanup
Remove some unnecessary includes, add needed includes, move prototypes to
cpu.h to suppress missing prototype warnings.

Remove unused functions and prototypes (cpu_x86_flush_tlb, cpu_lock,
cpu_unlock, restore_native_fp_state, save_native_fp_state).

Make some functions and data static (f15rk, parity_table, rclw_table,
rclb_table, raise_interrupt, fpu_raise_exception), they are not used
outside op_helper.c anymore.

Make some x86_64 and user only code conditional to avoid warnings.

Document where each function is implemented in cpu.h and exec.h.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6005 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 11:49:17 +00:00
aliguori
40a2d7050a Fix crash in kvm.c (Stefan Weil)
Fix crash with kvm enabled.

Signed-off-by: Stefan Weil <weil@mail.berlios.de> 
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5984 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 21:03:10 +00:00
aurel32
32938e127f target-i386: Fix jmp im on x86_64 when executing 32-bit code
When running grub-install (32-bit) on an x86_64 Linux system in qemu, it
hangs on a pagefault forever, because an integer overflow occurs on the
IP on "jmp im". This patch masks overflows for 32 bit IPs on a 64 bit
system, just like it is done for 16 bit IPs already.

Using this patch, x86_64 openSUSE installation works again.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Kevin Wolf <kwolf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5963 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 15:02:16 +00:00
aurel32
db8d990204 Remove FORCE_RET() and RETURN()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:15:54 +00:00
aurel32
0b97134b29 target-i386: fix CVE-2007-1322
The icebp instruction can be abused to terminate the emulation,
resulting in denial of service.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5921 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:15:36 +00:00
aliguori
d4b55be509 Fix register name typo in dumping debug registers (Jan Kiszka)
Signed-off-by: Jan Kiszka <jan.kiszka@web.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5855 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-02 19:40:26 +00:00
balrog
dcfd12b83e Fix pmovsx* / pmovzx* SSE instructions (original fix by Frank Mehnert).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5841 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01 01:52:37 +00:00
aurel32
2cbd949d7a Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:09 +00:00
aliguori
c0ce998e94 Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25 22:13:57 +00:00
aliguori
9c99d2ab02 i386: remove unused function prototypes (Laurent Desnogues)
This patch removes two unused prototypes from i386 target exec.h file.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5795 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25 17:19:45 +00:00
aliguori
a59cb4e023 x86: Dump debug registers (Jan Kiszka)
As the debug registers are no longer dummies, let's include their
current state into the 'info registers' output and other register dumps.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5748 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 21:09:47 +00:00
aliguori
01df040b52 x86: Debug register emulation (Jan Kiszka)
Built on top of previously enhanced breakpoint/watchpoint support, this
patch adds full debug register emulation for the x86 architecture.

Many corner cases were considered, and the result was successfully
tested inside a Linux guest with gdb, but I won't be surprised if one
or two scenarios still behave differently in reality.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5747 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 21:08:15 +00:00
aliguori
a1d1bb3101 Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.

Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 20:07:32 +00:00
aliguori
6b9175478e Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:46:41 +00:00
aliguori
622ed3605b Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:36:03 +00:00
pbrook
a7812ae412 TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
aurel32
30913bae9a target-i386: fix helper_pmovmskb_mmx helper
(malc)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5728 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-16 19:15:15 +00:00