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target-i386: implement lzcnt emulation

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lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Andre Przywara 2009-10-23 13:44:31 +02:00 committed by Aurelien Jarno
parent cb2dbfc351
commit 31501a714b
3 changed files with 38 additions and 14 deletions
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1
target-i386/helper.h
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@ -193,6 +193,7 @@ DEF_HELPER_2(fxsave, void, tl, int)
DEF_HELPER_2(fxrstor, void, tl, int)
DEF_HELPER_1(bsf, tl, tl)
DEF_HELPER_1(bsr, tl, tl)
DEF_HELPER_2(lzcnt, tl, tl, int)
/* MMX/SSE */

14
target-i386/op_helper.c
View File

@ -5479,11 +5479,14 @@ target_ulong helper_bsf(target_ulong t0)
return count;
}
target_ulong helper_bsr(target_ulong t0)
target_ulong helper_lzcnt(target_ulong t0, int wordsize)
{
int count;
target_ulong res, mask;
if (wordsize > 0 && t0 == 0) {
return wordsize;
}
res = t0;
count = TARGET_LONG_BITS - 1;
mask = (target_ulong)1 << (TARGET_LONG_BITS - 1);
@ -5491,9 +5494,16 @@ target_ulong helper_bsr(target_ulong t0)
count--;
res <<= 1;
}
if (wordsize > 0) {
return wordsize - 1 - count;
}
return count;
}
target_ulong helper_bsr(target_ulong t0)
{
return helper_lzcnt(t0, 0);
}
static int compute_all_eflags(void)
{

37
target-i386/translate.c
View File

@ -6573,23 +6573,36 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
ot = dflag + OT_WORD;
modrm = ldub_code(s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
gen_extu(ot, cpu_T[0]);
label1 = gen_new_label();
tcg_gen_movi_tl(cpu_cc_dst, 0);
t0 = tcg_temp_local_new();
tcg_gen_mov_tl(t0, cpu_T[0]);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
if (b & 1) {
gen_helper_bsr(cpu_T[0], t0);
if ((b & 1) && (prefixes & PREFIX_REPZ) &&
(s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
switch(ot) {
case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
tcg_const_i32(16)); break;
case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
tcg_const_i32(32)); break;
case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
tcg_const_i32(64)); break;
}
gen_op_mov_reg_T0(ot, reg);
} else {
gen_helper_bsf(cpu_T[0], t0);
label1 = gen_new_label();
tcg_gen_movi_tl(cpu_cc_dst, 0);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
if (b & 1) {
gen_helper_bsr(cpu_T[0], t0);
} else {
gen_helper_bsf(cpu_T[0], t0);
}
gen_op_mov_reg_T0(ot, reg);
tcg_gen_movi_tl(cpu_cc_dst, 1);
gen_set_label(label1);
tcg_gen_discard_tl(cpu_cc_src);
s->cc_op = CC_OP_LOGICB + ot;
}
gen_op_mov_reg_T0(ot, reg);
tcg_gen_movi_tl(cpu_cc_dst, 1);
gen_set_label(label1);
tcg_gen_discard_tl(cpu_cc_src);
s->cc_op = CC_OP_LOGICB + ot;
tcg_temp_free(t0);
}
break;