apic: qdev conversion cleanup
Make APICState completely private to apic.c by using DeviceState in external APIs. Move apic_init() to pc.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
8546b09965
commit
92a16d7a9a
86
hw/apic.c
86
hw/apic.c
@ -18,7 +18,6 @@
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*/
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#include "hw.h"
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#include "apic.h"
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#include "msix.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "sysbus.h"
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@ -89,9 +88,10 @@
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#define MSI_ADDR_DEST_ID_SHIFT 12
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
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#define MSI_ADDR_BASE 0xfee00000
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#define MSI_ADDR_SIZE 0x100000
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typedef struct APICState APICState;
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struct APICState {
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SysBusDevice busdev;
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void *cpu_env;
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@ -195,8 +195,10 @@ static void apic_local_deliver(APICState *s, int vector)
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}
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}
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void apic_deliver_pic_intr(APICState *s, int level)
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void apic_deliver_pic_intr(DeviceState *d, int level)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0);
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} else {
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@ -306,8 +308,10 @@ void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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trigger_mode);
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}
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void cpu_set_apic_base(APICState *s, uint64_t val)
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void cpu_set_apic_base(DeviceState *d, uint64_t val)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val);
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if (!s)
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return;
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@ -321,23 +325,29 @@ void cpu_set_apic_base(APICState *s, uint64_t val)
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}
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}
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uint64_t cpu_get_apic_base(APICState *s)
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uint64_t cpu_get_apic_base(DeviceState *d)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n",
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s ? (uint64_t)s->apicbase: 0);
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return s ? s->apicbase : 0;
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}
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void cpu_set_apic_tpr(APICState *s, uint8_t val)
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void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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if (!s)
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return;
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s->tpr = (val & 0x0f) << 4;
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apic_update_irq(s);
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}
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uint8_t cpu_get_apic_tpr(APICState *s)
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uint8_t cpu_get_apic_tpr(DeviceState *d)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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return s ? s->tpr >> 4 : 0;
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}
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@ -479,9 +489,9 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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}
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}
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void apic_init_reset(APICState *s)
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void apic_init_reset(DeviceState *d)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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int i;
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if (!s)
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@ -512,8 +522,10 @@ static void apic_startup(APICState *s, int vector_num)
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
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}
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void apic_sipi(APICState *s)
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void apic_sipi(DeviceState *d)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
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if (!s->wait_for_sipi)
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@ -522,10 +534,11 @@ void apic_sipi(APICState *s)
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s->wait_for_sipi = 0;
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}
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static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
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static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t polarity, uint8_t trigger_mode)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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int dest_shorthand = (s->icr[0] >> 18) & 3;
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APICState *apic_iter;
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@ -570,8 +583,9 @@ static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
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trigger_mode);
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}
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int apic_get_interrupt(APICState *s)
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int apic_get_interrupt(DeviceState *d)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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int intno;
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/* if the APIC is installed or enabled, we let the 8259 handle the
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@ -593,8 +607,9 @@ int apic_get_interrupt(APICState *s)
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return intno;
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}
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int apic_accept_pic_intr(APICState *s)
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int apic_accept_pic_intr(DeviceState *d)
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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uint32_t lvt0;
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if (!s)
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@ -680,14 +695,16 @@ static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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DeviceState *d;
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APICState *s;
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uint32_t val;
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int index;
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s = cpu_get_current_apic();
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if (!s) {
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d = cpu_get_current_apic();
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if (!d) {
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return 0;
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}
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s = DO_UPCAST(APICState, busdev.qdev, d);
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index = (addr >> 4) & 0xff;
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switch(index) {
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@ -769,6 +786,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32 data)
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static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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DeviceState *d;
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APICState *s;
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int index = (addr >> 4) & 0xff;
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if (addr > 0xfff || !index) {
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@ -781,10 +799,11 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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return;
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}
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s = cpu_get_current_apic();
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if (!s) {
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d = cpu_get_current_apic();
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if (!d) {
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return;
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}
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s = DO_UPCAST(APICState, busdev.qdev, d);
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DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val);
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@ -821,7 +840,7 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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case 0x30:
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s->icr[0] = val;
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apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
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apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
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(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
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(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
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break;
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@ -935,7 +954,7 @@ static void apic_reset(DeviceState *d)
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s->apicbase = 0xfee00000 |
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(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
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apic_init_reset(s);
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apic_init_reset(d);
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if (bsp) {
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/*
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@ -959,35 +978,6 @@ static CPUWriteMemoryFunc * const apic_mem_write[3] = {
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apic_mem_writel,
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};
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APICState *apic_init(void *env, uint8_t apic_id)
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{
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DeviceState *dev;
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SysBusDevice *d;
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APICState *s;
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static int apic_mapped;
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dev = qdev_create(NULL, "apic");
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qdev_prop_set_uint8(dev, "id", apic_id);
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qdev_prop_set_ptr(dev, "cpu_env", env);
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qdev_init_nofail(dev);
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d = sysbus_from_qdev(dev);
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/* XXX: mapping more APICs at the same memory location */
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if (apic_mapped == 0) {
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/* NOTE: the APIC is directly connected to the CPU - it is not
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on the global memory bus. */
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/* XXX: what if the base changes? */
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sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
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apic_mapped = 1;
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}
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msix_supported = 1;
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s = DO_UPCAST(APICState, busdev.qdev, dev);
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return s;
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}
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static int apic_init1(SysBusDevice *dev)
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{
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APICState *s = FROM_SYSBUS(APICState, dev);
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24
hw/apic.h
24
hw/apic.h
@ -1,27 +1,27 @@
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#ifndef APIC_H
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#define APIC_H
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#include "qemu-common.h"
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/* apic.c */
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typedef struct APICState APICState;
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode);
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APICState *apic_init(void *env, uint8_t apic_id);
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int apic_accept_pic_intr(APICState *s);
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void apic_deliver_pic_intr(APICState *s, int level);
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int apic_get_interrupt(APICState *s);
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int apic_accept_pic_intr(DeviceState *s);
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void apic_deliver_pic_intr(DeviceState *s, int level);
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int apic_get_interrupt(DeviceState *s);
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void apic_reset_irq_delivered(void);
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int apic_get_irq_delivered(void);
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void cpu_set_apic_base(APICState *s, uint64_t val);
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uint64_t cpu_get_apic_base(APICState *s);
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void cpu_set_apic_tpr(APICState *s, uint8_t val);
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uint8_t cpu_get_apic_tpr(APICState *s);
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void apic_init_reset(APICState *s);
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void apic_sipi(APICState *s);
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void cpu_set_apic_base(DeviceState *s, uint64_t val);
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uint64_t cpu_get_apic_base(DeviceState *s);
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void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
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uint8_t cpu_get_apic_tpr(DeviceState *s);
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void apic_init_reset(DeviceState *s);
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void apic_sipi(DeviceState *s);
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/* pc.c */
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int cpu_is_bsp(CPUState *env);
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APICState *cpu_get_current_apic(void);
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DeviceState *cpu_get_current_apic(void);
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#endif
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31
hw/pc.c
31
hw/pc.c
@ -35,6 +35,7 @@
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#include "elf.h"
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#include "multiboot.h"
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#include "mc146818rtc.h"
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#include "msix.h"
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#include "sysbus.h"
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#include "sysemu.h"
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@ -64,6 +65,8 @@
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
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#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
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#define MSI_ADDR_BASE 0xfee00000
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#define E820_NR_ENTRIES 16
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struct e820_entry {
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@ -754,7 +757,7 @@ int cpu_is_bsp(CPUState *env)
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return env->cpu_index == 0;
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}
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APICState *cpu_get_current_apic(void)
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DeviceState *cpu_get_current_apic(void)
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{
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if (cpu_single_env) {
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return cpu_single_env->apic_state;
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@ -763,6 +766,32 @@ APICState *cpu_get_current_apic(void)
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}
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}
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static DeviceState *apic_init(void *env, uint8_t apic_id)
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{
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DeviceState *dev;
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SysBusDevice *d;
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static int apic_mapped;
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dev = qdev_create(NULL, "apic");
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qdev_prop_set_uint8(dev, "id", apic_id);
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qdev_prop_set_ptr(dev, "cpu_env", env);
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qdev_init_nofail(dev);
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d = sysbus_from_qdev(dev);
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/* XXX: mapping more APICs at the same memory location */
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if (apic_mapped == 0) {
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/* NOTE: the APIC is directly connected to the CPU - it is not
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on the global memory bus. */
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/* XXX: what if the base changes? */
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sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
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apic_mapped = 1;
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}
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msix_supported = 1;
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return dev;
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}
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/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
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BIOS will read it and start S3 resume at POST Entry */
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void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
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@ -16,6 +16,7 @@
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typedef struct QEMUTimer QEMUTimer;
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typedef struct QEMUFile QEMUFile;
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typedef struct QEMUBH QEMUBH;
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typedef struct DeviceState DeviceState;
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/* Hack around the mess dyngen-exec.h causes: We need QEMU_NORETURN in files that
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cannot include the following headers without conflicts. This condition has
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@ -224,7 +225,6 @@ typedef struct PCMCIACardState PCMCIACardState;
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typedef struct MouseTransformInfo MouseTransformInfo;
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typedef struct uWireSlave uWireSlave;
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typedef struct I2SCodec I2SCodec;
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typedef struct DeviceState DeviceState;
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typedef struct SSIBus SSIBus;
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typedef struct EventNotifier EventNotifier;
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typedef struct VirtIODevice VirtIODevice;
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@ -705,7 +705,7 @@ typedef struct CPUX86State {
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/* in order to simplify APIC support, we leave this pointer to the
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user */
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struct APICState *apic_state;
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struct DeviceState *apic_state;
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uint64 mcg_cap;
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uint64 mcg_status;
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