2003-05-13 04:25:15 +04:00
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/*
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2003-05-14 23:00:11 +04:00
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* virtual page mapping and translated block handling
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2007-09-17 01:08:06 +04:00
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*
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2003-05-13 04:25:15 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-05-13 04:25:15 +04:00
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*/
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2004-04-01 03:37:16 +04:00
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#include "config.h"
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2004-09-30 01:15:28 +04:00
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#ifdef _WIN32
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#include <windows.h>
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#else
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2004-11-14 19:22:05 +03:00
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#include <sys/types.h>
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2004-09-30 01:15:28 +04:00
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#include <sys/mman.h>
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#endif
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2003-05-13 04:25:15 +04:00
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2010-10-23 01:03:32 +04:00
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#include "qemu-common.h"
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2003-10-01 01:04:53 +04:00
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#include "cpu.h"
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2008-05-23 13:57:34 +04:00
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#include "tcg.h"
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2008-06-30 20:31:04 +04:00
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#include "hw/hw.h"
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2010-06-25 21:09:43 +04:00
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#include "hw/qdev.h"
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2008-10-06 18:02:03 +04:00
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#include "osdep.h"
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2008-11-05 19:04:33 +03:00
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#include "kvm.h"
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2010-08-31 19:41:25 +04:00
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#include "hw/xen.h"
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2010-03-29 23:24:00 +04:00
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#include "qemu-timer.h"
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2011-07-26 15:26:14 +04:00
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#include "memory.h"
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#include "exec-memory.h"
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2006-03-25 22:31:22 +03:00
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h>
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2010-03-26 00:32:16 +03:00
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#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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#include <sys/param.h>
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#if __FreeBSD_version >= 700104
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#define HAVE_KINFO_GETVMMAP
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#define sigqueue sigqueue_freebsd /* avoid redefinition */
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#include <sys/time.h>
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#include <sys/proc.h>
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#include <machine/profile.h>
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#define _KERNEL
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#include <sys/user.h>
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#undef _KERNEL
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#undef sigqueue
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#include <libutil.h>
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#endif
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#endif
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2010-08-31 19:41:25 +04:00
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#else /* !CONFIG_USER_ONLY */
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#include "xen-mapcache.h"
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2011-05-19 21:35:44 +04:00
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#include "trace.h"
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2006-03-25 22:31:22 +03:00
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#endif
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2003-05-13 04:25:15 +04:00
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2011-12-15 17:25:22 +04:00
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#define WANT_EXEC_OBSOLETE
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#include "exec-obsolete.h"
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2003-05-14 23:00:11 +04:00
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//#define DEBUG_TB_INVALIDATE
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2003-06-24 17:28:12 +04:00
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//#define DEBUG_FLUSH
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2004-01-04 21:06:42 +03:00
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//#define DEBUG_TLB
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2006-12-18 08:03:52 +03:00
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//#define DEBUG_UNASSIGNED
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2003-05-14 23:00:11 +04:00
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/* make various TB consistency checks */
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2007-09-17 01:08:06 +04:00
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//#define DEBUG_TB_CHECK
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//#define DEBUG_TLB_CHECK
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2003-05-14 23:00:11 +04:00
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2007-03-17 18:17:58 +03:00
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//#define DEBUG_IOPORT
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2007-05-26 21:36:03 +04:00
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//#define DEBUG_SUBPAGE
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2007-03-17 18:17:58 +03:00
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2006-04-16 19:14:59 +04:00
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#if !defined(CONFIG_USER_ONLY)
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/* TB consistency checks only implemented for usermode emulation. */
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#undef DEBUG_TB_CHECK
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#endif
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2004-01-04 21:06:42 +03:00
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#define SMC_BITMAP_USE_THRESHOLD 10
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2008-10-04 11:24:27 +04:00
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static TranslationBlock *tbs;
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2010-07-19 20:23:17 +04:00
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static int code_gen_max_blocks;
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2004-01-04 21:06:42 +03:00
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TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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2008-10-04 11:24:27 +04:00
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static int nb_tbs;
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2003-05-15 01:51:13 +04:00
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/* any access to the tbs or the page table must use this lock */
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2009-10-02 01:12:16 +04:00
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spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
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2003-05-14 23:00:11 +04:00
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2008-07-26 19:05:57 +04:00
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#if defined(__arm__) || defined(__sparc_v9__)
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/* The prologue must be reachable with a direct jump. ARM and Sparc64
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have limited branch ranges (possibly also PPC) so place it in a
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2008-07-10 21:21:31 +04:00
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section close to code segment. */
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#define code_gen_section \
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__attribute__((__section__(".gen_code"))) \
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__attribute__((aligned (32)))
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2009-06-19 01:04:48 +04:00
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#elif defined(_WIN32)
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/* Maximum alignment for Win32 is 16. */
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#define code_gen_section \
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__attribute__((aligned (16)))
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2008-07-10 21:21:31 +04:00
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#else
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#define code_gen_section \
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__attribute__((aligned (32)))
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#endif
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uint8_t code_gen_prologue[1024] code_gen_section;
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2008-10-04 11:24:27 +04:00
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static uint8_t *code_gen_buffer;
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static unsigned long code_gen_buffer_size;
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2008-05-28 16:30:31 +04:00
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/* threshold to flush the translated code buffer */
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2008-10-04 11:24:27 +04:00
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static unsigned long code_gen_buffer_max_size;
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2010-07-19 20:23:17 +04:00
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static uint8_t *code_gen_ptr;
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2003-05-14 23:00:11 +04:00
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2008-06-08 05:09:01 +04:00
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#if !defined(CONFIG_USER_ONLY)
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2004-01-04 21:06:42 +03:00
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int phys_ram_fd;
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2008-10-06 18:02:03 +04:00
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static int in_migration;
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2009-04-11 21:15:54 +04:00
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2011-08-12 15:18:14 +04:00
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RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
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2011-07-26 15:26:14 +04:00
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static MemoryRegion *system_memory;
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2011-08-08 17:09:03 +04:00
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static MemoryRegion *system_io;
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2011-07-26 15:26:14 +04:00
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2012-01-02 02:32:15 +04:00
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MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty;
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2012-01-02 14:41:07 +04:00
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static MemoryRegion io_mem_subpage_ram;
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2012-01-02 02:32:15 +04:00
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2008-06-08 05:09:01 +04:00
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#endif
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2004-01-04 21:06:42 +03:00
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2005-11-22 02:25:50 +03:00
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CPUState *first_cpu;
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/* current CPU in the current thread. It is only valid inside
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cpu_exec() */
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2011-10-28 13:52:42 +04:00
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DEFINE_TLS(CPUState *,cpu_single_env);
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2008-06-29 05:03:05 +04:00
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/* 0 = Do not count executed instructions.
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2008-06-30 21:22:19 +04:00
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1 = Precise instruction counting.
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2008-06-29 05:03:05 +04:00
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2 = Adaptive rate instruction counting. */
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int use_icount = 0;
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2005-11-22 02:25:50 +03:00
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2003-05-13 04:25:15 +04:00
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typedef struct PageDesc {
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2004-05-21 18:52:29 +04:00
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/* list of TBs intersecting this ram page */
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2003-05-14 23:00:11 +04:00
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TranslationBlock *first_tb;
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2004-01-04 21:06:42 +03:00
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/* in order to optimize self modifying code, we count the number
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of lookups we do to a given page to use a bitmap */
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unsigned int code_write_count;
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uint8_t *code_bitmap;
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#if defined(CONFIG_USER_ONLY)
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unsigned long flags;
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#endif
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2003-05-13 04:25:15 +04:00
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} PageDesc;
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2010-03-12 19:54:58 +03:00
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/* In system mode we want L1_MAP to be based on ram offsets,
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2010-03-11 02:53:37 +03:00
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while in user mode we want it to be based on virtual addresses. */
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#if !defined(CONFIG_USER_ONLY)
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2010-03-12 19:54:58 +03:00
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#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
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# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
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#else
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2010-03-11 02:53:37 +03:00
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# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
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2010-03-12 19:54:58 +03:00
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#endif
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2007-04-06 00:08:21 +04:00
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#else
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2010-03-11 02:53:37 +03:00
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# define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS
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2007-04-06 00:08:21 +04:00
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#endif
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2003-05-13 04:25:15 +04:00
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2010-03-11 02:53:37 +03:00
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/* Size of the L2 (and L3, etc) page tables. */
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#define L2_BITS 10
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2003-05-13 04:25:15 +04:00
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#define L2_SIZE (1 << L2_BITS)
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2010-03-11 02:53:37 +03:00
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/* The bits remaining after N lower levels of page tables. */
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#define P_L1_BITS_REM \
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((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
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#define V_L1_BITS_REM \
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((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
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/* Size of the L1 page table. Avoid silly small sizes. */
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#if P_L1_BITS_REM < 4
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#define P_L1_BITS (P_L1_BITS_REM + L2_BITS)
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#else
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#define P_L1_BITS P_L1_BITS_REM
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#endif
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#if V_L1_BITS_REM < 4
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#define V_L1_BITS (V_L1_BITS_REM + L2_BITS)
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#else
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#define V_L1_BITS V_L1_BITS_REM
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#endif
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#define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS)
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#define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
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#define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS)
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#define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
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2004-07-06 01:25:26 +04:00
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unsigned long qemu_real_host_page_size;
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unsigned long qemu_host_page_size;
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unsigned long qemu_host_page_mask;
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2003-05-13 04:25:15 +04:00
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2010-03-11 02:53:37 +03:00
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/* This is a multi-level map on the virtual address space.
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The bottom level has pointers to PageDesc. */
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static void *l1_map[V_L1_SIZE];
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2003-05-13 04:25:15 +04:00
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2008-06-08 05:09:01 +04:00
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#if !defined(CONFIG_USER_ONLY)
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2010-03-12 19:54:58 +03:00
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typedef struct PhysPageDesc {
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/* offset in host memory of the page + io_index in the low bits */
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ram_addr_t phys_offset;
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ram_addr_t region_offset;
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} PhysPageDesc;
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2010-03-11 02:53:37 +03:00
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/* This is a multi-level map on the physical address space.
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The bottom level has pointers to PhysPageDesc. */
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static void *l1_phys_map[P_L1_SIZE];
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2010-03-01 02:55:53 +03:00
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2008-06-08 05:09:01 +04:00
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static void io_mem_init(void);
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2011-07-26 15:26:14 +04:00
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static void memory_map_init(void);
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2008-06-08 05:09:01 +04:00
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2003-08-11 01:47:01 +04:00
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/* io memory support */
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2012-01-02 15:12:08 +04:00
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MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
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2009-03-07 18:32:56 +03:00
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static char io_mem_used[IO_MEM_NB_ENTRIES];
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2012-01-02 14:47:48 +04:00
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static MemoryRegion io_mem_watch;
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2007-03-17 02:58:11 +03:00
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#endif
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2003-08-11 01:47:01 +04:00
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2003-10-05 18:28:56 +04:00
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/* log support */
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2009-12-03 16:56:02 +03:00
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#ifdef WIN32
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static const char *logfilename = "qemu.log";
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#else
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2008-10-05 13:57:08 +04:00
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static const char *logfilename = "/tmp/qemu.log";
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2009-12-03 16:56:02 +03:00
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#endif
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2003-10-05 18:28:56 +04:00
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FILE *logfile;
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int loglevel;
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2007-06-30 17:53:24 +04:00
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static int log_append = 0;
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2003-10-05 18:28:56 +04:00
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2005-01-27 01:00:47 +03:00
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/* statistics */
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2010-03-12 19:54:58 +03:00
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#if !defined(CONFIG_USER_ONLY)
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2005-01-27 01:00:47 +03:00
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static int tlb_flush_count;
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2010-03-12 19:54:58 +03:00
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#endif
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2005-01-27 01:00:47 +03:00
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static int tb_flush_count;
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static int tb_phys_invalidate_count;
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2008-05-10 14:55:51 +04:00
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#ifdef _WIN32
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static void map_exec(void *addr, long size)
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{
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DWORD old_protect;
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VirtualProtect(addr, size,
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PAGE_EXECUTE_READWRITE, &old_protect);
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}
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#else
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static void map_exec(void *addr, long size)
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{
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2008-05-29 13:35:57 +04:00
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unsigned long start, end, page_size;
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2008-05-10 14:55:51 +04:00
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2008-05-29 13:35:57 +04:00
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page_size = getpagesize();
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2008-05-10 14:55:51 +04:00
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start = (unsigned long)addr;
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2008-05-29 13:35:57 +04:00
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start &= ~(page_size - 1);
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2008-05-10 14:55:51 +04:00
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end = (unsigned long)addr + size;
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2008-05-29 13:35:57 +04:00
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end += page_size - 1;
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end &= ~(page_size - 1);
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2008-05-10 14:55:51 +04:00
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mprotect((void *)start, end - start,
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PROT_READ | PROT_WRITE | PROT_EXEC);
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}
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#endif
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2003-06-16 00:05:50 +04:00
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static void page_init(void)
|
2003-05-13 04:25:15 +04:00
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{
|
2004-07-06 01:25:26 +04:00
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/* NOTE: we can always suppose that qemu_host_page_size >=
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2003-05-13 04:25:15 +04:00
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TARGET_PAGE_SIZE */
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2008-11-12 01:06:42 +03:00
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#ifdef _WIN32
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{
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SYSTEM_INFO system_info;
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GetSystemInfo(&system_info);
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qemu_real_host_page_size = system_info.dwPageSize;
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}
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#else
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qemu_real_host_page_size = getpagesize();
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#endif
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2004-07-06 01:25:26 +04:00
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|
|
if (qemu_host_page_size == 0)
|
|
|
|
qemu_host_page_size = qemu_real_host_page_size;
|
|
|
|
if (qemu_host_page_size < TARGET_PAGE_SIZE)
|
|
|
|
qemu_host_page_size = TARGET_PAGE_SIZE;
|
|
|
|
qemu_host_page_mask = ~(qemu_host_page_size - 1);
|
2007-12-12 04:16:23 +03:00
|
|
|
|
2010-05-05 19:32:59 +04:00
|
|
|
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
|
2007-12-12 04:16:23 +03:00
|
|
|
{
|
2010-03-26 00:32:16 +03:00
|
|
|
#ifdef HAVE_KINFO_GETVMMAP
|
|
|
|
struct kinfo_vmentry *freep;
|
|
|
|
int i, cnt;
|
|
|
|
|
|
|
|
freep = kinfo_getvmmap(getpid(), &cnt);
|
|
|
|
if (freep) {
|
|
|
|
mmap_lock();
|
|
|
|
for (i = 0; i < cnt; i++) {
|
|
|
|
unsigned long startaddr, endaddr;
|
|
|
|
|
|
|
|
startaddr = freep[i].kve_start;
|
|
|
|
endaddr = freep[i].kve_end;
|
|
|
|
if (h2g_valid(startaddr)) {
|
|
|
|
startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
|
|
|
|
|
|
|
|
if (h2g_valid(endaddr)) {
|
|
|
|
endaddr = h2g(endaddr);
|
2010-04-10 19:20:36 +04:00
|
|
|
page_set_flags(startaddr, endaddr, PAGE_RESERVED);
|
2010-03-26 00:32:16 +03:00
|
|
|
} else {
|
|
|
|
#if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
|
|
|
|
endaddr = ~0ul;
|
2010-04-10 19:20:36 +04:00
|
|
|
page_set_flags(startaddr, endaddr, PAGE_RESERVED);
|
2010-03-26 00:32:16 +03:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
free(freep);
|
|
|
|
mmap_unlock();
|
|
|
|
}
|
|
|
|
#else
|
2007-12-12 04:16:23 +03:00
|
|
|
FILE *f;
|
|
|
|
|
2008-05-31 20:33:53 +04:00
|
|
|
last_brk = (unsigned long)sbrk(0);
|
2010-03-11 02:53:37 +03:00
|
|
|
|
2010-04-10 19:20:36 +04:00
|
|
|
f = fopen("/compat/linux/proc/self/maps", "r");
|
2007-12-12 04:16:23 +03:00
|
|
|
if (f) {
|
2010-03-11 02:53:37 +03:00
|
|
|
mmap_lock();
|
|
|
|
|
2007-12-12 04:16:23 +03:00
|
|
|
do {
|
2010-03-11 02:53:37 +03:00
|
|
|
unsigned long startaddr, endaddr;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr);
|
|
|
|
|
|
|
|
if (n == 2 && h2g_valid(startaddr)) {
|
|
|
|
startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
|
|
|
|
|
|
|
|
if (h2g_valid(endaddr)) {
|
|
|
|
endaddr = h2g(endaddr);
|
|
|
|
} else {
|
|
|
|
endaddr = ~0ul;
|
|
|
|
}
|
|
|
|
page_set_flags(startaddr, endaddr, PAGE_RESERVED);
|
2007-12-12 04:16:23 +03:00
|
|
|
}
|
|
|
|
} while (!feof(f));
|
2010-03-11 02:53:37 +03:00
|
|
|
|
2007-12-12 04:16:23 +03:00
|
|
|
fclose(f);
|
2010-03-11 02:53:37 +03:00
|
|
|
mmap_unlock();
|
2007-12-12 04:16:23 +03:00
|
|
|
}
|
2010-03-26 00:32:16 +03:00
|
|
|
#endif
|
2007-12-12 04:16:23 +03:00
|
|
|
}
|
|
|
|
#endif
|
2003-05-13 04:25:15 +04:00
|
|
|
}
|
|
|
|
|
2010-03-12 19:54:58 +03:00
|
|
|
static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
|
2003-05-13 04:25:15 +04:00
|
|
|
{
|
2010-03-12 19:54:58 +03:00
|
|
|
PageDesc *pd;
|
|
|
|
void **lp;
|
|
|
|
int i;
|
|
|
|
|
2010-03-11 02:53:37 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2011-08-21 07:09:37 +04:00
|
|
|
/* We can't use g_malloc because it may recurse into a locked mutex. */
|
2010-03-11 02:53:37 +03:00
|
|
|
# define ALLOC(P, SIZE) \
|
|
|
|
do { \
|
|
|
|
P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \
|
|
|
|
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \
|
|
|
|
} while (0)
|
|
|
|
#else
|
|
|
|
# define ALLOC(P, SIZE) \
|
2011-08-21 07:09:37 +04:00
|
|
|
do { P = g_malloc0(SIZE); } while (0)
|
2008-06-09 17:47:45 +04:00
|
|
|
#endif
|
2008-09-15 19:56:30 +04:00
|
|
|
|
2010-03-11 02:53:37 +03:00
|
|
|
/* Level 1. Always allocated. */
|
|
|
|
lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
|
|
|
|
|
|
|
|
/* Level 2..N-1. */
|
|
|
|
for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
|
|
|
|
void **p = *lp;
|
|
|
|
|
|
|
|
if (p == NULL) {
|
|
|
|
if (!alloc) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
ALLOC(p, sizeof(void *) * L2_SIZE);
|
|
|
|
*lp = p;
|
2008-06-09 17:47:45 +04:00
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
|
|
|
|
lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
|
|
|
|
}
|
|
|
|
|
|
|
|
pd = *lp;
|
|
|
|
if (pd == NULL) {
|
|
|
|
if (!alloc) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
ALLOC(pd, sizeof(PageDesc) * L2_SIZE);
|
|
|
|
*lp = pd;
|
2003-05-13 04:25:15 +04:00
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
|
|
|
|
#undef ALLOC
|
|
|
|
|
|
|
|
return pd + (index & (L2_SIZE - 1));
|
2003-05-13 04:25:15 +04:00
|
|
|
}
|
|
|
|
|
2010-03-12 19:54:58 +03:00
|
|
|
static inline PageDesc *page_find(tb_page_addr_t index)
|
2003-05-13 04:25:15 +04:00
|
|
|
{
|
2010-03-11 02:53:37 +03:00
|
|
|
return page_find_alloc(index, 0);
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
|
2010-03-01 02:55:53 +03:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2009-10-02 01:12:16 +04:00
|
|
|
static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
|
2004-05-21 18:52:29 +04:00
|
|
|
{
|
2006-04-09 00:02:06 +04:00
|
|
|
PhysPageDesc *pd;
|
2010-03-11 02:53:37 +03:00
|
|
|
void **lp;
|
|
|
|
int i;
|
2004-05-21 18:52:29 +04:00
|
|
|
|
2010-03-11 02:53:37 +03:00
|
|
|
/* Level 1. Always allocated. */
|
|
|
|
lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1));
|
2005-07-24 16:55:09 +04:00
|
|
|
|
2010-03-11 02:53:37 +03:00
|
|
|
/* Level 2..N-1. */
|
|
|
|
for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
|
|
|
|
void **p = *lp;
|
|
|
|
if (p == NULL) {
|
|
|
|
if (!alloc) {
|
|
|
|
return NULL;
|
|
|
|
}
|
2011-08-21 07:09:37 +04:00
|
|
|
*lp = p = g_malloc0(sizeof(void *) * L2_SIZE);
|
2010-03-11 02:53:37 +03:00
|
|
|
}
|
|
|
|
lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
|
2005-07-24 16:55:09 +04:00
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
|
2006-04-09 00:02:06 +04:00
|
|
|
pd = *lp;
|
2010-03-11 02:53:37 +03:00
|
|
|
if (pd == NULL) {
|
2006-04-09 00:02:06 +04:00
|
|
|
int i;
|
2011-12-13 14:52:08 +04:00
|
|
|
int first_index = index & ~(L2_SIZE - 1);
|
2010-03-11 02:53:37 +03:00
|
|
|
|
|
|
|
if (!alloc) {
|
2005-07-24 16:55:09 +04:00
|
|
|
return NULL;
|
2010-03-11 02:53:37 +03:00
|
|
|
}
|
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
*lp = pd = g_malloc(sizeof(PhysPageDesc) * L2_SIZE);
|
2010-03-11 02:53:37 +03:00
|
|
|
|
2009-02-23 16:16:07 +03:00
|
|
|
for (i = 0; i < L2_SIZE; i++) {
|
2012-01-02 02:32:15 +04:00
|
|
|
pd[i].phys_offset = io_mem_unassigned.ram_addr;
|
2011-12-13 14:52:08 +04:00
|
|
|
pd[i].region_offset = (first_index + i) << TARGET_PAGE_BITS;
|
2009-02-23 16:16:07 +03:00
|
|
|
}
|
2004-05-21 18:52:29 +04:00
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
|
|
|
|
return pd + (index & (L2_SIZE - 1));
|
2004-05-21 18:52:29 +04:00
|
|
|
}
|
|
|
|
|
2011-11-20 19:52:22 +04:00
|
|
|
static inline PhysPageDesc phys_page_find(target_phys_addr_t index)
|
2004-05-21 18:52:29 +04:00
|
|
|
{
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc *p = phys_page_find_alloc(index, 0);
|
|
|
|
|
|
|
|
if (p) {
|
|
|
|
return *p;
|
|
|
|
} else {
|
|
|
|
return (PhysPageDesc) {
|
2012-01-02 02:32:15 +04:00
|
|
|
.phys_offset = io_mem_unassigned.ram_addr,
|
2011-11-20 19:52:22 +04:00
|
|
|
.region_offset = index << TARGET_PAGE_BITS,
|
|
|
|
};
|
|
|
|
}
|
2004-05-21 18:52:29 +04:00
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static void tlb_protect_code(ram_addr_t ram_addr);
|
|
|
|
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
|
2005-08-21 13:26:42 +04:00
|
|
|
target_ulong vaddr);
|
2008-06-02 20:16:42 +04:00
|
|
|
#define mmap_lock() do { } while(0)
|
|
|
|
#define mmap_unlock() do { } while(0)
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
2003-05-14 23:00:11 +04:00
|
|
|
|
2008-05-29 13:35:57 +04:00
|
|
|
#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
|
|
|
|
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2009-05-03 15:15:06 +04:00
|
|
|
/* Currently it is not recommended to allocate big chunks of data in
|
2008-05-29 13:35:57 +04:00
|
|
|
user mode. It will change when a dedicated libc will be used */
|
|
|
|
#define USE_STATIC_CODE_GEN_BUFFER
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef USE_STATIC_CODE_GEN_BUFFER
|
2010-03-29 04:12:51 +04:00
|
|
|
static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]
|
|
|
|
__attribute__((aligned (CODE_GEN_ALIGN)));
|
2008-05-29 13:35:57 +04:00
|
|
|
#endif
|
|
|
|
|
2008-08-18 00:26:25 +04:00
|
|
|
static void code_gen_alloc(unsigned long tb_size)
|
2008-05-28 16:30:31 +04:00
|
|
|
{
|
2008-05-29 13:35:57 +04:00
|
|
|
#ifdef USE_STATIC_CODE_GEN_BUFFER
|
|
|
|
code_gen_buffer = static_code_gen_buffer;
|
|
|
|
code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
|
|
|
map_exec(code_gen_buffer, code_gen_buffer_size);
|
|
|
|
#else
|
2008-05-28 16:30:31 +04:00
|
|
|
code_gen_buffer_size = tb_size;
|
|
|
|
if (code_gen_buffer_size == 0) {
|
2008-05-29 13:35:57 +04:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
|
|
|
#else
|
2009-05-03 15:15:06 +04:00
|
|
|
/* XXX: needs adjustments */
|
2009-04-11 21:15:54 +04:00
|
|
|
code_gen_buffer_size = (unsigned long)(ram_size / 4);
|
2008-05-29 13:35:57 +04:00
|
|
|
#endif
|
2008-05-28 16:30:31 +04:00
|
|
|
}
|
|
|
|
if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
|
|
|
|
code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
|
|
|
|
/* The code gen buffer location may have constraints depending on
|
|
|
|
the host cpu and OS */
|
|
|
|
#if defined(__linux__)
|
|
|
|
{
|
|
|
|
int flags;
|
2008-07-26 19:05:57 +04:00
|
|
|
void *start = NULL;
|
|
|
|
|
2008-05-28 16:30:31 +04:00
|
|
|
flags = MAP_PRIVATE | MAP_ANONYMOUS;
|
|
|
|
#if defined(__x86_64__)
|
|
|
|
flags |= MAP_32BIT;
|
|
|
|
/* Cannot map more than that */
|
|
|
|
if (code_gen_buffer_size > (800 * 1024 * 1024))
|
|
|
|
code_gen_buffer_size = (800 * 1024 * 1024);
|
2008-07-26 19:05:57 +04:00
|
|
|
#elif defined(__sparc_v9__)
|
|
|
|
// Map the buffer below 2G, so we can use direct calls and branches
|
|
|
|
flags |= MAP_FIXED;
|
|
|
|
start = (void *) 0x60000000UL;
|
|
|
|
if (code_gen_buffer_size > (512 * 1024 * 1024))
|
|
|
|
code_gen_buffer_size = (512 * 1024 * 1024);
|
2008-12-01 05:10:17 +03:00
|
|
|
#elif defined(__arm__)
|
2012-01-08 00:00:25 +04:00
|
|
|
/* Keep the buffer no bigger than 16MB to branch between blocks */
|
2008-12-01 05:10:17 +03:00
|
|
|
if (code_gen_buffer_size > 16 * 1024 * 1024)
|
|
|
|
code_gen_buffer_size = 16 * 1024 * 1024;
|
2010-06-04 23:14:14 +04:00
|
|
|
#elif defined(__s390x__)
|
|
|
|
/* Map the buffer so that we can use direct calls and branches. */
|
|
|
|
/* We have a +- 4GB range on the branches; leave some slop. */
|
|
|
|
if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) {
|
|
|
|
code_gen_buffer_size = 3ul * 1024 * 1024 * 1024;
|
|
|
|
}
|
|
|
|
start = (void *)0x90000000UL;
|
2008-05-28 16:30:31 +04:00
|
|
|
#endif
|
2008-07-26 19:05:57 +04:00
|
|
|
code_gen_buffer = mmap(start, code_gen_buffer_size,
|
|
|
|
PROT_WRITE | PROT_READ | PROT_EXEC,
|
2008-05-28 16:30:31 +04:00
|
|
|
flags, -1, 0);
|
|
|
|
if (code_gen_buffer == MAP_FAILED) {
|
|
|
|
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2010-12-21 05:25:40 +03:00
|
|
|
#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
|
2011-08-07 13:57:05 +04:00
|
|
|
|| defined(__DragonFly__) || defined(__OpenBSD__) \
|
|
|
|
|| defined(__NetBSD__)
|
2008-09-27 19:32:41 +04:00
|
|
|
{
|
|
|
|
int flags;
|
|
|
|
void *addr = NULL;
|
|
|
|
flags = MAP_PRIVATE | MAP_ANONYMOUS;
|
|
|
|
#if defined(__x86_64__)
|
|
|
|
/* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
|
|
|
|
* 0x40000000 is free */
|
|
|
|
flags |= MAP_FIXED;
|
|
|
|
addr = (void *)0x40000000;
|
|
|
|
/* Cannot map more than that */
|
|
|
|
if (code_gen_buffer_size > (800 * 1024 * 1024))
|
|
|
|
code_gen_buffer_size = (800 * 1024 * 1024);
|
2011-01-16 11:32:27 +03:00
|
|
|
#elif defined(__sparc_v9__)
|
|
|
|
// Map the buffer below 2G, so we can use direct calls and branches
|
|
|
|
flags |= MAP_FIXED;
|
|
|
|
addr = (void *) 0x60000000UL;
|
|
|
|
if (code_gen_buffer_size > (512 * 1024 * 1024)) {
|
|
|
|
code_gen_buffer_size = (512 * 1024 * 1024);
|
|
|
|
}
|
2008-09-27 19:32:41 +04:00
|
|
|
#endif
|
|
|
|
code_gen_buffer = mmap(addr, code_gen_buffer_size,
|
|
|
|
PROT_WRITE | PROT_READ | PROT_EXEC,
|
|
|
|
flags, -1, 0);
|
|
|
|
if (code_gen_buffer == MAP_FAILED) {
|
|
|
|
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2008-05-28 16:30:31 +04:00
|
|
|
#else
|
2011-08-21 07:09:37 +04:00
|
|
|
code_gen_buffer = g_malloc(code_gen_buffer_size);
|
2008-05-28 16:30:31 +04:00
|
|
|
map_exec(code_gen_buffer, code_gen_buffer_size);
|
|
|
|
#endif
|
2008-05-29 13:35:57 +04:00
|
|
|
#endif /* !USE_STATIC_CODE_GEN_BUFFER */
|
2008-05-28 16:30:31 +04:00
|
|
|
map_exec(code_gen_prologue, sizeof(code_gen_prologue));
|
2011-06-22 14:58:25 +04:00
|
|
|
code_gen_buffer_max_size = code_gen_buffer_size -
|
|
|
|
(TCG_MAX_OP_SIZE * OPC_BUF_SIZE);
|
2008-05-28 16:30:31 +04:00
|
|
|
code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
|
2011-08-21 07:09:37 +04:00
|
|
|
tbs = g_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
|
2008-05-28 16:30:31 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Must be called before using the QEMU cpus. 'tb_size' is the size
|
|
|
|
(in bytes) allocated to the translation buffer. Zero means default
|
|
|
|
size. */
|
2011-08-02 18:10:21 +04:00
|
|
|
void tcg_exec_init(unsigned long tb_size)
|
2008-05-28 16:30:31 +04:00
|
|
|
{
|
|
|
|
cpu_gen_init();
|
|
|
|
code_gen_alloc(tb_size);
|
|
|
|
code_gen_ptr = code_gen_buffer;
|
2008-05-29 13:35:57 +04:00
|
|
|
page_init();
|
2010-05-06 19:50:41 +04:00
|
|
|
#if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE)
|
|
|
|
/* There's no guest base to take into account, so go ahead and
|
|
|
|
initialize the prologue now. */
|
|
|
|
tcg_prologue_init(&tcg_ctx);
|
|
|
|
#endif
|
2008-05-28 16:30:31 +04:00
|
|
|
}
|
|
|
|
|
2011-08-02 18:10:21 +04:00
|
|
|
bool tcg_enabled(void)
|
|
|
|
{
|
|
|
|
return code_gen_buffer != NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_exec_init_all(void)
|
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
memory_map_init();
|
|
|
|
io_mem_init();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2008-07-02 00:01:19 +04:00
|
|
|
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
|
|
|
|
2009-09-30 00:48:21 +04:00
|
|
|
static int cpu_common_post_load(void *opaque, int version_id)
|
2009-09-10 05:04:33 +04:00
|
|
|
{
|
|
|
|
CPUState *env = opaque;
|
2008-07-02 00:01:19 +04:00
|
|
|
|
2009-03-08 00:28:24 +03:00
|
|
|
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
|
|
|
|
version_id is increased. */
|
|
|
|
env->interrupt_request &= ~0x01;
|
2008-07-02 00:01:19 +04:00
|
|
|
tlb_flush(env, 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2009-09-10 05:04:33 +04:00
|
|
|
|
|
|
|
static const VMStateDescription vmstate_cpu_common = {
|
|
|
|
.name = "cpu_common",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.post_load = cpu_common_post_load,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_UINT32(halted, CPUState),
|
|
|
|
VMSTATE_UINT32(interrupt_request, CPUState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-07-02 00:01:19 +04:00
|
|
|
#endif
|
|
|
|
|
2009-06-09 20:15:18 +04:00
|
|
|
CPUState *qemu_get_cpu(int cpu)
|
|
|
|
{
|
|
|
|
CPUState *env = first_cpu;
|
|
|
|
|
|
|
|
while (env) {
|
|
|
|
if (env->cpu_index == cpu)
|
|
|
|
break;
|
|
|
|
env = env->next_cpu;
|
|
|
|
}
|
|
|
|
|
|
|
|
return env;
|
|
|
|
}
|
|
|
|
|
2005-11-22 02:25:50 +03:00
|
|
|
void cpu_exec_init(CPUState *env)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
2005-11-22 02:25:50 +03:00
|
|
|
CPUState **penv;
|
|
|
|
int cpu_index;
|
|
|
|
|
2009-03-07 18:24:59 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
cpu_list_lock();
|
|
|
|
#endif
|
2005-11-22 02:25:50 +03:00
|
|
|
env->next_cpu = NULL;
|
|
|
|
penv = &first_cpu;
|
|
|
|
cpu_index = 0;
|
|
|
|
while (*penv != NULL) {
|
2009-06-03 22:33:08 +04:00
|
|
|
penv = &(*penv)->next_cpu;
|
2005-11-22 02:25:50 +03:00
|
|
|
cpu_index++;
|
|
|
|
}
|
|
|
|
env->cpu_index = cpu_index;
|
2009-04-22 02:30:27 +04:00
|
|
|
env->numa_node = 0;
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_INIT(&env->breakpoints);
|
|
|
|
QTAILQ_INIT(&env->watchpoints);
|
2011-03-15 14:26:31 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
env->thread_id = qemu_get_thread_id();
|
|
|
|
#endif
|
2005-11-22 02:25:50 +03:00
|
|
|
*penv = env;
|
2009-03-07 18:24:59 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
cpu_list_unlock();
|
|
|
|
#endif
|
2008-06-30 20:31:04 +04:00
|
|
|
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
2010-06-25 21:09:07 +04:00
|
|
|
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
|
|
|
|
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
|
2008-06-30 20:31:04 +04:00
|
|
|
cpu_save, cpu_load, env);
|
|
|
|
#endif
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
|
2011-02-10 12:04:57 +03:00
|
|
|
/* Allocate a new translation block. Flush the translation buffer if
|
|
|
|
too many translation blocks or too much generated code. */
|
|
|
|
static TranslationBlock *tb_alloc(target_ulong pc)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
|
|
|
|
if (nb_tbs >= code_gen_max_blocks ||
|
|
|
|
(code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
|
|
|
|
return NULL;
|
|
|
|
tb = &tbs[nb_tbs++];
|
|
|
|
tb->pc = pc;
|
|
|
|
tb->cflags = 0;
|
|
|
|
return tb;
|
|
|
|
}
|
|
|
|
|
|
|
|
void tb_free(TranslationBlock *tb)
|
|
|
|
{
|
|
|
|
/* In practice this is mostly used for single use temporary TB
|
|
|
|
Ignore the hard cases and just back up if this TB happens to
|
|
|
|
be the last one generated. */
|
|
|
|
if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
|
|
|
|
code_gen_ptr = tb->tc_ptr;
|
|
|
|
nb_tbs--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
static inline void invalidate_page_bitmap(PageDesc *p)
|
|
|
|
{
|
|
|
|
if (p->code_bitmap) {
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(p->code_bitmap);
|
2004-01-04 21:06:42 +03:00
|
|
|
p->code_bitmap = NULL;
|
|
|
|
}
|
|
|
|
p->code_write_count = 0;
|
|
|
|
}
|
|
|
|
|
2010-03-11 02:53:37 +03:00
|
|
|
/* Set to NULL all the 'first_tb' fields in all PageDescs. */
|
|
|
|
|
|
|
|
static void page_flush_tb_1 (int level, void **lp)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
2010-03-11 02:53:37 +03:00
|
|
|
int i;
|
2003-05-14 23:00:11 +04:00
|
|
|
|
2010-03-11 02:53:37 +03:00
|
|
|
if (*lp == NULL) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (level == 0) {
|
|
|
|
PageDesc *pd = *lp;
|
2010-03-14 17:58:46 +03:00
|
|
|
for (i = 0; i < L2_SIZE; ++i) {
|
2010-03-11 02:53:37 +03:00
|
|
|
pd[i].first_tb = NULL;
|
|
|
|
invalidate_page_bitmap(pd + i);
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
} else {
|
|
|
|
void **pp = *lp;
|
2010-03-14 17:58:46 +03:00
|
|
|
for (i = 0; i < L2_SIZE; ++i) {
|
2010-03-11 02:53:37 +03:00
|
|
|
page_flush_tb_1 (level - 1, pp + i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void page_flush_tb(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < V_L1_SIZE; i++) {
|
|
|
|
page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i);
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* flush all the translation blocks */
|
2003-05-25 20:46:15 +04:00
|
|
|
/* XXX: tb_flush is currently not thread safe */
|
2005-11-22 02:25:50 +03:00
|
|
|
void tb_flush(CPUState *env1)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
2005-11-22 02:25:50 +03:00
|
|
|
CPUState *env;
|
2004-01-04 18:48:17 +03:00
|
|
|
#if defined(DEBUG_FLUSH)
|
2007-11-04 10:31:40 +03:00
|
|
|
printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
|
|
|
|
(unsigned long)(code_gen_ptr - code_gen_buffer),
|
|
|
|
nb_tbs, nb_tbs > 0 ?
|
|
|
|
((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
|
2003-05-14 23:00:11 +04:00
|
|
|
#endif
|
2008-05-28 16:30:31 +04:00
|
|
|
if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
|
2008-03-31 21:07:36 +04:00
|
|
|
cpu_abort(env1, "Internal error: code buffer overflow\n");
|
|
|
|
|
2003-05-14 23:00:11 +04:00
|
|
|
nb_tbs = 0;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2005-11-22 02:25:50 +03:00
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
|
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2004-10-03 17:36:49 +04:00
|
|
|
memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
|
2003-05-14 23:00:11 +04:00
|
|
|
page_flush_tb();
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2003-05-14 23:00:11 +04:00
|
|
|
code_gen_ptr = code_gen_buffer;
|
2003-05-25 20:46:15 +04:00
|
|
|
/* XXX: flush processor icache at this point if cache flush is
|
|
|
|
expensive */
|
2005-01-27 01:00:47 +03:00
|
|
|
tb_flush_count++;
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG_TB_CHECK
|
|
|
|
|
2007-04-04 11:55:12 +04:00
|
|
|
static void tb_invalidate_check(target_ulong address)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int i;
|
|
|
|
address &= TARGET_PAGE_MASK;
|
2006-04-16 19:14:59 +04:00
|
|
|
for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
|
|
|
|
for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
|
2003-05-14 23:00:11 +04:00
|
|
|
if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
|
|
|
|
address >= tb->pc + tb->size)) {
|
2009-07-20 21:19:25 +04:00
|
|
|
printf("ERROR invalidate: address=" TARGET_FMT_lx
|
|
|
|
" PC=%08lx size=%04x\n",
|
2006-04-16 19:14:59 +04:00
|
|
|
address, (long)tb->pc, tb->size);
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* verify that all the pages have correct rights for code */
|
|
|
|
static void tb_page_check(void)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int i, flags1, flags2;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2006-04-16 19:14:59 +04:00
|
|
|
for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
|
|
|
|
for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
|
2003-05-14 23:00:11 +04:00
|
|
|
flags1 = page_get_flags(tb->pc);
|
|
|
|
flags2 = page_get_flags(tb->pc + tb->size - 1);
|
|
|
|
if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
|
|
|
|
printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
|
2006-04-16 19:14:59 +04:00
|
|
|
(long)tb->pc, tb->size, flags1, flags2);
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* invalidate one TB */
|
|
|
|
static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
|
|
|
|
int next_offset)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1;
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
if (tb1 == tb) {
|
|
|
|
*ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ptb = (TranslationBlock **)((char *)tb1 + next_offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (tb1 == tb) {
|
|
|
|
*ptb = tb1->page_next[n1];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ptb = &tb1->page_next[n1];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-05-25 20:46:15 +04:00
|
|
|
static inline void tb_jmp_remove(TranslationBlock *tb, int n)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1, **ptb;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
ptb = &tb->jmp_next[n];
|
|
|
|
tb1 = *ptb;
|
|
|
|
if (tb1) {
|
|
|
|
/* find tb(n) in circular list */
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == n && tb1 == tb)
|
|
|
|
break;
|
|
|
|
if (n1 == 2) {
|
|
|
|
ptb = &tb1->jmp_first;
|
|
|
|
} else {
|
|
|
|
ptb = &tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* now we can suppress tb(n) from the list */
|
|
|
|
*ptb = tb->jmp_next[n];
|
|
|
|
|
|
|
|
tb->jmp_next[n] = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* reset the jump entry 'n' of a TB so that it is not chained to
|
|
|
|
another TB */
|
|
|
|
static inline void tb_reset_jump(TranslationBlock *tb, int n)
|
|
|
|
{
|
|
|
|
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
|
|
|
|
}
|
|
|
|
|
2010-03-12 19:54:58 +03:00
|
|
|
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
2005-11-22 02:25:50 +03:00
|
|
|
CPUState *env;
|
2005-11-20 13:35:40 +03:00
|
|
|
PageDesc *p;
|
2003-05-25 20:46:15 +04:00
|
|
|
unsigned int h, n1;
|
2010-03-12 19:54:58 +03:00
|
|
|
tb_page_addr_t phys_pc;
|
2005-11-20 13:35:40 +03:00
|
|
|
TranslationBlock *tb1, *tb2;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2005-11-20 13:35:40 +03:00
|
|
|
/* remove the TB from the hash list */
|
|
|
|
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
|
|
|
|
h = tb_phys_hash_func(phys_pc);
|
2007-09-17 01:08:06 +04:00
|
|
|
tb_remove(&tb_phys_hash[h], tb,
|
2005-11-20 13:35:40 +03:00
|
|
|
offsetof(TranslationBlock, phys_hash_next));
|
|
|
|
|
|
|
|
/* remove the TB from the page list */
|
|
|
|
if (tb->page_addr[0] != page_addr) {
|
|
|
|
p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
|
|
|
|
tb_page_remove(&p->first_tb, tb);
|
|
|
|
invalidate_page_bitmap(p);
|
|
|
|
}
|
|
|
|
if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
|
|
|
|
p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
|
|
|
|
tb_page_remove(&p->first_tb, tb);
|
|
|
|
invalidate_page_bitmap(p);
|
|
|
|
}
|
|
|
|
|
2003-11-20 01:12:02 +03:00
|
|
|
tb_invalidated_flag = 1;
|
2004-02-17 01:01:13 +03:00
|
|
|
|
2003-05-14 23:00:11 +04:00
|
|
|
/* remove the TB from the hash list */
|
2005-11-20 13:35:40 +03:00
|
|
|
h = tb_jmp_cache_hash_func(tb->pc);
|
2005-11-22 02:25:50 +03:00
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
if (env->tb_jmp_cache[h] == tb)
|
|
|
|
env->tb_jmp_cache[h] = NULL;
|
|
|
|
}
|
2003-05-25 20:46:15 +04:00
|
|
|
|
|
|
|
/* suppress this TB from the two jump lists */
|
|
|
|
tb_jmp_remove(tb, 0);
|
|
|
|
tb_jmp_remove(tb, 1);
|
|
|
|
|
|
|
|
/* suppress any remaining jumps to this TB */
|
|
|
|
tb1 = tb->jmp_first;
|
|
|
|
for(;;) {
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
if (n1 == 2)
|
|
|
|
break;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
tb2 = tb1->jmp_next[n1];
|
|
|
|
tb_reset_jump(tb1, n1);
|
|
|
|
tb1->jmp_next[n1] = NULL;
|
|
|
|
tb1 = tb2;
|
|
|
|
}
|
|
|
|
tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2005-01-27 01:00:47 +03:00
|
|
|
tb_phys_invalidate_count++;
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void set_bits(uint8_t *tab, int start, int len)
|
|
|
|
{
|
|
|
|
int end, mask, end1;
|
|
|
|
|
|
|
|
end = start + len;
|
|
|
|
tab += start >> 3;
|
|
|
|
mask = 0xff << (start & 7);
|
|
|
|
if ((start & ~7) == (end & ~7)) {
|
|
|
|
if (start < end) {
|
|
|
|
mask &= ~(0xff << (end & 7));
|
|
|
|
*tab |= mask;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
*tab++ |= mask;
|
|
|
|
start = (start + 8) & ~7;
|
|
|
|
end1 = end & ~7;
|
|
|
|
while (start < end1) {
|
|
|
|
*tab++ = 0xff;
|
|
|
|
start += 8;
|
|
|
|
}
|
|
|
|
if (start < end) {
|
|
|
|
mask = ~(0xff << (end & 7));
|
|
|
|
*tab |= mask;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void build_page_bitmap(PageDesc *p)
|
|
|
|
{
|
|
|
|
int n, tb_start, tb_end;
|
|
|
|
TranslationBlock *tb;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
p->code_bitmap = g_malloc0(TARGET_PAGE_SIZE / 8);
|
2004-01-04 21:06:42 +03:00
|
|
|
|
|
|
|
tb = p->first_tb;
|
|
|
|
while (tb != NULL) {
|
|
|
|
n = (long)tb & 3;
|
|
|
|
tb = (TranslationBlock *)((long)tb & ~3);
|
|
|
|
/* NOTE: this is subtle as a TB may span two physical pages */
|
|
|
|
if (n == 0) {
|
|
|
|
/* NOTE: tb_end may be after the end of the page, but
|
|
|
|
it is not a problem */
|
|
|
|
tb_start = tb->pc & ~TARGET_PAGE_MASK;
|
|
|
|
tb_end = tb_start + tb->size;
|
|
|
|
if (tb_end > TARGET_PAGE_SIZE)
|
|
|
|
tb_end = TARGET_PAGE_SIZE;
|
|
|
|
} else {
|
|
|
|
tb_start = 0;
|
|
|
|
tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
|
|
|
|
}
|
|
|
|
set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
|
|
|
|
tb = tb->page_next[n];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-06-29 05:03:05 +04:00
|
|
|
TranslationBlock *tb_gen_code(CPUState *env,
|
|
|
|
target_ulong pc, target_ulong cs_base,
|
|
|
|
int flags, int cflags)
|
2004-04-25 21:57:43 +04:00
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
uint8_t *tc_ptr;
|
2010-03-12 19:54:58 +03:00
|
|
|
tb_page_addr_t phys_pc, phys_page2;
|
|
|
|
target_ulong virt_page2;
|
2004-04-25 21:57:43 +04:00
|
|
|
int code_gen_size;
|
|
|
|
|
2010-03-12 19:54:58 +03:00
|
|
|
phys_pc = get_page_addr_code(env, pc);
|
2005-01-04 02:35:10 +03:00
|
|
|
tb = tb_alloc(pc);
|
2004-04-25 21:57:43 +04:00
|
|
|
if (!tb) {
|
|
|
|
/* flush must be done */
|
|
|
|
tb_flush(env);
|
|
|
|
/* cannot fail at this point */
|
2005-01-04 02:35:10 +03:00
|
|
|
tb = tb_alloc(pc);
|
2008-06-29 05:03:05 +04:00
|
|
|
/* Don't forget to invalidate previous TB info. */
|
|
|
|
tb_invalidated_flag = 1;
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
|
|
|
tc_ptr = code_gen_ptr;
|
|
|
|
tb->tc_ptr = tc_ptr;
|
|
|
|
tb->cs_base = cs_base;
|
|
|
|
tb->flags = flags;
|
|
|
|
tb->cflags = cflags;
|
2007-12-11 22:35:45 +03:00
|
|
|
cpu_gen_code(env, tb, &code_gen_size);
|
2004-04-25 21:57:43 +04:00
|
|
|
code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-04-25 21:57:43 +04:00
|
|
|
/* check next page if needed */
|
2005-01-04 02:35:10 +03:00
|
|
|
virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
2004-04-25 21:57:43 +04:00
|
|
|
phys_page2 = -1;
|
2005-01-04 02:35:10 +03:00
|
|
|
if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
2010-03-12 19:54:58 +03:00
|
|
|
phys_page2 = get_page_addr_code(env, virt_page2);
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
2010-03-12 19:54:58 +03:00
|
|
|
tb_link_page(tb, phys_pc, phys_page2);
|
2008-06-29 05:03:05 +04:00
|
|
|
return tb;
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* invalidate all TBs which intersect with the target physical page
|
|
|
|
starting in range [start;end[. NOTE: start and end must refer to
|
2004-04-25 21:57:43 +04:00
|
|
|
the same physical page. 'is_cpu_write_access' should be true if called
|
|
|
|
from a real cpu write access: the virtual CPU will exit the current
|
|
|
|
TB if code is modified inside this TB. */
|
2010-03-12 19:54:58 +03:00
|
|
|
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
|
2004-04-25 21:57:43 +04:00
|
|
|
int is_cpu_write_access)
|
|
|
|
{
|
2008-11-18 22:46:41 +03:00
|
|
|
TranslationBlock *tb, *tb_next, *saved_tb;
|
2004-04-25 21:57:43 +04:00
|
|
|
CPUState *env = cpu_single_env;
|
2010-03-12 19:54:58 +03:00
|
|
|
tb_page_addr_t tb_start, tb_end;
|
2008-11-18 22:46:41 +03:00
|
|
|
PageDesc *p;
|
|
|
|
int n;
|
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
int current_tb_not_found = is_cpu_write_access;
|
|
|
|
TranslationBlock *current_tb = NULL;
|
|
|
|
int current_tb_modified = 0;
|
|
|
|
target_ulong current_pc = 0;
|
|
|
|
target_ulong current_cs_base = 0;
|
|
|
|
int current_flags = 0;
|
|
|
|
#endif /* TARGET_HAS_PRECISE_SMC */
|
2004-01-04 21:06:42 +03:00
|
|
|
|
|
|
|
p = page_find(start >> TARGET_PAGE_BITS);
|
2007-09-17 01:08:06 +04:00
|
|
|
if (!p)
|
2004-01-04 21:06:42 +03:00
|
|
|
return;
|
2007-09-17 01:08:06 +04:00
|
|
|
if (!p->code_bitmap &&
|
2004-04-25 21:57:43 +04:00
|
|
|
++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
|
|
|
|
is_cpu_write_access) {
|
2004-01-04 21:06:42 +03:00
|
|
|
/* build code bitmap */
|
|
|
|
build_page_bitmap(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we remove all the TBs in the range [start, end[ */
|
|
|
|
/* XXX: see if in some cases it could be faster to invalidate all the code */
|
|
|
|
tb = p->first_tb;
|
|
|
|
while (tb != NULL) {
|
|
|
|
n = (long)tb & 3;
|
|
|
|
tb = (TranslationBlock *)((long)tb & ~3);
|
|
|
|
tb_next = tb->page_next[n];
|
|
|
|
/* NOTE: this is subtle as a TB may span two physical pages */
|
|
|
|
if (n == 0) {
|
|
|
|
/* NOTE: tb_end may be after the end of the page, but
|
|
|
|
it is not a problem */
|
|
|
|
tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
|
|
|
|
tb_end = tb_start + tb->size;
|
|
|
|
} else {
|
|
|
|
tb_start = tb->page_addr[1];
|
|
|
|
tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
|
|
|
|
}
|
|
|
|
if (!(tb_end <= start || tb_start >= end)) {
|
2004-04-25 21:57:43 +04:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb_not_found) {
|
|
|
|
current_tb_not_found = 0;
|
|
|
|
current_tb = NULL;
|
2008-06-29 05:03:05 +04:00
|
|
|
if (env->mem_io_pc) {
|
2004-04-25 21:57:43 +04:00
|
|
|
/* now we have a real cpu fault */
|
2008-06-29 05:03:05 +04:00
|
|
|
current_tb = tb_find_pc(env->mem_io_pc);
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (current_tb == tb &&
|
2008-06-29 05:03:05 +04:00
|
|
|
(current_tb->cflags & CF_COUNT_MASK) != 1) {
|
2004-04-25 21:57:43 +04:00
|
|
|
/* If we are modifying the current TB, we must stop
|
|
|
|
its execution. We could be more precise by checking
|
|
|
|
that the modification is after the current PC, but it
|
|
|
|
would require a specialized function to partially
|
|
|
|
restore the CPU state */
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-04-25 21:57:43 +04:00
|
|
|
current_tb_modified = 1;
|
2011-04-18 10:39:53 +04:00
|
|
|
cpu_restore_state(current_tb, env, env->mem_io_pc);
|
2008-11-18 22:46:41 +03:00
|
|
|
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
|
|
|
|
¤t_flags);
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
|
|
|
#endif /* TARGET_HAS_PRECISE_SMC */
|
2005-11-26 23:12:28 +03:00
|
|
|
/* we need to do that to handle the case where a signal
|
|
|
|
occurs while doing tb_phys_invalidate() */
|
|
|
|
saved_tb = NULL;
|
|
|
|
if (env) {
|
|
|
|
saved_tb = env->current_tb;
|
|
|
|
env->current_tb = NULL;
|
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
tb_phys_invalidate(tb, -1);
|
2005-11-26 23:12:28 +03:00
|
|
|
if (env) {
|
|
|
|
env->current_tb = saved_tb;
|
|
|
|
if (env->interrupt_request && env->current_tb)
|
|
|
|
cpu_interrupt(env, env->interrupt_request);
|
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
tb = tb_next;
|
|
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* if no code remaining, no need to continue to use slow writes */
|
|
|
|
if (!p->first_tb) {
|
|
|
|
invalidate_page_bitmap(p);
|
2004-04-25 21:57:43 +04:00
|
|
|
if (is_cpu_write_access) {
|
2008-06-29 05:03:05 +04:00
|
|
|
tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb_modified) {
|
|
|
|
/* we generate a block containing just the instruction
|
|
|
|
modifying the memory. It will ensure that it cannot modify
|
|
|
|
itself */
|
2004-06-14 22:56:36 +04:00
|
|
|
env->current_tb = NULL;
|
2008-06-29 05:03:05 +04:00
|
|
|
tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
|
2004-04-25 21:57:43 +04:00
|
|
|
cpu_resume_from_signal(env, NULL);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
2003-05-14 23:00:11 +04:00
|
|
|
#endif
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
2003-05-14 23:00:11 +04:00
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* len must be <= 8 and start must be a multiple of len */
|
2010-03-12 19:54:58 +03:00
|
|
|
static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
|
|
|
PageDesc *p;
|
|
|
|
int offset, b;
|
2004-02-17 01:01:13 +03:00
|
|
|
#if 0
|
2004-06-03 18:01:43 +04:00
|
|
|
if (1) {
|
2009-01-16 01:34:14 +03:00
|
|
|
qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
|
|
|
|
cpu_single_env->mem_io_vaddr, len,
|
|
|
|
cpu_single_env->eip,
|
|
|
|
cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
|
2004-02-17 01:01:13 +03:00
|
|
|
}
|
|
|
|
#endif
|
2004-01-04 21:06:42 +03:00
|
|
|
p = page_find(start >> TARGET_PAGE_BITS);
|
2007-09-17 01:08:06 +04:00
|
|
|
if (!p)
|
2004-01-04 21:06:42 +03:00
|
|
|
return;
|
|
|
|
if (p->code_bitmap) {
|
|
|
|
offset = start & ~TARGET_PAGE_MASK;
|
|
|
|
b = p->code_bitmap[offset >> 3] >> (offset & 7);
|
|
|
|
if (b & ((1 << len) - 1))
|
|
|
|
goto do_invalidate;
|
|
|
|
} else {
|
|
|
|
do_invalidate:
|
2004-04-25 21:57:43 +04:00
|
|
|
tb_invalidate_phys_page_range(start, start + len, 1);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
2010-03-12 19:54:58 +03:00
|
|
|
static void tb_invalidate_phys_page(tb_page_addr_t addr,
|
2004-04-25 21:57:43 +04:00
|
|
|
unsigned long pc, void *puc)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2008-11-18 22:46:41 +03:00
|
|
|
TranslationBlock *tb;
|
2004-01-04 21:06:42 +03:00
|
|
|
PageDesc *p;
|
2008-11-18 22:46:41 +03:00
|
|
|
int n;
|
2004-04-25 21:57:43 +04:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
2008-11-18 22:46:41 +03:00
|
|
|
TranslationBlock *current_tb = NULL;
|
2004-04-25 21:57:43 +04:00
|
|
|
CPUState *env = cpu_single_env;
|
2008-11-18 22:46:41 +03:00
|
|
|
int current_tb_modified = 0;
|
|
|
|
target_ulong current_pc = 0;
|
|
|
|
target_ulong current_cs_base = 0;
|
|
|
|
int current_flags = 0;
|
2004-04-25 21:57:43 +04:00
|
|
|
#endif
|
2004-01-04 21:06:42 +03:00
|
|
|
|
|
|
|
addr &= TARGET_PAGE_MASK;
|
|
|
|
p = page_find(addr >> TARGET_PAGE_BITS);
|
2007-09-17 01:08:06 +04:00
|
|
|
if (!p)
|
2004-01-04 21:06:42 +03:00
|
|
|
return;
|
|
|
|
tb = p->first_tb;
|
2004-04-25 21:57:43 +04:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (tb && pc != 0) {
|
|
|
|
current_tb = tb_find_pc(pc);
|
|
|
|
}
|
|
|
|
#endif
|
2004-01-04 21:06:42 +03:00
|
|
|
while (tb != NULL) {
|
|
|
|
n = (long)tb & 3;
|
|
|
|
tb = (TranslationBlock *)((long)tb & ~3);
|
2004-04-25 21:57:43 +04:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb == tb &&
|
2008-06-29 05:03:05 +04:00
|
|
|
(current_tb->cflags & CF_COUNT_MASK) != 1) {
|
2004-04-25 21:57:43 +04:00
|
|
|
/* If we are modifying the current TB, we must stop
|
|
|
|
its execution. We could be more precise by checking
|
|
|
|
that the modification is after the current PC, but it
|
|
|
|
would require a specialized function to partially
|
|
|
|
restore the CPU state */
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-04-25 21:57:43 +04:00
|
|
|
current_tb_modified = 1;
|
2011-04-18 10:39:53 +04:00
|
|
|
cpu_restore_state(current_tb, env, pc);
|
2008-11-18 22:46:41 +03:00
|
|
|
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
|
|
|
|
¤t_flags);
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
|
|
|
#endif /* TARGET_HAS_PRECISE_SMC */
|
2004-01-04 21:06:42 +03:00
|
|
|
tb_phys_invalidate(tb, addr);
|
|
|
|
tb = tb->page_next[n];
|
|
|
|
}
|
2003-05-14 23:00:11 +04:00
|
|
|
p->first_tb = NULL;
|
2004-04-25 21:57:43 +04:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb_modified) {
|
|
|
|
/* we generate a block containing just the instruction
|
|
|
|
modifying the memory. It will ensure that it cannot modify
|
|
|
|
itself */
|
2004-06-14 22:56:36 +04:00
|
|
|
env->current_tb = NULL;
|
2008-06-29 05:03:05 +04:00
|
|
|
tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
|
2004-04-25 21:57:43 +04:00
|
|
|
cpu_resume_from_signal(env, puc);
|
|
|
|
}
|
|
|
|
#endif
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
2003-05-14 23:00:11 +04:00
|
|
|
|
|
|
|
/* add the tb in the target page and protect it if necessary */
|
2007-09-17 01:08:06 +04:00
|
|
|
static inline void tb_alloc_page(TranslationBlock *tb,
|
2010-03-12 19:54:58 +03:00
|
|
|
unsigned int n, tb_page_addr_t page_addr)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
|
|
|
PageDesc *p;
|
2011-06-02 05:53:44 +04:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
bool page_already_protected;
|
|
|
|
#endif
|
2004-01-04 21:06:42 +03:00
|
|
|
|
|
|
|
tb->page_addr[n] = page_addr;
|
2010-03-11 02:53:37 +03:00
|
|
|
p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1);
|
2004-01-04 21:06:42 +03:00
|
|
|
tb->page_next[n] = p->first_tb;
|
2011-06-02 05:53:44 +04:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
page_already_protected = p->first_tb != NULL;
|
|
|
|
#endif
|
2004-01-04 21:06:42 +03:00
|
|
|
p->first_tb = (TranslationBlock *)((long)tb | n);
|
|
|
|
invalidate_page_bitmap(p);
|
2003-05-14 23:00:11 +04:00
|
|
|
|
2004-06-22 22:48:46 +04:00
|
|
|
#if defined(TARGET_HAS_SMC) || 1
|
2004-04-25 21:57:43 +04:00
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2003-05-14 23:00:11 +04:00
|
|
|
if (p->flags & PAGE_WRITE) {
|
2006-03-25 22:31:22 +03:00
|
|
|
target_ulong addr;
|
|
|
|
PageDesc *p2;
|
2004-01-04 21:06:42 +03:00
|
|
|
int prot;
|
|
|
|
|
2003-05-14 23:00:11 +04:00
|
|
|
/* force the host page as non writable (writes will have a
|
|
|
|
page fault + mprotect overhead) */
|
2006-03-25 22:31:22 +03:00
|
|
|
page_addr &= qemu_host_page_mask;
|
2003-05-14 23:00:11 +04:00
|
|
|
prot = 0;
|
2006-03-25 22:31:22 +03:00
|
|
|
for(addr = page_addr; addr < page_addr + qemu_host_page_size;
|
|
|
|
addr += TARGET_PAGE_SIZE) {
|
|
|
|
|
|
|
|
p2 = page_find (addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p2)
|
|
|
|
continue;
|
|
|
|
prot |= p2->flags;
|
|
|
|
p2->flags &= ~PAGE_WRITE;
|
|
|
|
}
|
2007-09-17 01:08:06 +04:00
|
|
|
mprotect(g2h(page_addr), qemu_host_page_size,
|
2003-05-14 23:00:11 +04:00
|
|
|
(prot & PAGE_BITS) & ~PAGE_WRITE);
|
|
|
|
#ifdef DEBUG_TB_INVALIDATE
|
2007-11-04 10:31:40 +03:00
|
|
|
printf("protecting code page: 0x" TARGET_FMT_lx "\n",
|
2006-03-25 22:31:22 +03:00
|
|
|
page_addr);
|
2003-05-14 23:00:11 +04:00
|
|
|
#endif
|
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
#else
|
|
|
|
/* if some code is already present, then the pages are already
|
|
|
|
protected. So we handle the case where only the first TB is
|
|
|
|
allocated in a physical page */
|
2011-06-02 05:53:44 +04:00
|
|
|
if (!page_already_protected) {
|
2005-11-22 02:25:50 +03:00
|
|
|
tlb_protect_code(page_addr);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
#endif
|
2004-04-25 21:57:43 +04:00
|
|
|
|
|
|
|
#endif /* TARGET_HAS_SMC */
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* add a new TB and link it to the physical page tables. phys_page2 is
|
|
|
|
(-1) to indicate that only one page contains the TB. */
|
2010-03-12 19:54:58 +03:00
|
|
|
void tb_link_page(TranslationBlock *tb,
|
|
|
|
tb_page_addr_t phys_pc, tb_page_addr_t phys_page2)
|
2003-05-25 20:46:15 +04:00
|
|
|
{
|
2004-01-04 21:06:42 +03:00
|
|
|
unsigned int h;
|
|
|
|
TranslationBlock **ptb;
|
|
|
|
|
2008-06-02 20:16:42 +04:00
|
|
|
/* Grab the mmap lock to stop another thread invalidating this TB
|
|
|
|
before we are done. */
|
|
|
|
mmap_lock();
|
2004-01-04 21:06:42 +03:00
|
|
|
/* add in the physical hash table */
|
|
|
|
h = tb_phys_hash_func(phys_pc);
|
|
|
|
ptb = &tb_phys_hash[h];
|
|
|
|
tb->phys_hash_next = *ptb;
|
|
|
|
*ptb = tb;
|
2003-05-14 23:00:11 +04:00
|
|
|
|
|
|
|
/* add in the page list */
|
2004-01-04 21:06:42 +03:00
|
|
|
tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
|
|
|
|
if (phys_page2 != -1)
|
|
|
|
tb_alloc_page(tb, 1, phys_page2);
|
|
|
|
else
|
|
|
|
tb->page_addr[1] = -1;
|
|
|
|
|
2003-05-25 20:46:15 +04:00
|
|
|
tb->jmp_first = (TranslationBlock *)((long)tb | 2);
|
|
|
|
tb->jmp_next[0] = NULL;
|
|
|
|
tb->jmp_next[1] = NULL;
|
|
|
|
|
|
|
|
/* init original jump addresses */
|
|
|
|
if (tb->tb_next_offset[0] != 0xffff)
|
|
|
|
tb_reset_jump(tb, 0);
|
|
|
|
if (tb->tb_next_offset[1] != 0xffff)
|
|
|
|
tb_reset_jump(tb, 1);
|
2005-11-20 13:35:40 +03:00
|
|
|
|
|
|
|
#ifdef DEBUG_TB_CHECK
|
|
|
|
tb_page_check();
|
|
|
|
#endif
|
2008-06-02 20:16:42 +04:00
|
|
|
mmap_unlock();
|
2003-05-14 23:00:11 +04:00
|
|
|
}
|
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
|
|
|
|
tb[1].tc_ptr. Return NULL if not found */
|
|
|
|
TranslationBlock *tb_find_pc(unsigned long tc_ptr)
|
2003-05-14 23:00:11 +04:00
|
|
|
{
|
2004-01-04 21:06:42 +03:00
|
|
|
int m_min, m_max, m;
|
|
|
|
unsigned long v;
|
|
|
|
TranslationBlock *tb;
|
2003-05-28 03:29:48 +04:00
|
|
|
|
|
|
|
if (nb_tbs <= 0)
|
|
|
|
return NULL;
|
|
|
|
if (tc_ptr < (unsigned long)code_gen_buffer ||
|
|
|
|
tc_ptr >= (unsigned long)code_gen_ptr)
|
|
|
|
return NULL;
|
|
|
|
/* binary search (cf Knuth) */
|
|
|
|
m_min = 0;
|
|
|
|
m_max = nb_tbs - 1;
|
|
|
|
while (m_min <= m_max) {
|
|
|
|
m = (m_min + m_max) >> 1;
|
|
|
|
tb = &tbs[m];
|
|
|
|
v = (unsigned long)tb->tc_ptr;
|
|
|
|
if (v == tc_ptr)
|
|
|
|
return tb;
|
|
|
|
else if (tc_ptr < v) {
|
|
|
|
m_max = m - 1;
|
|
|
|
} else {
|
|
|
|
m_min = m + 1;
|
|
|
|
}
|
2007-09-17 01:08:06 +04:00
|
|
|
}
|
2003-05-28 03:29:48 +04:00
|
|
|
return &tbs[m_max];
|
|
|
|
}
|
2003-06-21 17:11:07 +04:00
|
|
|
|
2003-06-25 20:16:50 +04:00
|
|
|
static void tb_reset_jump_recursive(TranslationBlock *tb);
|
|
|
|
|
|
|
|
static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1, *tb_next, **ptb;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
tb1 = tb->jmp_next[n];
|
|
|
|
if (tb1 != NULL) {
|
|
|
|
/* find head of list */
|
|
|
|
for(;;) {
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == 2)
|
|
|
|
break;
|
|
|
|
tb1 = tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
/* we are now sure now that tb jumps to tb1 */
|
|
|
|
tb_next = tb1;
|
|
|
|
|
|
|
|
/* remove tb from the jmp_first list */
|
|
|
|
ptb = &tb_next->jmp_first;
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == n && tb1 == tb)
|
|
|
|
break;
|
|
|
|
ptb = &tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
*ptb = tb->jmp_next[n];
|
|
|
|
tb->jmp_next[n] = NULL;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2003-06-25 20:16:50 +04:00
|
|
|
/* suppress the jump to next tb in generated code */
|
|
|
|
tb_reset_jump(tb, n);
|
|
|
|
|
2004-01-04 18:48:17 +03:00
|
|
|
/* suppress jumps in the tb on which we could have jumped */
|
2003-06-25 20:16:50 +04:00
|
|
|
tb_reset_jump_recursive(tb_next);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tb_reset_jump_recursive(TranslationBlock *tb)
|
|
|
|
{
|
|
|
|
tb_reset_jump_recursive2(tb, 0);
|
|
|
|
tb_reset_jump_recursive2(tb, 1);
|
|
|
|
}
|
|
|
|
|
2005-04-17 23:16:13 +04:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2010-03-01 02:47:45 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
|
|
|
|
{
|
|
|
|
tb_invalidate_phys_page_range(pc, pc + 1, 0);
|
|
|
|
}
|
|
|
|
#else
|
2004-04-25 21:57:43 +04:00
|
|
|
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
|
|
|
|
{
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t addr;
|
2007-04-07 15:21:28 +04:00
|
|
|
target_ulong pd;
|
2009-10-02 01:12:16 +04:00
|
|
|
ram_addr_t ram_addr;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2004-04-25 21:57:43 +04:00
|
|
|
|
2006-04-08 21:14:56 +04:00
|
|
|
addr = cpu_get_phys_page_debug(env, pc);
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2006-04-08 21:14:56 +04:00
|
|
|
ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
|
2006-04-08 21:36:21 +04:00
|
|
|
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
|
2004-04-25 21:57:43 +04:00
|
|
|
}
|
2005-01-04 02:35:10 +03:00
|
|
|
#endif
|
2010-03-01 02:47:45 +03:00
|
|
|
#endif /* TARGET_HAS_ICE */
|
2004-04-25 21:57:43 +04:00
|
|
|
|
2010-03-01 06:31:14 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
void cpu_watchpoint_remove_all(CPUState *env, int mask)
|
|
|
|
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
|
|
|
int flags, CPUWatchpoint **watchpoint)
|
|
|
|
{
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
#else
|
2007-03-17 02:58:11 +03:00
|
|
|
/* Add a watchpoint. */
|
2008-11-18 23:07:32 +03:00
|
|
|
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
|
|
|
int flags, CPUWatchpoint **watchpoint)
|
2007-03-17 02:58:11 +03:00
|
|
|
{
|
2008-11-18 23:14:20 +03:00
|
|
|
target_ulong len_mask = ~(len - 1);
|
2008-11-26 01:13:57 +03:00
|
|
|
CPUWatchpoint *wp;
|
2007-03-17 02:58:11 +03:00
|
|
|
|
2008-11-18 23:14:20 +03:00
|
|
|
/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
|
|
|
|
if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
|
|
|
|
fprintf(stderr, "qemu: tried to set invalid watchpoint at "
|
|
|
|
TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-08-21 07:09:37 +04:00
|
|
|
wp = g_malloc(sizeof(*wp));
|
2008-11-18 23:07:32 +03:00
|
|
|
|
|
|
|
wp->vaddr = addr;
|
2008-11-18 23:14:20 +03:00
|
|
|
wp->len_mask = len_mask;
|
2008-11-18 23:07:32 +03:00
|
|
|
wp->flags = flags;
|
|
|
|
|
2008-11-18 23:56:59 +03:00
|
|
|
/* keep all GDB-injected watchpoints in front */
|
2008-11-26 01:13:57 +03:00
|
|
|
if (flags & BP_GDB)
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
|
2008-11-26 01:13:57 +03:00
|
|
|
else
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
|
2007-03-17 02:58:11 +03:00
|
|
|
|
|
|
|
tlb_flush_page(env, addr);
|
2008-11-18 23:07:32 +03:00
|
|
|
|
|
|
|
if (watchpoint)
|
|
|
|
*watchpoint = wp;
|
|
|
|
return 0;
|
2007-03-17 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
/* Remove a specific watchpoint. */
|
|
|
|
int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
|
|
|
|
int flags)
|
2007-03-17 02:58:11 +03:00
|
|
|
{
|
2008-11-18 23:14:20 +03:00
|
|
|
target_ulong len_mask = ~(len - 1);
|
2008-11-18 23:07:32 +03:00
|
|
|
CPUWatchpoint *wp;
|
2007-03-17 02:58:11 +03:00
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
2008-11-18 23:14:20 +03:00
|
|
|
if (addr == wp->vaddr && len_mask == wp->len_mask
|
2008-11-18 23:37:55 +03:00
|
|
|
&& flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
|
2008-11-18 23:07:32 +03:00
|
|
|
cpu_watchpoint_remove_by_ref(env, wp);
|
2007-03-17 02:58:11 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2008-11-18 23:07:32 +03:00
|
|
|
return -ENOENT;
|
2007-03-17 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
/* Remove a specific watchpoint by reference. */
|
|
|
|
void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
|
|
|
|
{
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
|
2008-05-17 22:58:29 +04:00
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
tlb_flush_page(env, watchpoint->vaddr);
|
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(watchpoint);
|
2008-11-18 23:07:32 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Remove all matching watchpoints. */
|
|
|
|
void cpu_watchpoint_remove_all(CPUState *env, int mask)
|
|
|
|
{
|
2008-11-26 01:13:57 +03:00
|
|
|
CPUWatchpoint *wp, *next;
|
2008-11-18 23:07:32 +03:00
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
|
2008-11-18 23:07:32 +03:00
|
|
|
if (wp->flags & mask)
|
|
|
|
cpu_watchpoint_remove_by_ref(env, wp);
|
2008-11-26 01:13:57 +03:00
|
|
|
}
|
2008-05-17 22:58:29 +04:00
|
|
|
}
|
2010-03-01 06:31:14 +03:00
|
|
|
#endif
|
2008-05-17 22:58:29 +04:00
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
/* Add a breakpoint. */
|
|
|
|
int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
|
|
|
|
CPUBreakpoint **breakpoint)
|
2003-07-26 16:06:08 +04:00
|
|
|
{
|
2005-04-17 23:16:13 +04:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2008-11-26 01:13:57 +03:00
|
|
|
CPUBreakpoint *bp;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
bp = g_malloc(sizeof(*bp));
|
2003-07-26 16:06:08 +04:00
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
bp->pc = pc;
|
|
|
|
bp->flags = flags;
|
|
|
|
|
2008-11-18 23:56:59 +03:00
|
|
|
/* keep all GDB-injected breakpoints in front */
|
2008-11-26 01:13:57 +03:00
|
|
|
if (flags & BP_GDB)
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
|
2008-11-26 01:13:57 +03:00
|
|
|
else
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-04-25 21:57:43 +04:00
|
|
|
breakpoint_invalidate(env, pc);
|
2008-11-18 23:07:32 +03:00
|
|
|
|
|
|
|
if (breakpoint)
|
|
|
|
*breakpoint = bp;
|
2003-07-26 16:06:08 +04:00
|
|
|
return 0;
|
|
|
|
#else
|
2008-11-18 23:07:32 +03:00
|
|
|
return -ENOSYS;
|
2003-07-26 16:06:08 +04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
/* Remove a specific breakpoint. */
|
|
|
|
int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
|
|
|
|
{
|
2008-05-17 22:58:29 +04:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2008-11-18 23:07:32 +03:00
|
|
|
CPUBreakpoint *bp;
|
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
2008-11-18 23:07:32 +03:00
|
|
|
if (bp->pc == pc && bp->flags == flags) {
|
|
|
|
cpu_breakpoint_remove_by_ref(env, bp);
|
|
|
|
return 0;
|
|
|
|
}
|
2008-05-17 22:58:29 +04:00
|
|
|
}
|
2008-11-18 23:07:32 +03:00
|
|
|
return -ENOENT;
|
|
|
|
#else
|
|
|
|
return -ENOSYS;
|
2008-05-17 22:58:29 +04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
/* Remove a specific breakpoint by reference. */
|
|
|
|
void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
|
2003-07-26 16:06:08 +04:00
|
|
|
{
|
2005-04-17 23:16:13 +04:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
|
2004-04-25 21:57:43 +04:00
|
|
|
|
2008-11-18 23:07:32 +03:00
|
|
|
breakpoint_invalidate(env, breakpoint->pc);
|
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(breakpoint);
|
2008-11-18 23:07:32 +03:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Remove all matching breakpoints. */
|
|
|
|
void cpu_breakpoint_remove_all(CPUState *env, int mask)
|
|
|
|
{
|
|
|
|
#if defined(TARGET_HAS_ICE)
|
2008-11-26 01:13:57 +03:00
|
|
|
CPUBreakpoint *bp, *next;
|
2008-11-18 23:07:32 +03:00
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
|
2008-11-18 23:07:32 +03:00
|
|
|
if (bp->flags & mask)
|
|
|
|
cpu_breakpoint_remove_by_ref(env, bp);
|
2008-11-26 01:13:57 +03:00
|
|
|
}
|
2003-07-26 16:06:08 +04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2003-07-30 00:50:33 +04:00
|
|
|
/* enable or disable single step mode. EXCP_DEBUG is returned by the
|
|
|
|
CPU loop after each instruction */
|
|
|
|
void cpu_single_step(CPUState *env, int enabled)
|
|
|
|
{
|
2005-04-17 23:16:13 +04:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2003-07-30 00:50:33 +04:00
|
|
|
if (env->singlestep_enabled != enabled) {
|
|
|
|
env->singlestep_enabled = enabled;
|
2009-03-12 23:12:48 +03:00
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_update_guest_debug(env, 0);
|
|
|
|
else {
|
2009-05-03 15:15:06 +04:00
|
|
|
/* must flush all the translated code to avoid inconsistencies */
|
2009-03-12 23:12:48 +03:00
|
|
|
/* XXX: only flush what is necessary */
|
|
|
|
tb_flush(env);
|
|
|
|
}
|
2003-07-30 00:50:33 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2003-10-05 18:28:56 +04:00
|
|
|
/* enable or disable low levels log */
|
|
|
|
void cpu_set_log(int log_flags)
|
|
|
|
{
|
|
|
|
loglevel = log_flags;
|
|
|
|
if (loglevel && !logfile) {
|
2007-07-01 22:21:11 +04:00
|
|
|
logfile = fopen(logfilename, log_append ? "a" : "w");
|
2003-10-05 18:28:56 +04:00
|
|
|
if (!logfile) {
|
|
|
|
perror(logfilename);
|
|
|
|
_exit(1);
|
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
|
|
|
/* must avoid mmap() usage of glibc by setting a buffer "by hand" */
|
|
|
|
{
|
2008-09-20 12:07:15 +04:00
|
|
|
static char logfile_buf[4096];
|
2004-01-04 21:06:42 +03:00
|
|
|
setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
|
|
|
|
}
|
2011-12-04 01:32:37 +04:00
|
|
|
#elif defined(_WIN32)
|
|
|
|
/* Win32 doesn't support line-buffering, so use unbuffered output. */
|
|
|
|
setvbuf(logfile, NULL, _IONBF, 0);
|
|
|
|
#else
|
2003-10-05 18:28:56 +04:00
|
|
|
setvbuf(logfile, NULL, _IOLBF, 0);
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
2007-06-30 17:53:24 +04:00
|
|
|
log_append = 1;
|
|
|
|
}
|
|
|
|
if (!loglevel && logfile) {
|
|
|
|
fclose(logfile);
|
|
|
|
logfile = NULL;
|
2003-10-05 18:28:56 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_set_log_filename(const char *filename)
|
|
|
|
{
|
|
|
|
logfilename = strdup(filename);
|
2007-06-30 17:53:24 +04:00
|
|
|
if (logfile) {
|
|
|
|
fclose(logfile);
|
|
|
|
logfile = NULL;
|
|
|
|
}
|
|
|
|
cpu_set_log(loglevel);
|
2003-10-05 18:28:56 +04:00
|
|
|
}
|
2003-07-30 00:50:33 +04:00
|
|
|
|
2009-03-08 00:28:24 +03:00
|
|
|
static void cpu_unlink_tb(CPUState *env)
|
2003-06-25 20:16:50 +04:00
|
|
|
{
|
2009-03-08 00:28:24 +03:00
|
|
|
/* FIXME: TB unchaining isn't SMP safe. For now just ignore the
|
|
|
|
problem and hope the cpu will stop of its own accord. For userspace
|
|
|
|
emulation this often isn't actually as bad as it sounds. Often
|
|
|
|
signals are used primarily to interrupt blocking syscalls. */
|
2003-06-25 20:16:50 +04:00
|
|
|
TranslationBlock *tb;
|
2009-10-02 01:12:16 +04:00
|
|
|
static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
|
2004-02-17 01:01:13 +03:00
|
|
|
|
2010-01-20 13:56:27 +03:00
|
|
|
spin_lock(&interrupt_lock);
|
2009-03-08 00:28:24 +03:00
|
|
|
tb = env->current_tb;
|
|
|
|
/* if the cpu is currently executing code, we must unlink it and
|
|
|
|
all the potentially executing TB */
|
2009-12-04 16:16:30 +03:00
|
|
|
if (tb) {
|
2009-03-08 00:28:24 +03:00
|
|
|
env->current_tb = NULL;
|
|
|
|
tb_reset_jump_recursive(tb);
|
2009-03-07 00:48:00 +03:00
|
|
|
}
|
2010-01-20 13:56:27 +03:00
|
|
|
spin_unlock(&interrupt_lock);
|
2009-03-08 00:28:24 +03:00
|
|
|
}
|
|
|
|
|
2011-04-13 03:32:56 +04:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2009-03-08 00:28:24 +03:00
|
|
|
/* mask must never be zero, except for A20 change call */
|
2011-04-13 03:32:56 +04:00
|
|
|
static void tcg_handle_interrupt(CPUState *env, int mask)
|
2009-03-08 00:28:24 +03:00
|
|
|
{
|
|
|
|
int old_mask;
|
2009-03-07 00:48:00 +03:00
|
|
|
|
2008-06-29 05:03:05 +04:00
|
|
|
old_mask = env->interrupt_request;
|
2003-06-30 17:12:32 +04:00
|
|
|
env->interrupt_request |= mask;
|
2009-03-08 00:28:24 +03:00
|
|
|
|
2009-04-24 22:03:45 +04:00
|
|
|
/*
|
|
|
|
* If called from iothread context, wake the target cpu in
|
|
|
|
* case its halted.
|
|
|
|
*/
|
2011-03-12 19:43:51 +03:00
|
|
|
if (!qemu_cpu_is_self(env)) {
|
2009-04-24 22:03:45 +04:00
|
|
|
qemu_cpu_kick(env);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-06-29 05:03:05 +04:00
|
|
|
if (use_icount) {
|
2008-07-09 19:31:50 +04:00
|
|
|
env->icount_decr.u16.high = 0xffff;
|
2008-06-29 05:03:05 +04:00
|
|
|
if (!can_do_io(env)
|
2009-03-07 00:48:00 +03:00
|
|
|
&& (mask & ~old_mask) != 0) {
|
2008-06-29 05:03:05 +04:00
|
|
|
cpu_abort(env, "Raised interrupt while not in I/O function");
|
|
|
|
}
|
|
|
|
} else {
|
2009-03-08 00:28:24 +03:00
|
|
|
cpu_unlink_tb(env);
|
2003-06-25 20:16:50 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-04-13 03:32:56 +04:00
|
|
|
CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
|
|
|
|
|
2011-04-13 03:32:56 +04:00
|
|
|
#else /* CONFIG_USER_ONLY */
|
|
|
|
|
|
|
|
void cpu_interrupt(CPUState *env, int mask)
|
|
|
|
{
|
|
|
|
env->interrupt_request |= mask;
|
|
|
|
cpu_unlink_tb(env);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
|
2004-05-20 17:42:52 +04:00
|
|
|
void cpu_reset_interrupt(CPUState *env, int mask)
|
|
|
|
{
|
|
|
|
env->interrupt_request &= ~mask;
|
|
|
|
}
|
|
|
|
|
2009-03-08 00:28:24 +03:00
|
|
|
void cpu_exit(CPUState *env)
|
|
|
|
{
|
|
|
|
env->exit_request = 1;
|
|
|
|
cpu_unlink_tb(env);
|
|
|
|
}
|
|
|
|
|
2008-10-02 22:27:46 +04:00
|
|
|
const CPULogItem cpu_log_items[] = {
|
2007-09-17 01:08:06 +04:00
|
|
|
{ CPU_LOG_TB_OUT_ASM, "out_asm",
|
2004-03-21 20:06:25 +03:00
|
|
|
"show generated host assembly code for each compiled TB" },
|
|
|
|
{ CPU_LOG_TB_IN_ASM, "in_asm",
|
|
|
|
"show target assembly code for each compiled TB" },
|
2007-09-17 01:08:06 +04:00
|
|
|
{ CPU_LOG_TB_OP, "op",
|
2008-02-01 13:50:11 +03:00
|
|
|
"show micro ops for each compiled TB" },
|
2004-03-21 20:06:25 +03:00
|
|
|
{ CPU_LOG_TB_OP_OPT, "op_opt",
|
2008-03-14 20:37:11 +03:00
|
|
|
"show micro ops "
|
|
|
|
#ifdef TARGET_I386
|
|
|
|
"before eflags optimization and "
|
2004-03-21 20:06:25 +03:00
|
|
|
#endif
|
2008-03-14 20:37:11 +03:00
|
|
|
"after liveness analysis" },
|
2004-03-21 20:06:25 +03:00
|
|
|
{ CPU_LOG_INT, "int",
|
|
|
|
"show interrupts/exceptions in short format" },
|
|
|
|
{ CPU_LOG_EXEC, "exec",
|
|
|
|
"show trace before each executed TB (lots of logs)" },
|
2004-05-21 16:59:32 +04:00
|
|
|
{ CPU_LOG_TB_CPU, "cpu",
|
2007-06-03 17:35:16 +04:00
|
|
|
"show CPU state before block translation" },
|
2004-03-21 20:06:25 +03:00
|
|
|
#ifdef TARGET_I386
|
|
|
|
{ CPU_LOG_PCALL, "pcall",
|
|
|
|
"show protected mode far calls/returns/exceptions" },
|
2009-01-26 22:54:31 +03:00
|
|
|
{ CPU_LOG_RESET, "cpu_reset",
|
|
|
|
"show CPU state before CPU resets" },
|
2004-03-21 20:06:25 +03:00
|
|
|
#endif
|
2004-10-09 21:32:58 +04:00
|
|
|
#ifdef DEBUG_IOPORT
|
2004-05-12 23:11:15 +04:00
|
|
|
{ CPU_LOG_IOPORT, "ioport",
|
|
|
|
"show all i/o ports accesses" },
|
2004-10-09 21:32:58 +04:00
|
|
|
#endif
|
2004-03-21 20:06:25 +03:00
|
|
|
{ 0, NULL, NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int cmp1(const char *s1, int n, const char *s2)
|
|
|
|
{
|
|
|
|
if (strlen(s2) != n)
|
|
|
|
return 0;
|
|
|
|
return memcmp(s1, s2, n) == 0;
|
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-03-21 20:06:25 +03:00
|
|
|
/* takes a comma separated list of log masks. Return 0 if error. */
|
|
|
|
int cpu_str_to_log_mask(const char *str)
|
|
|
|
{
|
2008-10-02 22:27:46 +04:00
|
|
|
const CPULogItem *item;
|
2004-03-21 20:06:25 +03:00
|
|
|
int mask;
|
|
|
|
const char *p, *p1;
|
|
|
|
|
|
|
|
p = str;
|
|
|
|
mask = 0;
|
|
|
|
for(;;) {
|
|
|
|
p1 = strchr(p, ',');
|
|
|
|
if (!p1)
|
|
|
|
p1 = p + strlen(p);
|
2010-08-18 08:30:13 +04:00
|
|
|
if(cmp1(p,p1-p,"all")) {
|
|
|
|
for(item = cpu_log_items; item->mask != 0; item++) {
|
|
|
|
mask |= item->mask;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for(item = cpu_log_items; item->mask != 0; item++) {
|
|
|
|
if (cmp1(p, p1 - p, item->name))
|
|
|
|
goto found;
|
|
|
|
}
|
|
|
|
return 0;
|
2004-03-21 20:06:25 +03:00
|
|
|
}
|
|
|
|
found:
|
|
|
|
mask |= item->mask;
|
|
|
|
if (*p1 != ',')
|
|
|
|
break;
|
|
|
|
p = p1 + 1;
|
|
|
|
}
|
|
|
|
return mask;
|
|
|
|
}
|
2003-06-25 20:16:50 +04:00
|
|
|
|
2003-06-21 17:11:07 +04:00
|
|
|
void cpu_abort(CPUState *env, const char *fmt, ...)
|
|
|
|
{
|
|
|
|
va_list ap;
|
2007-11-23 19:53:59 +03:00
|
|
|
va_list ap2;
|
2003-06-21 17:11:07 +04:00
|
|
|
|
|
|
|
va_start(ap, fmt);
|
2007-11-23 19:53:59 +03:00
|
|
|
va_copy(ap2, ap);
|
2003-06-21 17:11:07 +04:00
|
|
|
fprintf(stderr, "qemu: fatal: ");
|
|
|
|
vfprintf(stderr, fmt, ap);
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
#ifdef TARGET_I386
|
2004-10-09 22:08:01 +04:00
|
|
|
cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
|
|
|
|
#else
|
|
|
|
cpu_dump_state(env, stderr, fprintf, 0);
|
2003-06-21 17:11:07 +04:00
|
|
|
#endif
|
2009-01-16 01:34:14 +03:00
|
|
|
if (qemu_log_enabled()) {
|
|
|
|
qemu_log("qemu: fatal: ");
|
|
|
|
qemu_log_vprintf(fmt, ap2);
|
|
|
|
qemu_log("\n");
|
2007-09-29 16:18:20 +04:00
|
|
|
#ifdef TARGET_I386
|
2009-01-16 01:34:14 +03:00
|
|
|
log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
|
2007-09-29 16:18:20 +04:00
|
|
|
#else
|
2009-01-16 01:34:14 +03:00
|
|
|
log_cpu_state(env, 0);
|
2007-09-29 16:18:20 +04:00
|
|
|
#endif
|
2009-01-16 01:35:09 +03:00
|
|
|
qemu_log_flush();
|
2009-01-16 01:34:14 +03:00
|
|
|
qemu_log_close();
|
2007-06-10 18:07:13 +04:00
|
|
|
}
|
2007-11-23 19:53:59 +03:00
|
|
|
va_end(ap2);
|
2007-09-29 16:18:20 +04:00
|
|
|
va_end(ap);
|
2010-01-25 15:30:49 +03:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
{
|
|
|
|
struct sigaction act;
|
|
|
|
sigfillset(&act.sa_mask);
|
|
|
|
act.sa_handler = SIG_DFL;
|
|
|
|
sigaction(SIGABRT, &act, NULL);
|
|
|
|
}
|
|
|
|
#endif
|
2003-06-21 17:11:07 +04:00
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2007-02-28 23:20:53 +03:00
|
|
|
CPUState *cpu_copy(CPUState *env)
|
|
|
|
{
|
2007-12-09 05:22:57 +03:00
|
|
|
CPUState *new_env = cpu_init(env->cpu_model_str);
|
2007-02-28 23:20:53 +03:00
|
|
|
CPUState *next_cpu = new_env->next_cpu;
|
|
|
|
int cpu_index = new_env->cpu_index;
|
2009-01-15 23:16:51 +03:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
|
|
|
CPUBreakpoint *bp;
|
|
|
|
CPUWatchpoint *wp;
|
|
|
|
#endif
|
|
|
|
|
2007-02-28 23:20:53 +03:00
|
|
|
memcpy(new_env, env, sizeof(CPUState));
|
2009-01-15 23:16:51 +03:00
|
|
|
|
|
|
|
/* Preserve chaining and index. */
|
2007-02-28 23:20:53 +03:00
|
|
|
new_env->next_cpu = next_cpu;
|
|
|
|
new_env->cpu_index = cpu_index;
|
2009-01-15 23:16:51 +03:00
|
|
|
|
|
|
|
/* Clone all break/watchpoints.
|
|
|
|
Note: Once we support ptrace with hw-debug register access, make sure
|
|
|
|
BP_CPU break/watchpoints are handled correctly on clone. */
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_INIT(&env->breakpoints);
|
|
|
|
QTAILQ_INIT(&env->watchpoints);
|
2009-01-15 23:16:51 +03:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
2009-01-15 23:16:51 +03:00
|
|
|
cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
|
|
|
|
}
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
2009-01-15 23:16:51 +03:00
|
|
|
cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
|
|
|
|
wp->flags, NULL);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2007-02-28 23:20:53 +03:00
|
|
|
return new_env;
|
|
|
|
}
|
|
|
|
|
2004-01-04 18:48:17 +03:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
|
2008-05-06 12:44:21 +04:00
|
|
|
static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/* Discard jump cache entries for any tb which might potentially
|
|
|
|
overlap the flushed page. */
|
|
|
|
i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
|
|
|
|
memset (&env->tb_jmp_cache[i], 0,
|
2010-08-18 08:30:13 +04:00
|
|
|
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
|
2008-05-06 12:44:21 +04:00
|
|
|
|
|
|
|
i = tb_jmp_cache_hash_page(addr);
|
|
|
|
memset (&env->tb_jmp_cache[i], 0,
|
2010-08-18 08:30:13 +04:00
|
|
|
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
|
2008-05-06 12:44:21 +04:00
|
|
|
}
|
|
|
|
|
2009-07-12 02:15:40 +04:00
|
|
|
static CPUTLBEntry s_cputlb_empty_entry = {
|
|
|
|
.addr_read = -1,
|
|
|
|
.addr_write = -1,
|
|
|
|
.addr_code = -1,
|
|
|
|
.addend = -1,
|
|
|
|
};
|
|
|
|
|
2012-01-17 17:23:13 +04:00
|
|
|
/* NOTE:
|
|
|
|
* If flush_global is true (the usual case), flush all tlb entries.
|
|
|
|
* If flush_global is false, flush (at least) all tlb entries not
|
|
|
|
* marked global.
|
|
|
|
*
|
|
|
|
* Since QEMU doesn't currently implement a global/not-global flag
|
|
|
|
* for tlb entries, at the moment tlb_flush() will also flush all
|
|
|
|
* tlb entries in the flush_global == false case. This is OK because
|
|
|
|
* CPU architectures generally permit an implementation to drop
|
|
|
|
* entries from the TLB at any time, so flushing more entries than
|
|
|
|
* required is only an efficiency issue, not a correctness issue.
|
|
|
|
*/
|
2004-02-04 02:35:10 +03:00
|
|
|
void tlb_flush(CPUState *env, int flush_global)
|
2003-08-11 01:47:01 +04:00
|
|
|
{
|
|
|
|
int i;
|
2004-01-04 18:48:17 +03:00
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
#if defined(DEBUG_TLB)
|
|
|
|
printf("tlb_flush:\n");
|
|
|
|
#endif
|
2004-01-04 18:48:17 +03:00
|
|
|
/* must reset current TB so that interrupts cannot modify the
|
|
|
|
links while we are modifying them */
|
|
|
|
env->current_tb = NULL;
|
|
|
|
|
2003-08-11 01:47:01 +04:00
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++) {
|
2009-05-20 06:31:43 +04:00
|
|
|
int mmu_idx;
|
|
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
2009-07-12 02:15:40 +04:00
|
|
|
env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
|
2009-05-20 06:31:43 +04:00
|
|
|
}
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2005-11-20 13:35:40 +03:00
|
|
|
memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2010-03-17 05:14:28 +03:00
|
|
|
env->tlb_flush_addr = -1;
|
|
|
|
env->tlb_flush_mask = 0;
|
2005-01-27 01:00:47 +03:00
|
|
|
tlb_flush_count++;
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
|
|
|
|
2004-05-21 01:56:27 +04:00
|
|
|
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
|
2003-10-28 00:22:23 +03:00
|
|
|
{
|
2007-09-17 01:08:06 +04:00
|
|
|
if (addr == (tlb_entry->addr_read &
|
2005-11-29 00:19:04 +03:00
|
|
|
(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
|
2007-09-17 01:08:06 +04:00
|
|
|
addr == (tlb_entry->addr_write &
|
2005-11-29 00:19:04 +03:00
|
|
|
(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
|
2007-09-17 01:08:06 +04:00
|
|
|
addr == (tlb_entry->addr_code &
|
2005-11-29 00:19:04 +03:00
|
|
|
(TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
2009-07-12 02:15:40 +04:00
|
|
|
*tlb_entry = s_cputlb_empty_entry;
|
2005-11-29 00:19:04 +03:00
|
|
|
}
|
2003-10-28 00:22:23 +03:00
|
|
|
}
|
|
|
|
|
2004-04-26 01:28:44 +04:00
|
|
|
void tlb_flush_page(CPUState *env, target_ulong addr)
|
2003-08-11 01:47:01 +04:00
|
|
|
{
|
2005-11-20 13:35:40 +03:00
|
|
|
int i;
|
2009-05-20 06:31:43 +04:00
|
|
|
int mmu_idx;
|
2004-01-04 18:48:17 +03:00
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
#if defined(DEBUG_TLB)
|
2005-07-24 16:55:09 +04:00
|
|
|
printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
2010-03-17 05:14:28 +03:00
|
|
|
/* Check if we need to flush due to large pages. */
|
|
|
|
if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
|
|
|
|
#if defined(DEBUG_TLB)
|
|
|
|
printf("tlb_flush_page: forced full flush ("
|
|
|
|
TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
|
|
|
|
env->tlb_flush_addr, env->tlb_flush_mask);
|
|
|
|
#endif
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
return;
|
|
|
|
}
|
2004-01-04 18:48:17 +03:00
|
|
|
/* must reset current TB so that interrupts cannot modify the
|
|
|
|
links while we are modifying them */
|
|
|
|
env->current_tb = NULL;
|
2003-10-28 00:22:23 +03:00
|
|
|
|
|
|
|
addr &= TARGET_PAGE_MASK;
|
|
|
|
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
2009-05-20 06:31:43 +04:00
|
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
|
|
|
|
tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
|
2004-01-04 18:48:17 +03:00
|
|
|
|
2008-05-06 12:44:21 +04:00
|
|
|
tlb_flush_jmp_cache(env, addr);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* update the TLBs so that writes to code in the virtual page 'addr'
|
|
|
|
can be detected */
|
2009-10-02 01:12:16 +04:00
|
|
|
static void tlb_protect_code(ram_addr_t ram_addr)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2007-09-17 01:08:06 +04:00
|
|
|
cpu_physical_memory_reset_dirty(ram_addr,
|
2005-11-22 02:25:50 +03:00
|
|
|
ram_addr + TARGET_PAGE_SIZE,
|
|
|
|
CODE_DIRTY_FLAG);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* update the TLB so that writes in physical page 'phys_addr' are no longer
|
2005-08-21 13:26:42 +04:00
|
|
|
tested for self modifying code */
|
2009-10-02 01:12:16 +04:00
|
|
|
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
|
2005-08-21 13:26:42 +04:00
|
|
|
target_ulong vaddr)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
|
2004-02-06 22:46:14 +03:00
|
|
|
}
|
|
|
|
|
2007-09-17 01:08:06 +04:00
|
|
|
static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
|
2004-02-06 22:46:14 +03:00
|
|
|
unsigned long start, unsigned long length)
|
|
|
|
{
|
|
|
|
unsigned long addr;
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) {
|
2005-11-29 00:19:04 +03:00
|
|
|
addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
|
2004-02-06 22:46:14 +03:00
|
|
|
if ((addr - start) < length) {
|
2008-06-09 04:20:13 +04:00
|
|
|
tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
|
2004-02-06 22:46:14 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-04-11 18:47:08 +04:00
|
|
|
/* Note: start and end must be within the same ram block. */
|
2009-10-02 01:12:16 +04:00
|
|
|
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
2005-02-11 01:00:27 +03:00
|
|
|
int dirty_flags)
|
2004-02-06 22:46:14 +03:00
|
|
|
{
|
|
|
|
CPUState *env;
|
2004-04-26 23:44:02 +04:00
|
|
|
unsigned long length, start1;
|
2010-03-23 10:39:53 +03:00
|
|
|
int i;
|
2004-02-06 22:46:14 +03:00
|
|
|
|
|
|
|
start &= TARGET_PAGE_MASK;
|
|
|
|
end = TARGET_PAGE_ALIGN(end);
|
|
|
|
|
|
|
|
length = end - start;
|
|
|
|
if (length == 0)
|
|
|
|
return;
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_mask_dirty_range(start, length, dirty_flags);
|
2005-08-21 23:12:28 +04:00
|
|
|
|
2004-02-06 22:46:14 +03:00
|
|
|
/* we modify the TLB cache so that the dirty bit will be set again
|
|
|
|
when accessing the range */
|
2010-11-22 20:52:34 +03:00
|
|
|
start1 = (unsigned long)qemu_safe_ram_ptr(start);
|
2011-05-01 00:49:26 +04:00
|
|
|
/* Check that we don't span multiple blocks - this breaks the
|
2009-04-11 18:47:08 +04:00
|
|
|
address comparisons below. */
|
2010-11-22 20:52:34 +03:00
|
|
|
if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1
|
2009-04-11 18:47:08 +04:00
|
|
|
!= (end - 1) - start) {
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2005-11-22 02:25:50 +03:00
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
2009-05-20 06:31:43 +04:00
|
|
|
int mmu_idx;
|
|
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
|
|
|
tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
|
|
|
|
start1, length);
|
|
|
|
}
|
2005-11-22 02:25:50 +03:00
|
|
|
}
|
2004-02-06 22:46:14 +03:00
|
|
|
}
|
|
|
|
|
2008-10-06 18:02:03 +04:00
|
|
|
int cpu_physical_memory_set_dirty_tracking(int enable)
|
|
|
|
{
|
2010-01-27 23:06:57 +03:00
|
|
|
int ret = 0;
|
2008-10-06 18:02:03 +04:00
|
|
|
in_migration = enable;
|
2010-01-27 23:06:57 +03:00
|
|
|
return ret;
|
2008-10-06 18:02:03 +04:00
|
|
|
}
|
|
|
|
|
2005-08-21 13:26:42 +04:00
|
|
|
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
|
|
|
|
{
|
2009-10-02 01:12:16 +04:00
|
|
|
ram_addr_t ram_addr;
|
2009-04-11 18:47:08 +04:00
|
|
|
void *p;
|
2005-08-21 13:26:42 +04:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) {
|
2009-04-11 18:47:08 +04:00
|
|
|
p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK)
|
|
|
|
+ tlb_entry->addend);
|
2010-10-11 22:31:19 +04:00
|
|
|
ram_addr = qemu_ram_addr_from_host_nofail(p);
|
2005-08-21 13:26:42 +04:00
|
|
|
if (!cpu_physical_memory_is_dirty(ram_addr)) {
|
2008-06-09 04:20:13 +04:00
|
|
|
tlb_entry->addr_write |= TLB_NOTDIRTY;
|
2005-08-21 13:26:42 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* update the TLB according to the current state of the dirty bits */
|
|
|
|
void cpu_tlb_update_dirty(CPUState *env)
|
|
|
|
{
|
|
|
|
int i;
|
2009-05-20 06:31:43 +04:00
|
|
|
int mmu_idx;
|
|
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
|
|
|
tlb_update_dirty(&env->tlb_table[mmu_idx][i]);
|
|
|
|
}
|
2005-08-21 13:26:42 +04:00
|
|
|
}
|
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
|
2004-02-06 22:46:14 +03:00
|
|
|
{
|
2008-06-09 04:20:13 +04:00
|
|
|
if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
|
|
|
|
tlb_entry->addr_write = vaddr;
|
2004-02-06 22:46:14 +03:00
|
|
|
}
|
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
/* update the TLB corresponding to virtual page vaddr
|
|
|
|
so that it is no longer dirty */
|
|
|
|
static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
|
2004-02-06 22:46:14 +03:00
|
|
|
{
|
|
|
|
int i;
|
2009-05-20 06:31:43 +04:00
|
|
|
int mmu_idx;
|
2004-02-06 22:46:14 +03:00
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
vaddr &= TARGET_PAGE_MASK;
|
2004-02-06 22:46:14 +03:00
|
|
|
i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
2009-05-20 06:31:43 +04:00
|
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
|
|
|
|
tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
|
2010-03-17 05:14:28 +03:00
|
|
|
/* Our TLB does not support large pages, so remember the area covered by
|
|
|
|
large pages and trigger a full TLB flush if these are invalidated. */
|
|
|
|
static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
|
|
|
|
target_ulong size)
|
|
|
|
{
|
|
|
|
target_ulong mask = ~(size - 1);
|
|
|
|
|
|
|
|
if (env->tlb_flush_addr == (target_ulong)-1) {
|
|
|
|
env->tlb_flush_addr = vaddr & mask;
|
|
|
|
env->tlb_flush_mask = mask;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* Extend the existing region to include the new page.
|
|
|
|
This is a compromise between unnecessary flushes and the cost
|
|
|
|
of maintaining a full variable size TLB. */
|
|
|
|
mask &= env->tlb_flush_mask;
|
|
|
|
while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
|
|
|
|
mask <<= 1;
|
|
|
|
}
|
|
|
|
env->tlb_flush_addr &= mask;
|
|
|
|
env->tlb_flush_mask = mask;
|
|
|
|
}
|
|
|
|
|
2012-01-01 23:15:42 +04:00
|
|
|
static bool is_ram_rom(ram_addr_t pd)
|
|
|
|
{
|
|
|
|
pd &= ~TARGET_PAGE_MASK;
|
2012-01-02 02:32:15 +04:00
|
|
|
return pd == io_mem_ram.ram_addr || pd == io_mem_rom.ram_addr;
|
2012-01-01 23:15:42 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 17:40:52 +04:00
|
|
|
static bool is_romd(ram_addr_t pd)
|
|
|
|
{
|
|
|
|
MemoryRegion *mr;
|
|
|
|
|
|
|
|
pd &= ~TARGET_PAGE_MASK;
|
2012-01-02 19:21:07 +04:00
|
|
|
mr = io_mem_region[pd];
|
2012-01-02 17:40:52 +04:00
|
|
|
return mr->rom_device && mr->readable;
|
|
|
|
}
|
|
|
|
|
2012-01-01 23:15:42 +04:00
|
|
|
static bool is_ram_rom_romd(ram_addr_t pd)
|
|
|
|
{
|
2012-01-02 17:40:52 +04:00
|
|
|
return is_ram_rom(pd) || is_romd(pd);
|
2012-01-01 23:15:42 +04:00
|
|
|
}
|
|
|
|
|
2010-03-17 05:14:28 +03:00
|
|
|
/* Add a new TLB entry. At most one entry for a given virtual address
|
|
|
|
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
|
|
|
|
supplied size is only used by tlb_flush_page. */
|
|
|
|
void tlb_set_page(CPUState *env, target_ulong vaddr,
|
|
|
|
target_phys_addr_t paddr, int prot,
|
|
|
|
int mmu_idx, target_ulong size)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2004-04-26 23:44:02 +04:00
|
|
|
unsigned long pd;
|
2004-01-04 21:06:42 +03:00
|
|
|
unsigned int index;
|
2004-04-26 23:44:02 +04:00
|
|
|
target_ulong address;
|
2008-06-09 04:20:13 +04:00
|
|
|
target_ulong code_address;
|
2010-04-05 03:28:53 +04:00
|
|
|
unsigned long addend;
|
2005-11-29 00:19:04 +03:00
|
|
|
CPUTLBEntry *te;
|
2008-11-18 23:07:32 +03:00
|
|
|
CPUWatchpoint *wp;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t iotlb;
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2010-03-17 05:14:28 +03:00
|
|
|
assert(size >= TARGET_PAGE_SIZE);
|
|
|
|
if (size != TARGET_PAGE_SIZE) {
|
|
|
|
tlb_add_large_page(env, vaddr, size);
|
|
|
|
}
|
2004-05-21 18:52:29 +04:00
|
|
|
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2004-01-04 21:06:42 +03:00
|
|
|
#if defined(DEBUG_TLB)
|
2010-10-01 00:39:51 +04:00
|
|
|
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
|
|
|
|
" prot=%x idx=%d pd=0x%08lx\n",
|
|
|
|
vaddr, paddr, prot, mmu_idx, pd);
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
address = vaddr;
|
2012-01-01 23:15:42 +04:00
|
|
|
if (!is_ram_rom_romd(pd)) {
|
2008-06-09 04:20:13 +04:00
|
|
|
/* IO memory case (romd handled later) */
|
|
|
|
address |= TLB_MMIO;
|
|
|
|
}
|
2009-04-11 18:47:08 +04:00
|
|
|
addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
|
2012-01-01 23:15:42 +04:00
|
|
|
if (is_ram_rom(pd)) {
|
2008-06-09 04:20:13 +04:00
|
|
|
/* Normal RAM. */
|
|
|
|
iotlb = pd & TARGET_PAGE_MASK;
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr)
|
|
|
|
iotlb |= io_mem_notdirty.ram_addr;
|
2008-06-09 04:20:13 +04:00
|
|
|
else
|
2012-01-02 02:32:15 +04:00
|
|
|
iotlb |= io_mem_rom.ram_addr;
|
2008-06-09 04:20:13 +04:00
|
|
|
} else {
|
2009-05-03 15:15:06 +04:00
|
|
|
/* IO handlers are currently passed a physical address.
|
2008-06-09 04:20:13 +04:00
|
|
|
It would be nice to pass an offset from the base address
|
|
|
|
of that region. This would avoid having to special case RAM,
|
|
|
|
and avoid full address decoding in every device.
|
|
|
|
We can't use the high bits of pd for this because
|
|
|
|
IO_MEM_ROMD uses these as a ram address. */
|
2008-12-01 21:59:50 +03:00
|
|
|
iotlb = (pd & ~TARGET_PAGE_MASK);
|
2011-11-20 19:52:22 +04:00
|
|
|
iotlb += p.region_offset;
|
2008-06-09 04:20:13 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
code_address = address;
|
|
|
|
/* Make accesses to pages with watchpoints go via the
|
|
|
|
watchpoint trap routines. */
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
2008-11-18 23:07:32 +03:00
|
|
|
if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
|
2010-05-06 09:36:59 +04:00
|
|
|
/* Avoid trapping reads of pages with a write breakpoint. */
|
|
|
|
if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
|
2012-01-02 14:47:48 +04:00
|
|
|
iotlb = io_mem_watch.ram_addr + paddr;
|
2010-05-06 09:36:59 +04:00
|
|
|
address |= TLB_MMIO;
|
|
|
|
break;
|
|
|
|
}
|
2007-03-17 02:58:11 +03:00
|
|
|
}
|
2008-06-09 04:20:13 +04:00
|
|
|
}
|
2007-06-27 00:01:13 +04:00
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
env->iotlb[mmu_idx][index] = iotlb - vaddr;
|
|
|
|
te = &env->tlb_table[mmu_idx][index];
|
|
|
|
te->addend = addend - vaddr;
|
|
|
|
if (prot & PAGE_READ) {
|
|
|
|
te->addr_read = address;
|
|
|
|
} else {
|
|
|
|
te->addr_read = -1;
|
|
|
|
}
|
2008-05-06 12:44:21 +04:00
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
if (prot & PAGE_EXEC) {
|
|
|
|
te->addr_code = code_address;
|
|
|
|
} else {
|
|
|
|
te->addr_code = -1;
|
|
|
|
}
|
|
|
|
if (prot & PAGE_WRITE) {
|
2012-01-02 17:40:52 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) == io_mem_rom.ram_addr || is_romd(pd)) {
|
2008-06-09 04:20:13 +04:00
|
|
|
/* Write access calls the I/O callback. */
|
|
|
|
te->addr_write = address | TLB_MMIO;
|
2012-01-02 02:32:15 +04:00
|
|
|
} else if ((pd & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr &&
|
2008-06-09 04:20:13 +04:00
|
|
|
!cpu_physical_memory_is_dirty(pd)) {
|
|
|
|
te->addr_write = address | TLB_NOTDIRTY;
|
2004-01-04 21:06:42 +03:00
|
|
|
} else {
|
2008-06-09 04:20:13 +04:00
|
|
|
te->addr_write = address;
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
2008-06-09 04:20:13 +04:00
|
|
|
} else {
|
|
|
|
te->addr_write = -1;
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-01-04 18:48:17 +03:00
|
|
|
#else
|
|
|
|
|
2004-02-04 02:35:10 +03:00
|
|
|
void tlb_flush(CPUState *env, int flush_global)
|
2004-01-04 18:48:17 +03:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2004-04-26 01:28:44 +04:00
|
|
|
void tlb_flush_page(CPUState *env, target_ulong addr)
|
2004-01-04 18:48:17 +03:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2009-04-07 10:57:11 +04:00
|
|
|
/*
|
|
|
|
* Walks guest process memory "regions" one by one
|
|
|
|
* and calls callback function 'fn' for each region.
|
|
|
|
*/
|
2010-03-11 02:53:37 +03:00
|
|
|
|
|
|
|
struct walk_memory_regions_data
|
|
|
|
{
|
|
|
|
walk_memory_regions_fn fn;
|
|
|
|
void *priv;
|
|
|
|
unsigned long start;
|
|
|
|
int prot;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int walk_memory_regions_end(struct walk_memory_regions_data *data,
|
2010-03-13 02:23:29 +03:00
|
|
|
abi_ulong end, int new_prot)
|
2010-03-11 02:53:37 +03:00
|
|
|
{
|
|
|
|
if (data->start != -1ul) {
|
|
|
|
int rc = data->fn(data->priv, data->start, end, data->prot);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
data->start = (new_prot ? end : -1ul);
|
|
|
|
data->prot = new_prot;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int walk_memory_regions_1(struct walk_memory_regions_data *data,
|
2010-03-13 02:23:29 +03:00
|
|
|
abi_ulong base, int level, void **lp)
|
2010-03-11 02:53:37 +03:00
|
|
|
{
|
2010-03-13 02:23:29 +03:00
|
|
|
abi_ulong pa;
|
2010-03-11 02:53:37 +03:00
|
|
|
int i, rc;
|
|
|
|
|
|
|
|
if (*lp == NULL) {
|
|
|
|
return walk_memory_regions_end(data, base, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (level == 0) {
|
|
|
|
PageDesc *pd = *lp;
|
2010-03-14 17:58:46 +03:00
|
|
|
for (i = 0; i < L2_SIZE; ++i) {
|
2010-03-11 02:53:37 +03:00
|
|
|
int prot = pd[i].flags;
|
|
|
|
|
|
|
|
pa = base | (i << TARGET_PAGE_BITS);
|
|
|
|
if (prot != data->prot) {
|
|
|
|
rc = walk_memory_regions_end(data, pa, prot);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
void **pp = *lp;
|
2010-03-14 17:58:46 +03:00
|
|
|
for (i = 0; i < L2_SIZE; ++i) {
|
2010-03-13 02:23:29 +03:00
|
|
|
pa = base | ((abi_ulong)i <<
|
|
|
|
(TARGET_PAGE_BITS + L2_BITS * level));
|
2010-03-11 02:53:37 +03:00
|
|
|
rc = walk_memory_regions_1(data, pa, level - 1, pp + i);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int walk_memory_regions(void *priv, walk_memory_regions_fn fn)
|
|
|
|
{
|
|
|
|
struct walk_memory_regions_data data;
|
|
|
|
unsigned long i;
|
|
|
|
|
|
|
|
data.fn = fn;
|
|
|
|
data.priv = priv;
|
|
|
|
data.start = -1ul;
|
|
|
|
data.prot = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < V_L1_SIZE; i++) {
|
2010-03-13 02:23:29 +03:00
|
|
|
int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT,
|
2010-03-11 02:53:37 +03:00
|
|
|
V_L1_SHIFT / L2_BITS - 1, l1_map + i);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
2010-03-11 02:53:37 +03:00
|
|
|
|
|
|
|
return walk_memory_regions_end(&data, 0, 0);
|
2009-04-07 10:57:11 +04:00
|
|
|
}
|
|
|
|
|
2010-03-13 02:23:29 +03:00
|
|
|
static int dump_region(void *priv, abi_ulong start,
|
|
|
|
abi_ulong end, unsigned long prot)
|
2009-04-07 10:57:11 +04:00
|
|
|
{
|
|
|
|
FILE *f = (FILE *)priv;
|
|
|
|
|
2010-03-13 02:23:29 +03:00
|
|
|
(void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx
|
|
|
|
" "TARGET_ABI_FMT_lx" %c%c%c\n",
|
2009-04-07 10:57:11 +04:00
|
|
|
start, end, end - start,
|
|
|
|
((prot & PAGE_READ) ? 'r' : '-'),
|
|
|
|
((prot & PAGE_WRITE) ? 'w' : '-'),
|
|
|
|
((prot & PAGE_EXEC) ? 'x' : '-'));
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dump memory mappings */
|
|
|
|
void page_dump(FILE *f)
|
|
|
|
{
|
|
|
|
(void) fprintf(f, "%-8s %-8s %-8s %s\n",
|
|
|
|
"start", "end", "size", "prot");
|
|
|
|
walk_memory_regions(f, dump_region);
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
|
|
|
|
2006-03-25 22:31:22 +03:00
|
|
|
int page_get_flags(target_ulong address)
|
2003-08-11 01:47:01 +04:00
|
|
|
{
|
2004-01-04 21:06:42 +03:00
|
|
|
PageDesc *p;
|
|
|
|
|
|
|
|
p = page_find(address >> TARGET_PAGE_BITS);
|
2003-08-11 01:47:01 +04:00
|
|
|
if (!p)
|
2004-01-04 21:06:42 +03:00
|
|
|
return 0;
|
|
|
|
return p->flags;
|
|
|
|
}
|
|
|
|
|
2010-03-11 02:57:04 +03:00
|
|
|
/* Modify the flags of a page and invalidate the code if necessary.
|
|
|
|
The flag PAGE_WRITE_ORG is positioned automatically depending
|
|
|
|
on PAGE_WRITE. The mmap_lock should already be held. */
|
2006-03-25 22:31:22 +03:00
|
|
|
void page_set_flags(target_ulong start, target_ulong end, int flags)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2010-03-11 02:57:04 +03:00
|
|
|
target_ulong addr, len;
|
|
|
|
|
|
|
|
/* This function should never be called with addresses outside the
|
|
|
|
guest address space. If this assert fires, it probably indicates
|
|
|
|
a missing call to h2g_valid. */
|
2010-03-13 02:23:29 +03:00
|
|
|
#if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
|
|
|
|
assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
|
2010-03-11 02:57:04 +03:00
|
|
|
#endif
|
|
|
|
assert(start < end);
|
2004-01-04 21:06:42 +03:00
|
|
|
|
|
|
|
start = start & TARGET_PAGE_MASK;
|
|
|
|
end = TARGET_PAGE_ALIGN(end);
|
2010-03-11 02:57:04 +03:00
|
|
|
|
|
|
|
if (flags & PAGE_WRITE) {
|
2004-01-04 21:06:42 +03:00
|
|
|
flags |= PAGE_WRITE_ORG;
|
2010-03-11 02:57:04 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
for (addr = start, len = end - start;
|
|
|
|
len != 0;
|
|
|
|
len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
|
|
|
|
PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
|
|
|
|
|
|
|
|
/* If the write protection bit is set, then we invalidate
|
|
|
|
the code inside. */
|
2007-09-17 01:08:06 +04:00
|
|
|
if (!(p->flags & PAGE_WRITE) &&
|
2004-01-04 21:06:42 +03:00
|
|
|
(flags & PAGE_WRITE) &&
|
|
|
|
p->first_tb) {
|
2004-04-25 21:57:43 +04:00
|
|
|
tb_invalidate_phys_page(addr, 0, NULL);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
p->flags = flags;
|
|
|
|
}
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
|
|
|
|
2007-11-02 22:02:07 +03:00
|
|
|
int page_check_range(target_ulong start, target_ulong len, int flags)
|
|
|
|
{
|
|
|
|
PageDesc *p;
|
|
|
|
target_ulong end;
|
|
|
|
target_ulong addr;
|
|
|
|
|
2010-03-11 02:57:04 +03:00
|
|
|
/* This function should never be called with addresses outside the
|
|
|
|
guest address space. If this assert fires, it probably indicates
|
|
|
|
a missing call to h2g_valid. */
|
2010-03-13 12:48:08 +03:00
|
|
|
#if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
|
|
|
|
assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
|
2010-03-11 02:57:04 +03:00
|
|
|
#endif
|
|
|
|
|
2010-03-29 21:54:42 +04:00
|
|
|
if (len == 0) {
|
|
|
|
return 0;
|
|
|
|
}
|
2010-03-11 02:57:04 +03:00
|
|
|
if (start + len - 1 < start) {
|
|
|
|
/* We've wrapped around. */
|
2008-10-28 13:24:11 +03:00
|
|
|
return -1;
|
2010-03-11 02:57:04 +03:00
|
|
|
}
|
2008-10-28 13:24:11 +03:00
|
|
|
|
2007-11-02 22:02:07 +03:00
|
|
|
end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
|
|
|
|
start = start & TARGET_PAGE_MASK;
|
|
|
|
|
2010-03-11 02:57:04 +03:00
|
|
|
for (addr = start, len = end - start;
|
|
|
|
len != 0;
|
|
|
|
len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
|
2007-11-02 22:02:07 +03:00
|
|
|
p = page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if( !p )
|
|
|
|
return -1;
|
|
|
|
if( !(p->flags & PAGE_VALID) )
|
|
|
|
return -1;
|
|
|
|
|
2007-11-14 13:51:00 +03:00
|
|
|
if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
|
2007-11-02 22:02:07 +03:00
|
|
|
return -1;
|
2007-11-14 13:51:00 +03:00
|
|
|
if (flags & PAGE_WRITE) {
|
|
|
|
if (!(p->flags & PAGE_WRITE_ORG))
|
|
|
|
return -1;
|
|
|
|
/* unprotect the page if it was put read-only because it
|
|
|
|
contains translated code */
|
|
|
|
if (!(p->flags & PAGE_WRITE)) {
|
|
|
|
if (!page_unprotect(addr, 0, NULL))
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2007-11-02 22:02:07 +03:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* called from signal handler: invalidate the code and unprotect the
|
2009-05-03 15:15:06 +04:00
|
|
|
page. Return TRUE if the fault was successfully handled. */
|
2006-03-25 22:31:22 +03:00
|
|
|
int page_unprotect(target_ulong address, unsigned long pc, void *puc)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2010-03-29 04:12:51 +04:00
|
|
|
unsigned int prot;
|
|
|
|
PageDesc *p;
|
2006-03-25 22:31:22 +03:00
|
|
|
target_ulong host_start, host_end, addr;
|
2004-01-04 21:06:42 +03:00
|
|
|
|
2008-06-02 20:16:42 +04:00
|
|
|
/* Technically this isn't safe inside a signal handler. However we
|
|
|
|
know this only ever happens in a synchronous SEGV handler, so in
|
|
|
|
practice it seems to be ok. */
|
|
|
|
mmap_lock();
|
|
|
|
|
2010-03-29 04:12:51 +04:00
|
|
|
p = page_find(address >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
2008-06-02 20:16:42 +04:00
|
|
|
mmap_unlock();
|
2004-01-04 21:06:42 +03:00
|
|
|
return 0;
|
2008-06-02 20:16:42 +04:00
|
|
|
}
|
2010-03-29 04:12:51 +04:00
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* if the page was really writable, then we change its
|
|
|
|
protection back to writable */
|
2010-03-29 04:12:51 +04:00
|
|
|
if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) {
|
|
|
|
host_start = address & qemu_host_page_mask;
|
|
|
|
host_end = host_start + qemu_host_page_size;
|
|
|
|
|
|
|
|
prot = 0;
|
|
|
|
for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) {
|
|
|
|
p = page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
p->flags |= PAGE_WRITE;
|
|
|
|
prot |= p->flags;
|
|
|
|
|
2004-01-04 21:06:42 +03:00
|
|
|
/* and since the content will be modified, we must invalidate
|
|
|
|
the corresponding translated code. */
|
2010-03-29 04:12:51 +04:00
|
|
|
tb_invalidate_phys_page(addr, pc, puc);
|
2004-01-04 21:06:42 +03:00
|
|
|
#ifdef DEBUG_TB_CHECK
|
2010-03-29 04:12:51 +04:00
|
|
|
tb_invalidate_check(addr);
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
|
|
|
}
|
2010-03-29 04:12:51 +04:00
|
|
|
mprotect((void *)g2h(host_start), qemu_host_page_size,
|
|
|
|
prot & PAGE_BITS);
|
|
|
|
|
|
|
|
mmap_unlock();
|
|
|
|
return 1;
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
2008-06-02 20:16:42 +04:00
|
|
|
mmap_unlock();
|
2004-01-04 21:06:42 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-22 02:25:50 +03:00
|
|
|
static inline void tlb_set_dirty(CPUState *env,
|
|
|
|
unsigned long addr, target_ulong vaddr)
|
2004-02-06 22:46:14 +03:00
|
|
|
{
|
|
|
|
}
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif /* defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2008-06-08 05:09:01 +04:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2008-12-01 21:59:50 +03:00
|
|
|
|
2010-03-01 06:31:14 +03:00
|
|
|
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
|
|
|
|
typedef struct subpage_t {
|
2012-01-02 14:32:48 +04:00
|
|
|
MemoryRegion iomem;
|
2010-03-01 06:31:14 +03:00
|
|
|
target_phys_addr_t base;
|
2010-04-23 03:47:31 +04:00
|
|
|
ram_addr_t sub_io_index[TARGET_PAGE_SIZE];
|
|
|
|
ram_addr_t region_offset[TARGET_PAGE_SIZE];
|
2010-03-01 06:31:14 +03:00
|
|
|
} subpage_t;
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
|
|
|
ram_addr_t memory, ram_addr_t region_offset);
|
2010-04-23 03:47:31 +04:00
|
|
|
static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
|
|
|
|
ram_addr_t orig_memory,
|
|
|
|
ram_addr_t region_offset);
|
2007-05-26 21:36:03 +04:00
|
|
|
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
|
|
|
|
need_subpage) \
|
|
|
|
do { \
|
|
|
|
if (addr > start_addr) \
|
|
|
|
start_addr2 = 0; \
|
|
|
|
else { \
|
|
|
|
start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
|
|
|
|
if (start_addr2 > 0) \
|
|
|
|
need_subpage = 1; \
|
|
|
|
} \
|
|
|
|
\
|
2007-05-30 21:25:06 +04:00
|
|
|
if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
|
2007-05-26 21:36:03 +04:00
|
|
|
end_addr2 = TARGET_PAGE_SIZE - 1; \
|
|
|
|
else { \
|
|
|
|
end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
|
|
|
|
if (end_addr2 < TARGET_PAGE_SIZE - 1) \
|
|
|
|
need_subpage = 1; \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
2009-09-29 20:53:16 +04:00
|
|
|
/* register physical memory.
|
|
|
|
For RAM, 'size' must be a multiple of the target page size.
|
|
|
|
If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
|
2008-12-01 21:59:50 +03:00
|
|
|
io memory page. The address used when calling the IO function is
|
|
|
|
the offset from the start of the region, plus region_offset. Both
|
2009-05-03 15:15:06 +04:00
|
|
|
start_addr and region_offset are rounded down to a page boundary
|
2008-12-01 21:59:50 +03:00
|
|
|
before calculating this offset. This should not be a problem unless
|
|
|
|
the low bits of start_addr and region_offset differ. */
|
2012-01-02 14:17:03 +04:00
|
|
|
void cpu_register_physical_memory_log(MemoryRegionSection *section,
|
|
|
|
bool readable, bool readonly)
|
2003-08-11 01:47:01 +04:00
|
|
|
{
|
2012-01-02 14:17:03 +04:00
|
|
|
target_phys_addr_t start_addr = section->offset_within_address_space;
|
|
|
|
ram_addr_t size = section->size;
|
|
|
|
ram_addr_t phys_offset = section->mr->ram_addr;
|
|
|
|
ram_addr_t region_offset = section->offset_within_region;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t addr, end_addr;
|
2004-05-21 18:52:29 +04:00
|
|
|
PhysPageDesc *p;
|
2006-06-26 02:25:22 +04:00
|
|
|
CPUState *env;
|
2009-10-02 01:12:16 +04:00
|
|
|
ram_addr_t orig_size = size;
|
2010-04-23 03:47:31 +04:00
|
|
|
subpage_t *subpage;
|
2003-08-11 01:47:01 +04:00
|
|
|
|
2012-01-02 14:17:03 +04:00
|
|
|
if (memory_region_is_ram(section->mr)) {
|
|
|
|
phys_offset += region_offset;
|
|
|
|
region_offset = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (readonly) {
|
|
|
|
phys_offset |= io_mem_rom.ram_addr;
|
|
|
|
}
|
|
|
|
|
2011-04-05 15:00:36 +04:00
|
|
|
assert(size);
|
2010-01-27 23:06:57 +03:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if (phys_offset == io_mem_unassigned.ram_addr) {
|
2009-02-23 16:16:07 +03:00
|
|
|
region_offset = start_addr;
|
|
|
|
}
|
2008-12-01 21:59:50 +03:00
|
|
|
region_offset &= TARGET_PAGE_MASK;
|
2004-05-24 01:11:22 +04:00
|
|
|
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
2009-10-02 01:12:16 +04:00
|
|
|
end_addr = start_addr + (target_phys_addr_t)size;
|
2011-04-05 15:00:36 +04:00
|
|
|
|
|
|
|
addr = start_addr;
|
|
|
|
do {
|
2011-11-20 19:52:22 +04:00
|
|
|
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 0);
|
2012-01-02 02:32:15 +04:00
|
|
|
if (p && p->phys_offset != io_mem_unassigned.ram_addr) {
|
2009-10-02 01:12:16 +04:00
|
|
|
ram_addr_t orig_memory = p->phys_offset;
|
|
|
|
target_phys_addr_t start_addr2, end_addr2;
|
2007-05-26 21:36:03 +04:00
|
|
|
int need_subpage = 0;
|
2012-01-02 19:21:07 +04:00
|
|
|
MemoryRegion *mr = io_mem_region[orig_memory & ~TARGET_PAGE_MASK];
|
2007-05-26 21:36:03 +04:00
|
|
|
|
|
|
|
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
|
|
|
|
need_subpage);
|
2010-04-23 03:47:31 +04:00
|
|
|
if (need_subpage) {
|
2012-01-02 15:20:11 +04:00
|
|
|
if (!(mr->subpage)) {
|
2007-05-26 21:36:03 +04:00
|
|
|
subpage = subpage_init((addr & TARGET_PAGE_MASK),
|
2008-12-01 21:59:50 +03:00
|
|
|
&p->phys_offset, orig_memory,
|
|
|
|
p->region_offset);
|
2007-05-26 21:36:03 +04:00
|
|
|
} else {
|
2012-01-02 15:12:08 +04:00
|
|
|
subpage = container_of(mr, subpage_t, iomem);
|
2007-05-26 21:36:03 +04:00
|
|
|
}
|
2008-12-01 21:59:50 +03:00
|
|
|
subpage_register(subpage, start_addr2, end_addr2, phys_offset,
|
|
|
|
region_offset);
|
|
|
|
p->region_offset = 0;
|
2007-05-26 21:36:03 +04:00
|
|
|
} else {
|
|
|
|
p->phys_offset = phys_offset;
|
2012-01-01 20:24:24 +04:00
|
|
|
p->region_offset = region_offset;
|
2012-01-01 23:15:42 +04:00
|
|
|
if (is_ram_rom_romd(phys_offset))
|
2007-05-26 21:36:03 +04:00
|
|
|
phys_offset += TARGET_PAGE_SIZE;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
|
|
|
|
p->phys_offset = phys_offset;
|
2008-12-01 21:59:50 +03:00
|
|
|
p->region_offset = region_offset;
|
2012-01-01 23:15:42 +04:00
|
|
|
if (is_ram_rom_romd(phys_offset)) {
|
2007-05-26 21:36:03 +04:00
|
|
|
phys_offset += TARGET_PAGE_SIZE;
|
2008-12-02 12:02:15 +03:00
|
|
|
} else {
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t start_addr2, end_addr2;
|
2007-05-26 21:36:03 +04:00
|
|
|
int need_subpage = 0;
|
|
|
|
|
|
|
|
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
|
|
|
|
end_addr2, need_subpage);
|
|
|
|
|
2010-04-23 03:47:31 +04:00
|
|
|
if (need_subpage) {
|
2007-05-26 21:36:03 +04:00
|
|
|
subpage = subpage_init((addr & TARGET_PAGE_MASK),
|
2012-01-02 02:32:15 +04:00
|
|
|
&p->phys_offset,
|
|
|
|
io_mem_unassigned.ram_addr,
|
2009-02-23 16:16:07 +03:00
|
|
|
addr & TARGET_PAGE_MASK);
|
2007-05-26 21:36:03 +04:00
|
|
|
subpage_register(subpage, start_addr2, end_addr2,
|
2008-12-01 21:59:50 +03:00
|
|
|
phys_offset, region_offset);
|
|
|
|
p->region_offset = 0;
|
2007-05-26 21:36:03 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-12-01 21:59:50 +03:00
|
|
|
region_offset += TARGET_PAGE_SIZE;
|
2011-04-05 15:00:36 +04:00
|
|
|
addr += TARGET_PAGE_SIZE;
|
|
|
|
} while (addr != end_addr);
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2006-06-26 02:25:22 +04:00
|
|
|
/* since each CPU stores ram addresses in its TLB cache, we must
|
|
|
|
reset the modified entries */
|
|
|
|
/* XXX: slow ! */
|
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
|
2008-12-09 23:09:57 +03:00
|
|
|
{
|
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_coalesce_mmio_region(addr, size);
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
|
2008-12-09 23:09:57 +03:00
|
|
|
{
|
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_uncoalesce_mmio_region(addr, size);
|
|
|
|
}
|
|
|
|
|
2010-01-26 14:21:16 +03:00
|
|
|
void qemu_flush_coalesced_mmio_buffer(void)
|
|
|
|
{
|
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_flush_coalesced_mmio_buffer();
|
|
|
|
}
|
|
|
|
|
2010-03-02 02:25:08 +03:00
|
|
|
#if defined(__linux__) && !defined(TARGET_S390X)
|
|
|
|
|
|
|
|
#include <sys/vfs.h>
|
|
|
|
|
|
|
|
#define HUGETLBFS_MAGIC 0x958458f6
|
|
|
|
|
|
|
|
static long gethugepagesize(const char *path)
|
|
|
|
{
|
|
|
|
struct statfs fs;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
do {
|
2010-08-18 08:30:13 +04:00
|
|
|
ret = statfs(path, &fs);
|
2010-03-02 02:25:08 +03:00
|
|
|
} while (ret != 0 && errno == EINTR);
|
|
|
|
|
|
|
|
if (ret != 0) {
|
2010-08-18 08:30:13 +04:00
|
|
|
perror(path);
|
|
|
|
return 0;
|
2010-03-02 02:25:08 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (fs.f_type != HUGETLBFS_MAGIC)
|
2010-08-18 08:30:13 +04:00
|
|
|
fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
|
2010-03-02 02:25:08 +03:00
|
|
|
|
|
|
|
return fs.f_bsize;
|
|
|
|
}
|
|
|
|
|
2010-07-02 21:13:17 +04:00
|
|
|
static void *file_ram_alloc(RAMBlock *block,
|
|
|
|
ram_addr_t memory,
|
|
|
|
const char *path)
|
2010-03-02 02:25:08 +03:00
|
|
|
{
|
|
|
|
char *filename;
|
|
|
|
void *area;
|
|
|
|
int fd;
|
|
|
|
#ifdef MAP_POPULATE
|
|
|
|
int flags;
|
|
|
|
#endif
|
|
|
|
unsigned long hpagesize;
|
|
|
|
|
|
|
|
hpagesize = gethugepagesize(path);
|
|
|
|
if (!hpagesize) {
|
2010-08-18 08:30:13 +04:00
|
|
|
return NULL;
|
2010-03-02 02:25:08 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (memory < hpagesize) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (kvm_enabled() && !kvm_has_sync_mmu()) {
|
|
|
|
fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) {
|
2010-08-18 08:30:13 +04:00
|
|
|
return NULL;
|
2010-03-02 02:25:08 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
fd = mkstemp(filename);
|
|
|
|
if (fd < 0) {
|
2010-08-18 08:30:13 +04:00
|
|
|
perror("unable to create backing store for hugepages");
|
|
|
|
free(filename);
|
|
|
|
return NULL;
|
2010-03-02 02:25:08 +03:00
|
|
|
}
|
|
|
|
unlink(filename);
|
|
|
|
free(filename);
|
|
|
|
|
|
|
|
memory = (memory+hpagesize-1) & ~(hpagesize-1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ftruncate is not supported by hugetlbfs in older
|
|
|
|
* hosts, so don't bother bailing out on errors.
|
|
|
|
* If anything goes wrong with it under other filesystems,
|
|
|
|
* mmap will fail.
|
|
|
|
*/
|
|
|
|
if (ftruncate(fd, memory))
|
2010-08-18 08:30:13 +04:00
|
|
|
perror("ftruncate");
|
2010-03-02 02:25:08 +03:00
|
|
|
|
|
|
|
#ifdef MAP_POPULATE
|
|
|
|
/* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case
|
|
|
|
* MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED
|
|
|
|
* to sidestep this quirk.
|
|
|
|
*/
|
|
|
|
flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE;
|
|
|
|
area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0);
|
|
|
|
#else
|
|
|
|
area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
|
|
|
|
#endif
|
|
|
|
if (area == MAP_FAILED) {
|
2010-08-18 08:30:13 +04:00
|
|
|
perror("file_ram_alloc: can't mmap RAM pages");
|
|
|
|
close(fd);
|
|
|
|
return (NULL);
|
2010-03-02 02:25:08 +03:00
|
|
|
}
|
2010-07-02 21:13:17 +04:00
|
|
|
block->fd = fd;
|
2010-03-02 02:25:08 +03:00
|
|
|
return area;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-06-25 21:08:38 +04:00
|
|
|
static ram_addr_t find_ram_offset(ram_addr_t size)
|
2010-07-02 21:13:17 +04:00
|
|
|
{
|
|
|
|
RAMBlock *block, *next_block;
|
2011-10-31 18:54:09 +04:00
|
|
|
ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
|
2010-07-02 21:13:17 +04:00
|
|
|
|
|
|
|
if (QLIST_EMPTY(&ram_list.blocks))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
2011-07-20 12:17:42 +04:00
|
|
|
ram_addr_t end, next = RAM_ADDR_MAX;
|
2010-07-02 21:13:17 +04:00
|
|
|
|
|
|
|
end = block->offset + block->length;
|
|
|
|
|
|
|
|
QLIST_FOREACH(next_block, &ram_list.blocks, next) {
|
|
|
|
if (next_block->offset >= end) {
|
|
|
|
next = MIN(next, next_block->offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (next - end >= size && next - end < mingap) {
|
2011-10-31 18:54:09 +04:00
|
|
|
offset = end;
|
2010-07-02 21:13:17 +04:00
|
|
|
mingap = next - end;
|
|
|
|
}
|
|
|
|
}
|
2011-10-31 18:54:09 +04:00
|
|
|
|
|
|
|
if (offset == RAM_ADDR_MAX) {
|
|
|
|
fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
|
|
|
|
(uint64_t)size);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2010-07-02 21:13:17 +04:00
|
|
|
return offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ram_addr_t last_ram_offset(void)
|
2010-06-25 21:08:38 +04:00
|
|
|
{
|
|
|
|
RAMBlock *block;
|
|
|
|
ram_addr_t last = 0;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next)
|
|
|
|
last = MAX(last, block->offset + block->length);
|
|
|
|
|
|
|
|
return last;
|
|
|
|
}
|
|
|
|
|
2011-12-20 17:59:12 +04:00
|
|
|
void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev)
|
2010-07-27 04:10:57 +04:00
|
|
|
{
|
|
|
|
RAMBlock *new_block, *block;
|
|
|
|
|
2011-12-20 17:59:12 +04:00
|
|
|
new_block = NULL;
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
if (block->offset == addr) {
|
|
|
|
new_block = block;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(new_block);
|
|
|
|
assert(!new_block->idstr[0]);
|
2010-07-27 04:10:57 +04:00
|
|
|
|
|
|
|
if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
|
|
|
|
char *id = dev->parent_bus->info->get_dev_path(dev);
|
|
|
|
if (id) {
|
|
|
|
snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(id);
|
2010-07-27 04:10:57 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
2011-12-20 17:59:12 +04:00
|
|
|
if (block != new_block && !strcmp(block->idstr, new_block->idstr)) {
|
2010-07-27 04:10:57 +04:00
|
|
|
fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
|
|
|
|
new_block->idstr);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
2011-12-20 17:59:12 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
|
|
|
|
MemoryRegion *mr)
|
|
|
|
{
|
|
|
|
RAMBlock *new_block;
|
|
|
|
|
|
|
|
size = TARGET_PAGE_ALIGN(size);
|
|
|
|
new_block = g_malloc0(sizeof(*new_block));
|
2010-07-27 04:10:57 +04:00
|
|
|
|
2011-12-21 15:09:49 +04:00
|
|
|
new_block->mr = mr;
|
2010-08-31 19:41:25 +04:00
|
|
|
new_block->offset = find_ram_offset(size);
|
2010-08-18 10:41:49 +04:00
|
|
|
if (host) {
|
|
|
|
new_block->host = host;
|
2011-03-02 10:56:19 +03:00
|
|
|
new_block->flags |= RAM_PREALLOC_MASK;
|
2010-08-18 10:41:49 +04:00
|
|
|
} else {
|
|
|
|
if (mem_path) {
|
2010-03-02 02:25:08 +03:00
|
|
|
#if defined (__linux__) && !defined(TARGET_S390X)
|
2010-08-18 10:41:49 +04:00
|
|
|
new_block->host = file_ram_alloc(new_block, size, mem_path);
|
|
|
|
if (!new_block->host) {
|
|
|
|
new_block->host = qemu_vmalloc(size);
|
2010-09-25 15:26:05 +04:00
|
|
|
qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE);
|
2010-08-18 10:41:49 +04:00
|
|
|
}
|
2010-03-02 02:25:08 +03:00
|
|
|
#else
|
2010-08-18 10:41:49 +04:00
|
|
|
fprintf(stderr, "-mem-path option unsupported\n");
|
|
|
|
exit(1);
|
2010-03-02 02:25:08 +03:00
|
|
|
#endif
|
2010-08-18 10:41:49 +04:00
|
|
|
} else {
|
2009-12-05 14:44:25 +03:00
|
|
|
#if defined(TARGET_S390X) && defined(CONFIG_KVM)
|
2011-05-10 16:49:10 +04:00
|
|
|
/* S390 KVM requires the topmost vma of the RAM to be smaller than
|
|
|
|
an system defined value, which is at least 256GB. Larger systems
|
|
|
|
have larger values. We put the guest between the end of data
|
|
|
|
segment (system break) and this value. We use 32GB as a base to
|
|
|
|
have enough room for the system break to grow. */
|
|
|
|
new_block->host = mmap((void*)0x800000000, size,
|
2010-08-18 10:41:49 +04:00
|
|
|
PROT_EXEC|PROT_READ|PROT_WRITE,
|
2011-05-10 16:49:10 +04:00
|
|
|
MAP_SHARED | MAP_ANONYMOUS | MAP_FIXED, -1, 0);
|
2011-05-20 19:33:28 +04:00
|
|
|
if (new_block->host == MAP_FAILED) {
|
|
|
|
fprintf(stderr, "Allocating RAM failed\n");
|
|
|
|
abort();
|
|
|
|
}
|
2009-12-05 14:44:25 +03:00
|
|
|
#else
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2011-12-18 17:48:55 +04:00
|
|
|
xen_ram_alloc(new_block->offset, size, mr);
|
2010-08-31 19:41:25 +04:00
|
|
|
} else {
|
|
|
|
new_block->host = qemu_vmalloc(size);
|
|
|
|
}
|
2009-12-05 14:44:25 +03:00
|
|
|
#endif
|
2010-09-25 15:26:05 +04:00
|
|
|
qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE);
|
2010-08-18 10:41:49 +04:00
|
|
|
}
|
2010-03-02 02:25:08 +03:00
|
|
|
}
|
2009-04-11 21:15:54 +04:00
|
|
|
new_block->length = size;
|
|
|
|
|
2010-06-11 21:11:42 +04:00
|
|
|
QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next);
|
2009-04-11 21:15:54 +04:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
ram_list.phys_dirty = g_realloc(ram_list.phys_dirty,
|
2010-07-02 21:13:17 +04:00
|
|
|
last_ram_offset() >> TARGET_PAGE_BITS);
|
2010-06-25 21:08:38 +04:00
|
|
|
memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS),
|
2009-04-11 21:15:54 +04:00
|
|
|
0xff, size >> TARGET_PAGE_BITS);
|
|
|
|
|
2009-04-26 20:03:40 +04:00
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_setup_guest_memory(new_block->host, size);
|
|
|
|
|
2009-04-11 21:15:54 +04:00
|
|
|
return new_block->offset;
|
|
|
|
}
|
2007-02-09 02:08:38 +03:00
|
|
|
|
2011-12-20 17:59:12 +04:00
|
|
|
ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr)
|
2010-08-18 10:41:49 +04:00
|
|
|
{
|
2011-12-20 17:59:12 +04:00
|
|
|
return qemu_ram_alloc_from_ptr(size, NULL, mr);
|
2010-08-18 10:41:49 +04:00
|
|
|
}
|
|
|
|
|
2011-05-03 22:48:09 +04:00
|
|
|
void qemu_ram_free_from_ptr(ram_addr_t addr)
|
|
|
|
{
|
|
|
|
RAMBlock *block;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
if (addr == block->offset) {
|
|
|
|
QLIST_REMOVE(block, next);
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(block);
|
2011-05-03 22:48:09 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
void qemu_ram_free(ram_addr_t addr)
|
2007-02-09 02:08:38 +03:00
|
|
|
{
|
2010-07-02 21:13:17 +04:00
|
|
|
RAMBlock *block;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
if (addr == block->offset) {
|
|
|
|
QLIST_REMOVE(block, next);
|
2011-03-02 10:56:19 +03:00
|
|
|
if (block->flags & RAM_PREALLOC_MASK) {
|
|
|
|
;
|
|
|
|
} else if (mem_path) {
|
2010-07-02 21:13:17 +04:00
|
|
|
#if defined (__linux__) && !defined(TARGET_S390X)
|
|
|
|
if (block->fd) {
|
|
|
|
munmap(block->host, block->length);
|
|
|
|
close(block->fd);
|
|
|
|
} else {
|
|
|
|
qemu_vfree(block->host);
|
|
|
|
}
|
2011-03-15 14:26:14 +03:00
|
|
|
#else
|
|
|
|
abort();
|
2010-07-02 21:13:17 +04:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
#if defined(TARGET_S390X) && defined(CONFIG_KVM)
|
|
|
|
munmap(block->host, block->length);
|
|
|
|
#else
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2011-06-22 00:59:08 +04:00
|
|
|
xen_invalidate_map_cache_entry(block->host);
|
2010-08-31 19:41:25 +04:00
|
|
|
} else {
|
|
|
|
qemu_vfree(block->host);
|
|
|
|
}
|
2010-07-02 21:13:17 +04:00
|
|
|
#endif
|
|
|
|
}
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(block);
|
2010-07-02 21:13:17 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-02-09 02:08:38 +03:00
|
|
|
}
|
|
|
|
|
2011-03-02 10:56:19 +03:00
|
|
|
#ifndef _WIN32
|
|
|
|
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
|
|
|
|
{
|
|
|
|
RAMBlock *block;
|
|
|
|
ram_addr_t offset;
|
|
|
|
int flags;
|
|
|
|
void *area, *vaddr;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
offset = addr - block->offset;
|
|
|
|
if (offset < block->length) {
|
|
|
|
vaddr = block->host + offset;
|
|
|
|
if (block->flags & RAM_PREALLOC_MASK) {
|
|
|
|
;
|
|
|
|
} else {
|
|
|
|
flags = MAP_FIXED;
|
|
|
|
munmap(vaddr, length);
|
|
|
|
if (mem_path) {
|
|
|
|
#if defined(__linux__) && !defined(TARGET_S390X)
|
|
|
|
if (block->fd) {
|
|
|
|
#ifdef MAP_POPULATE
|
|
|
|
flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED :
|
|
|
|
MAP_PRIVATE;
|
|
|
|
#else
|
|
|
|
flags |= MAP_PRIVATE;
|
|
|
|
#endif
|
|
|
|
area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
|
|
|
|
flags, block->fd, offset);
|
|
|
|
} else {
|
|
|
|
flags |= MAP_PRIVATE | MAP_ANONYMOUS;
|
|
|
|
area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
|
|
|
|
flags, -1, 0);
|
|
|
|
}
|
2011-03-15 14:26:14 +03:00
|
|
|
#else
|
|
|
|
abort();
|
2011-03-02 10:56:19 +03:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
#if defined(TARGET_S390X) && defined(CONFIG_KVM)
|
|
|
|
flags |= MAP_SHARED | MAP_ANONYMOUS;
|
|
|
|
area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE,
|
|
|
|
flags, -1, 0);
|
|
|
|
#else
|
|
|
|
flags |= MAP_PRIVATE | MAP_ANONYMOUS;
|
|
|
|
area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
|
|
|
|
flags, -1, 0);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
if (area != vaddr) {
|
2011-07-20 12:17:42 +04:00
|
|
|
fprintf(stderr, "Could not remap addr: "
|
|
|
|
RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
|
2011-03-02 10:56:19 +03:00
|
|
|
length, addr);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* !_WIN32 */
|
|
|
|
|
2009-04-10 02:21:07 +04:00
|
|
|
/* Return a host pointer to ram allocated with qemu_ram_alloc.
|
2009-04-11 18:47:08 +04:00
|
|
|
With the exception of the softmmu code in this file, this should
|
|
|
|
only be used for local memory (e.g. video ram) that the device owns,
|
|
|
|
and knows it isn't going to access beyond the end of the block.
|
|
|
|
|
|
|
|
It should not be used for general purpose DMA.
|
|
|
|
Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
|
|
|
|
*/
|
2009-10-02 01:12:16 +04:00
|
|
|
void *qemu_get_ram_ptr(ram_addr_t addr)
|
2009-04-10 02:21:07 +04:00
|
|
|
{
|
2009-04-11 21:15:54 +04:00
|
|
|
RAMBlock *block;
|
|
|
|
|
2010-06-11 21:11:42 +04:00
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
if (addr - block->offset < block->length) {
|
2011-03-10 23:47:46 +03:00
|
|
|
/* Move this entry to to start of the list. */
|
|
|
|
if (block != QLIST_FIRST(&ram_list.blocks)) {
|
|
|
|
QLIST_REMOVE(block, next);
|
|
|
|
QLIST_INSERT_HEAD(&ram_list.blocks, block, next);
|
|
|
|
}
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2010-08-31 19:41:25 +04:00
|
|
|
/* We need to check if the requested address is in the RAM
|
|
|
|
* because we don't want to map the entire memory in QEMU.
|
2011-05-19 21:35:46 +04:00
|
|
|
* In that case just map until the end of the page.
|
2010-08-31 19:41:25 +04:00
|
|
|
*/
|
|
|
|
if (block->offset == 0) {
|
2011-06-22 00:59:08 +04:00
|
|
|
return xen_map_cache(addr, 0, 0);
|
2010-08-31 19:41:25 +04:00
|
|
|
} else if (block->host == NULL) {
|
2011-06-22 00:59:08 +04:00
|
|
|
block->host =
|
|
|
|
xen_map_cache(block->offset, block->length, 1);
|
2010-08-31 19:41:25 +04:00
|
|
|
}
|
|
|
|
}
|
2010-06-11 21:11:42 +04:00
|
|
|
return block->host + (addr - block->offset);
|
|
|
|
}
|
2009-04-11 21:15:54 +04:00
|
|
|
}
|
2010-06-11 21:11:42 +04:00
|
|
|
|
|
|
|
fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
|
|
|
|
abort();
|
|
|
|
|
|
|
|
return NULL;
|
2009-04-10 02:21:07 +04:00
|
|
|
}
|
|
|
|
|
2010-11-22 20:52:34 +03:00
|
|
|
/* Return a host pointer to ram allocated with qemu_ram_alloc.
|
|
|
|
* Same as qemu_get_ram_ptr but avoid reordering ramblocks.
|
|
|
|
*/
|
|
|
|
void *qemu_safe_ram_ptr(ram_addr_t addr)
|
|
|
|
{
|
|
|
|
RAMBlock *block;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
if (addr - block->offset < block->length) {
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2010-08-31 19:41:25 +04:00
|
|
|
/* We need to check if the requested address is in the RAM
|
|
|
|
* because we don't want to map the entire memory in QEMU.
|
2011-05-19 21:35:46 +04:00
|
|
|
* In that case just map until the end of the page.
|
2010-08-31 19:41:25 +04:00
|
|
|
*/
|
|
|
|
if (block->offset == 0) {
|
2011-06-22 00:59:08 +04:00
|
|
|
return xen_map_cache(addr, 0, 0);
|
2010-08-31 19:41:25 +04:00
|
|
|
} else if (block->host == NULL) {
|
2011-06-22 00:59:08 +04:00
|
|
|
block->host =
|
|
|
|
xen_map_cache(block->offset, block->length, 1);
|
2010-08-31 19:41:25 +04:00
|
|
|
}
|
|
|
|
}
|
2010-11-22 20:52:34 +03:00
|
|
|
return block->host + (addr - block->offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
|
|
|
|
abort();
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2011-05-19 21:35:45 +04:00
|
|
|
/* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr
|
|
|
|
* but takes a size argument */
|
2011-06-27 21:26:06 +04:00
|
|
|
void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size)
|
2011-05-19 21:35:45 +04:00
|
|
|
{
|
2011-06-27 21:26:06 +04:00
|
|
|
if (*size == 0) {
|
|
|
|
return NULL;
|
|
|
|
}
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2011-06-22 00:59:08 +04:00
|
|
|
return xen_map_cache(addr, *size, 1);
|
2011-06-22 00:59:09 +04:00
|
|
|
} else {
|
2011-05-19 21:35:45 +04:00
|
|
|
RAMBlock *block;
|
|
|
|
|
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
|
|
|
if (addr - block->offset < block->length) {
|
|
|
|
if (addr - block->offset + *size > block->length)
|
|
|
|
*size = block->length - addr + block->offset;
|
|
|
|
return block->host + (addr - block->offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-16 16:57:49 +04:00
|
|
|
void qemu_put_ram_ptr(void *addr)
|
|
|
|
{
|
|
|
|
trace_qemu_put_ram_ptr(addr);
|
|
|
|
}
|
|
|
|
|
2010-10-11 22:31:19 +04:00
|
|
|
int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
|
2009-04-11 18:47:08 +04:00
|
|
|
{
|
2009-04-11 21:15:54 +04:00
|
|
|
RAMBlock *block;
|
|
|
|
uint8_t *host = ptr;
|
|
|
|
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2011-06-22 00:59:08 +04:00
|
|
|
*ram_addr = xen_ram_addr_from_mapcache(ptr);
|
2011-05-19 21:35:46 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-11 21:11:42 +04:00
|
|
|
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
2010-08-31 19:41:25 +04:00
|
|
|
/* This case append when the block is not mapped. */
|
|
|
|
if (block->host == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
2010-06-11 21:11:42 +04:00
|
|
|
if (host - block->host < block->length) {
|
2010-10-11 22:31:19 +04:00
|
|
|
*ram_addr = block->offset + (host - block->host);
|
|
|
|
return 0;
|
2010-06-11 21:11:42 +04:00
|
|
|
}
|
2009-04-11 21:15:54 +04:00
|
|
|
}
|
2010-08-31 19:41:25 +04:00
|
|
|
|
2010-10-11 22:31:19 +04:00
|
|
|
return -1;
|
|
|
|
}
|
2010-06-11 21:11:42 +04:00
|
|
|
|
2010-10-11 22:31:19 +04:00
|
|
|
/* Some of the softmmu routines need to translate from a host pointer
|
|
|
|
(typically a TLB entry) back to a ram offset. */
|
|
|
|
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
|
|
|
|
{
|
|
|
|
ram_addr_t ram_addr;
|
2010-06-11 21:11:42 +04:00
|
|
|
|
2010-10-11 22:31:19 +04:00
|
|
|
if (qemu_ram_addr_from_host(ptr, &ram_addr)) {
|
|
|
|
fprintf(stderr, "Bad ram pointer %p\n", ptr);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
return ram_addr;
|
2009-04-11 18:47:08 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
2008-10-06 22:46:28 +04:00
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
|
|
|
#endif
|
2011-04-19 03:13:12 +04:00
|
|
|
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
2012-01-02 02:32:15 +04:00
|
|
|
cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
|
2008-10-06 22:46:28 +04:00
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t val, unsigned size)
|
2008-10-06 22:46:28 +04:00
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
2012-01-02 02:32:15 +04:00
|
|
|
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
|
2008-10-06 22:46:28 +04:00
|
|
|
#endif
|
2011-04-19 03:13:12 +04:00
|
|
|
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
2012-01-02 02:32:15 +04:00
|
|
|
cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
|
2006-12-18 08:03:52 +03:00
|
|
|
#endif
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static const MemoryRegionOps unassigned_mem_ops = {
|
|
|
|
.read = unassigned_mem_read,
|
|
|
|
.write = unassigned_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
2008-10-06 22:46:28 +04:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
2008-10-06 22:46:28 +04:00
|
|
|
{
|
2012-01-02 02:32:15 +04:00
|
|
|
abort();
|
2008-10-06 22:46:28 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static void error_mem_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t value, unsigned size)
|
2008-10-06 22:46:28 +04:00
|
|
|
{
|
2012-01-02 02:32:15 +04:00
|
|
|
abort();
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static const MemoryRegionOps error_mem_ops = {
|
|
|
|
.read = error_mem_read,
|
|
|
|
.write = error_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2003-08-11 01:47:01 +04:00
|
|
|
};
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static const MemoryRegionOps rom_mem_ops = {
|
|
|
|
.read = error_mem_read,
|
|
|
|
.write = unassigned_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2003-08-11 01:47:01 +04:00
|
|
|
};
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
|
|
|
|
uint64_t val, unsigned size)
|
2004-01-04 21:06:42 +03:00
|
|
|
{
|
2005-08-21 13:26:42 +04:00
|
|
|
int dirty_flags;
|
2010-03-23 10:39:53 +03:00
|
|
|
dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
2005-08-21 13:26:42 +04:00
|
|
|
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
2004-01-04 21:06:42 +03:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2012-01-02 02:32:15 +04:00
|
|
|
tb_invalidate_phys_page_fast(ram_addr, size);
|
2010-03-23 10:39:53 +03:00
|
|
|
dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
2004-01-04 21:06:42 +03:00
|
|
|
#endif
|
2005-08-21 13:26:42 +04:00
|
|
|
}
|
2012-01-02 02:32:15 +04:00
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
stb_p(qemu_get_ram_ptr(ram_addr), val);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
stw_p(qemu_get_ram_ptr(ram_addr), val);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
stl_p(qemu_get_ram_ptr(ram_addr), val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
abort();
|
2005-08-21 13:26:42 +04:00
|
|
|
}
|
2005-08-21 23:12:28 +04:00
|
|
|
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
|
2005-08-21 23:12:28 +04:00
|
|
|
/* we remove the notdirty callback only if the code has been
|
|
|
|
flushed */
|
|
|
|
if (dirty_flags == 0xff)
|
2008-06-29 05:03:05 +04:00
|
|
|
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
2004-01-04 21:06:42 +03:00
|
|
|
}
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
static const MemoryRegionOps notdirty_mem_ops = {
|
|
|
|
.read = error_mem_read,
|
|
|
|
.write = notdirty_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2004-02-06 22:46:14 +03:00
|
|
|
};
|
|
|
|
|
2008-06-09 04:20:13 +04:00
|
|
|
/* Generate a debug exception if a watchpoint has been hit. */
|
2008-11-18 23:14:20 +03:00
|
|
|
static void check_watchpoint(int offset, int len_mask, int flags)
|
2008-06-09 04:20:13 +04:00
|
|
|
{
|
|
|
|
CPUState *env = cpu_single_env;
|
2008-11-18 23:24:06 +03:00
|
|
|
target_ulong pc, cs_base;
|
|
|
|
TranslationBlock *tb;
|
2008-06-09 04:20:13 +04:00
|
|
|
target_ulong vaddr;
|
2008-11-18 23:07:32 +03:00
|
|
|
CPUWatchpoint *wp;
|
2008-11-18 23:24:06 +03:00
|
|
|
int cpu_flags;
|
2008-06-09 04:20:13 +04:00
|
|
|
|
2008-11-18 23:24:06 +03:00
|
|
|
if (env->watchpoint_hit) {
|
|
|
|
/* We re-entered the check after replacing the TB. Now raise
|
|
|
|
* the debug interrupt so that is will trigger after the
|
|
|
|
* current instruction. */
|
|
|
|
cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
|
|
|
|
return;
|
|
|
|
}
|
2008-06-29 05:03:05 +04:00
|
|
|
vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
|
2009-09-12 11:36:22 +04:00
|
|
|
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
2008-11-18 23:14:20 +03:00
|
|
|
if ((vaddr == (wp->vaddr & len_mask) ||
|
|
|
|
(vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
|
2008-11-18 23:37:55 +03:00
|
|
|
wp->flags |= BP_WATCHPOINT_HIT;
|
|
|
|
if (!env->watchpoint_hit) {
|
|
|
|
env->watchpoint_hit = wp;
|
|
|
|
tb = tb_find_pc(env->mem_io_pc);
|
|
|
|
if (!tb) {
|
|
|
|
cpu_abort(env, "check_watchpoint: could not find TB for "
|
|
|
|
"pc=%p", (void *)env->mem_io_pc);
|
|
|
|
}
|
2011-04-18 10:39:53 +04:00
|
|
|
cpu_restore_state(tb, env, env->mem_io_pc);
|
2008-11-18 23:37:55 +03:00
|
|
|
tb_phys_invalidate(tb, -1);
|
|
|
|
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
|
|
|
|
env->exception_index = EXCP_DEBUG;
|
|
|
|
} else {
|
|
|
|
cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
|
|
|
|
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
|
|
|
|
}
|
|
|
|
cpu_resume_from_signal(env, NULL);
|
2008-11-18 23:24:06 +03:00
|
|
|
}
|
2008-11-18 23:37:55 +03:00
|
|
|
} else {
|
|
|
|
wp->flags &= ~BP_WATCHPOINT_HIT;
|
2008-06-09 04:20:13 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 02:58:11 +03:00
|
|
|
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
|
|
|
|
so these check for a hit then pass through to the normal out-of-line
|
|
|
|
phys routines. */
|
2012-01-02 14:47:48 +04:00
|
|
|
static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
2007-03-17 02:58:11 +03:00
|
|
|
{
|
2012-01-02 14:47:48 +04:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
|
|
|
|
switch (size) {
|
|
|
|
case 1: return ldub_phys(addr);
|
|
|
|
case 2: return lduw_phys(addr);
|
|
|
|
case 4: return ldl_phys(addr);
|
|
|
|
default: abort();
|
|
|
|
}
|
2007-03-17 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2012-01-02 14:47:48 +04:00
|
|
|
static void watch_mem_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t val, unsigned size)
|
2007-03-17 02:58:11 +03:00
|
|
|
{
|
2012-01-02 14:47:48 +04:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
|
|
|
|
switch (size) {
|
|
|
|
case 1: stb_phys(addr, val);
|
|
|
|
case 2: stw_phys(addr, val);
|
|
|
|
case 4: stl_phys(addr, val);
|
|
|
|
default: abort();
|
|
|
|
}
|
2007-03-17 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2012-01-02 14:47:48 +04:00
|
|
|
static const MemoryRegionOps watch_mem_ops = {
|
|
|
|
.read = watch_mem_read,
|
|
|
|
.write = watch_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-03-17 02:58:11 +03:00
|
|
|
};
|
|
|
|
|
2012-01-02 14:32:48 +04:00
|
|
|
static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned len)
|
2007-05-26 21:36:03 +04:00
|
|
|
{
|
2012-01-02 14:32:48 +04:00
|
|
|
subpage_t *mmio = opaque;
|
2010-04-23 03:47:31 +04:00
|
|
|
unsigned int idx = SUBPAGE_IDX(addr);
|
2007-05-26 21:36:03 +04:00
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
|
|
|
|
mmio, len, addr, idx);
|
|
|
|
#endif
|
|
|
|
|
2010-04-23 03:47:31 +04:00
|
|
|
addr += mmio->region_offset[idx];
|
|
|
|
idx = mmio->sub_io_index[idx];
|
2012-01-02 14:32:48 +04:00
|
|
|
return io_mem_read(idx, addr, len);
|
2007-05-26 21:36:03 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 14:32:48 +04:00
|
|
|
static void subpage_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t value, unsigned len)
|
2007-05-26 21:36:03 +04:00
|
|
|
{
|
2012-01-02 14:32:48 +04:00
|
|
|
subpage_t *mmio = opaque;
|
2010-04-23 03:47:31 +04:00
|
|
|
unsigned int idx = SUBPAGE_IDX(addr);
|
2007-05-26 21:36:03 +04:00
|
|
|
#if defined(DEBUG_SUBPAGE)
|
2012-01-02 14:32:48 +04:00
|
|
|
printf("%s: subpage %p len %d addr " TARGET_FMT_plx
|
|
|
|
" idx %d value %"PRIx64"\n",
|
2010-04-23 03:47:31 +04:00
|
|
|
__func__, mmio, len, addr, idx, value);
|
2007-05-26 21:36:03 +04:00
|
|
|
#endif
|
2010-04-23 03:47:31 +04:00
|
|
|
|
|
|
|
addr += mmio->region_offset[idx];
|
|
|
|
idx = mmio->sub_io_index[idx];
|
2012-01-02 14:32:48 +04:00
|
|
|
io_mem_write(idx, addr, value, len);
|
2007-05-26 21:36:03 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 14:32:48 +04:00
|
|
|
static const MemoryRegionOps subpage_ops = {
|
|
|
|
.read = subpage_read,
|
|
|
|
.write = subpage_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-05-26 21:36:03 +04:00
|
|
|
};
|
|
|
|
|
2012-01-02 14:41:07 +04:00
|
|
|
static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
2011-11-30 19:26:21 +04:00
|
|
|
{
|
|
|
|
ram_addr_t raddr = addr;
|
|
|
|
void *ptr = qemu_get_ram_ptr(raddr);
|
2012-01-02 14:41:07 +04:00
|
|
|
switch (size) {
|
|
|
|
case 1: return ldub_p(ptr);
|
|
|
|
case 2: return lduw_p(ptr);
|
|
|
|
case 4: return ldl_p(ptr);
|
|
|
|
default: abort();
|
|
|
|
}
|
2011-11-30 19:26:21 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 14:41:07 +04:00
|
|
|
static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t value, unsigned size)
|
2011-11-30 19:26:21 +04:00
|
|
|
{
|
|
|
|
ram_addr_t raddr = addr;
|
|
|
|
void *ptr = qemu_get_ram_ptr(raddr);
|
2012-01-02 14:41:07 +04:00
|
|
|
switch (size) {
|
|
|
|
case 1: return stb_p(ptr, value);
|
|
|
|
case 2: return stw_p(ptr, value);
|
|
|
|
case 4: return stl_p(ptr, value);
|
|
|
|
default: abort();
|
|
|
|
}
|
2011-11-30 19:26:21 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 14:41:07 +04:00
|
|
|
static const MemoryRegionOps subpage_ram_ops = {
|
|
|
|
.read = subpage_ram_read,
|
|
|
|
.write = subpage_ram_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2011-11-30 19:26:21 +04:00
|
|
|
};
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
|
|
|
ram_addr_t memory, ram_addr_t region_offset)
|
2007-05-26 21:36:03 +04:00
|
|
|
{
|
|
|
|
int idx, eidx;
|
|
|
|
|
|
|
|
if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
|
|
|
|
return -1;
|
|
|
|
idx = SUBPAGE_IDX(start);
|
|
|
|
eidx = SUBPAGE_IDX(end);
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
2009-07-20 21:19:25 +04:00
|
|
|
printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
|
2007-05-26 21:36:03 +04:00
|
|
|
mmio, start, end, idx, eidx, memory);
|
|
|
|
#endif
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((memory & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) {
|
2012-01-02 14:41:07 +04:00
|
|
|
memory = io_mem_subpage_ram.ram_addr;
|
2011-11-30 19:26:21 +04:00
|
|
|
}
|
2012-01-02 19:21:07 +04:00
|
|
|
memory &= IO_MEM_NB_ENTRIES - 1;
|
2007-05-26 21:36:03 +04:00
|
|
|
for (; idx <= eidx; idx++) {
|
2010-04-23 03:47:31 +04:00
|
|
|
mmio->sub_io_index[idx] = memory;
|
|
|
|
mmio->region_offset[idx] = region_offset;
|
2007-05-26 21:36:03 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-04-23 03:47:31 +04:00
|
|
|
static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
|
|
|
|
ram_addr_t orig_memory,
|
|
|
|
ram_addr_t region_offset)
|
2007-05-26 21:36:03 +04:00
|
|
|
{
|
2009-10-02 01:12:16 +04:00
|
|
|
subpage_t *mmio;
|
2007-05-26 21:36:03 +04:00
|
|
|
int subpage_memory;
|
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
mmio = g_malloc0(sizeof(subpage_t));
|
2009-02-06 01:06:18 +03:00
|
|
|
|
|
|
|
mmio->base = base;
|
2012-01-02 14:32:48 +04:00
|
|
|
memory_region_init_io(&mmio->iomem, &subpage_ops, mmio,
|
|
|
|
"subpage", TARGET_PAGE_SIZE);
|
2012-01-02 15:20:11 +04:00
|
|
|
mmio->iomem.subpage = true;
|
2012-01-02 14:32:48 +04:00
|
|
|
subpage_memory = mmio->iomem.ram_addr;
|
2007-05-26 21:36:03 +04:00
|
|
|
#if defined(DEBUG_SUBPAGE)
|
2009-02-06 01:06:18 +03:00
|
|
|
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
|
|
|
|
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
|
2007-05-26 21:36:03 +04:00
|
|
|
#endif
|
2012-01-02 15:20:11 +04:00
|
|
|
*phys = subpage_memory;
|
2010-04-23 03:47:31 +04:00
|
|
|
subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset);
|
2007-05-26 21:36:03 +04:00
|
|
|
|
|
|
|
return mmio;
|
|
|
|
}
|
|
|
|
|
2009-02-11 18:20:58 +03:00
|
|
|
static int get_free_io_mem_idx(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
|
|
|
|
if (!io_mem_used[i]) {
|
|
|
|
io_mem_used[i] = 1;
|
|
|
|
return i;
|
|
|
|
}
|
2009-12-03 16:56:05 +03:00
|
|
|
fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES);
|
2009-02-11 18:20:58 +03:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2003-08-11 01:47:01 +04:00
|
|
|
/* mem_read and mem_write are arrays of functions containing the
|
|
|
|
function to access byte (index 0), word (index 1) and dword (index
|
2009-04-30 21:37:55 +04:00
|
|
|
2). Functions can be omitted with a NULL function pointer.
|
2008-01-02 22:45:26 +03:00
|
|
|
If io_index is non zero, the corresponding io zone is
|
2008-01-01 19:57:19 +03:00
|
|
|
modified. If it is zero, a new io zone is allocated. The return
|
|
|
|
value can be used with cpu_register_physical_memory(). (-1) is
|
|
|
|
returned if error. */
|
2012-01-02 15:12:08 +04:00
|
|
|
static int cpu_register_io_memory_fixed(int io_index, MemoryRegion *mr)
|
2003-08-11 01:47:01 +04:00
|
|
|
{
|
|
|
|
if (io_index <= 0) {
|
2009-02-11 18:20:58 +03:00
|
|
|
io_index = get_free_io_mem_idx();
|
|
|
|
if (io_index == -1)
|
|
|
|
return io_index;
|
2003-08-11 01:47:01 +04:00
|
|
|
} else {
|
|
|
|
if (io_index >= IO_MEM_NB_ENTRIES)
|
|
|
|
return -1;
|
|
|
|
}
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2012-01-02 15:12:08 +04:00
|
|
|
io_mem_region[io_index] = mr;
|
2010-04-23 03:47:31 +04:00
|
|
|
|
2012-01-02 19:21:07 +04:00
|
|
|
return io_index;
|
2003-08-11 01:47:01 +04:00
|
|
|
}
|
2003-10-28 00:22:23 +03:00
|
|
|
|
2012-01-02 15:12:08 +04:00
|
|
|
int cpu_register_io_memory(MemoryRegion *mr)
|
2009-06-14 12:38:51 +04:00
|
|
|
{
|
2012-01-02 15:12:08 +04:00
|
|
|
return cpu_register_io_memory_fixed(0, mr);
|
2009-06-14 12:38:51 +04:00
|
|
|
}
|
|
|
|
|
2012-01-02 19:21:07 +04:00
|
|
|
void cpu_unregister_io_memory(int io_index)
|
2009-02-11 18:20:58 +03:00
|
|
|
{
|
2012-01-02 15:12:08 +04:00
|
|
|
io_mem_region[io_index] = NULL;
|
2009-02-11 18:20:58 +03:00
|
|
|
io_mem_used[io_index] = 0;
|
|
|
|
}
|
|
|
|
|
2009-06-14 12:38:52 +04:00
|
|
|
static void io_mem_init(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
/* Must be first: */
|
|
|
|
memory_region_init_io(&io_mem_ram, &error_mem_ops, NULL, "ram", UINT64_MAX);
|
|
|
|
assert(io_mem_ram.ram_addr == 0);
|
|
|
|
memory_region_init_io(&io_mem_rom, &rom_mem_ops, NULL, "rom", UINT64_MAX);
|
|
|
|
memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL,
|
|
|
|
"unassigned", UINT64_MAX);
|
|
|
|
memory_region_init_io(&io_mem_notdirty, ¬dirty_mem_ops, NULL,
|
|
|
|
"notdirty", UINT64_MAX);
|
2012-01-02 14:41:07 +04:00
|
|
|
memory_region_init_io(&io_mem_subpage_ram, &subpage_ram_ops, NULL,
|
|
|
|
"subpage-ram", UINT64_MAX);
|
2009-06-14 12:38:52 +04:00
|
|
|
for (i=0; i<5; i++)
|
|
|
|
io_mem_used[i] = 1;
|
|
|
|
|
2012-01-02 14:47:48 +04:00
|
|
|
memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL,
|
|
|
|
"watch", UINT64_MAX);
|
2009-06-14 12:38:52 +04:00
|
|
|
}
|
|
|
|
|
2011-07-26 15:26:14 +04:00
|
|
|
static void memory_map_init(void)
|
|
|
|
{
|
2011-08-21 07:09:37 +04:00
|
|
|
system_memory = g_malloc(sizeof(*system_memory));
|
2011-08-03 12:56:14 +04:00
|
|
|
memory_region_init(system_memory, "system", INT64_MAX);
|
2011-07-26 15:26:14 +04:00
|
|
|
set_system_memory_map(system_memory);
|
2011-08-08 17:09:03 +04:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
system_io = g_malloc(sizeof(*system_io));
|
2011-08-08 17:09:03 +04:00
|
|
|
memory_region_init(system_io, "io", 65536);
|
|
|
|
set_system_io_map(system_io);
|
2011-07-26 15:26:14 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
MemoryRegion *get_system_memory(void)
|
|
|
|
{
|
|
|
|
return system_memory;
|
|
|
|
}
|
|
|
|
|
2011-08-08 17:09:03 +04:00
|
|
|
MemoryRegion *get_system_io(void)
|
|
|
|
{
|
|
|
|
return system_io;
|
|
|
|
}
|
|
|
|
|
2008-06-08 05:09:01 +04:00
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2004-01-24 18:23:36 +03:00
|
|
|
/* physical memory access (slow version, mainly for debug) */
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2010-03-01 03:08:59 +03:00
|
|
|
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
|
|
|
uint8_t *buf, int len, int is_write)
|
2004-01-24 18:23:36 +03:00
|
|
|
{
|
|
|
|
int l, flags;
|
|
|
|
target_ulong page;
|
2006-03-25 22:31:22 +03:00
|
|
|
void * p;
|
2004-01-24 18:23:36 +03:00
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
flags = page_get_flags(page);
|
|
|
|
if (!(flags & PAGE_VALID))
|
2010-03-01 03:08:59 +03:00
|
|
|
return -1;
|
2004-01-24 18:23:36 +03:00
|
|
|
if (is_write) {
|
|
|
|
if (!(flags & PAGE_WRITE))
|
2010-03-01 03:08:59 +03:00
|
|
|
return -1;
|
2007-11-11 17:26:47 +03:00
|
|
|
/* XXX: this code should not depend on lock_user */
|
2008-04-28 03:53:45 +04:00
|
|
|
if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
|
2010-03-01 03:08:59 +03:00
|
|
|
return -1;
|
2008-04-28 03:53:45 +04:00
|
|
|
memcpy(p, buf, l);
|
|
|
|
unlock_user(p, addr, l);
|
2004-01-24 18:23:36 +03:00
|
|
|
} else {
|
|
|
|
if (!(flags & PAGE_READ))
|
2010-03-01 03:08:59 +03:00
|
|
|
return -1;
|
2007-11-11 17:26:47 +03:00
|
|
|
/* XXX: this code should not depend on lock_user */
|
2008-04-28 03:53:45 +04:00
|
|
|
if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
|
2010-03-01 03:08:59 +03:00
|
|
|
return -1;
|
2008-04-28 03:53:45 +04:00
|
|
|
memcpy(buf, p, l);
|
2008-04-28 12:54:59 +04:00
|
|
|
unlock_user(p, addr, 0);
|
2004-01-24 18:23:36 +03:00
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
2010-03-01 03:08:59 +03:00
|
|
|
return 0;
|
2004-01-24 18:23:36 +03:00
|
|
|
}
|
2005-01-29 01:37:22 +03:00
|
|
|
|
2004-01-24 18:23:36 +03:00
|
|
|
#else
|
2009-10-02 01:12:16 +04:00
|
|
|
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
2004-01-24 18:23:36 +03:00
|
|
|
int len, int is_write)
|
|
|
|
{
|
|
|
|
int l, io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint32_t val;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t page;
|
2011-07-15 08:32:53 +04:00
|
|
|
ram_addr_t pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-01-24 18:23:36 +03:00
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
2004-05-21 18:52:29 +04:00
|
|
|
p = phys_page_find(page >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-01-24 18:23:36 +03:00
|
|
|
if (is_write) {
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
|
2011-11-20 19:52:22 +04:00
|
|
|
target_phys_addr_t addr1;
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2005-11-22 02:25:50 +03:00
|
|
|
/* XXX: could force cpu_single_env to NULL to avoid
|
|
|
|
potential bugs */
|
2009-02-19 00:37:17 +03:00
|
|
|
if (l >= 4 && ((addr1 & 3) == 0)) {
|
2005-09-03 14:49:04 +04:00
|
|
|
/* 32 bit write access */
|
2005-01-04 02:35:10 +03:00
|
|
|
val = ldl_p(buf);
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr1, val, 4);
|
2004-01-24 18:23:36 +03:00
|
|
|
l = 4;
|
2009-02-19 00:37:17 +03:00
|
|
|
} else if (l >= 2 && ((addr1 & 1) == 0)) {
|
2005-09-03 14:49:04 +04:00
|
|
|
/* 16 bit write access */
|
2005-01-04 02:35:10 +03:00
|
|
|
val = lduw_p(buf);
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr1, val, 2);
|
2004-01-24 18:23:36 +03:00
|
|
|
l = 2;
|
|
|
|
} else {
|
2005-09-03 14:49:04 +04:00
|
|
|
/* 8 bit write access */
|
2005-01-04 02:35:10 +03:00
|
|
|
val = ldub_p(buf);
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr1, val, 1);
|
2004-01-24 18:23:36 +03:00
|
|
|
l = 1;
|
|
|
|
}
|
|
|
|
} else {
|
2011-07-15 08:32:53 +04:00
|
|
|
ram_addr_t addr1;
|
2004-02-26 02:24:04 +03:00
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
2004-01-24 18:23:36 +03:00
|
|
|
/* RAM case */
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(addr1);
|
2004-01-24 18:23:36 +03:00
|
|
|
memcpy(ptr, buf, l);
|
2005-08-21 13:26:42 +04:00
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
|
|
|
|
/* set dirty bit */
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_set_dirty_flags(
|
|
|
|
addr1, (0xff & ~CODE_DIRTY_FLAG));
|
2005-08-21 13:26:42 +04:00
|
|
|
}
|
2010-09-16 16:57:49 +04:00
|
|
|
qemu_put_ram_ptr(ptr);
|
2004-01-24 18:23:36 +03:00
|
|
|
}
|
|
|
|
} else {
|
2012-01-01 23:15:42 +04:00
|
|
|
if (!is_ram_rom_romd(pd)) {
|
2011-11-20 19:52:22 +04:00
|
|
|
target_phys_addr_t addr1;
|
2004-01-24 18:23:36 +03:00
|
|
|
/* I/O case */
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2009-02-19 00:37:17 +03:00
|
|
|
if (l >= 4 && ((addr1 & 3) == 0)) {
|
2004-01-24 18:23:36 +03:00
|
|
|
/* 32 bit read access */
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr1, 4);
|
2005-01-04 02:35:10 +03:00
|
|
|
stl_p(buf, val);
|
2004-01-24 18:23:36 +03:00
|
|
|
l = 4;
|
2009-02-19 00:37:17 +03:00
|
|
|
} else if (l >= 2 && ((addr1 & 1) == 0)) {
|
2004-01-24 18:23:36 +03:00
|
|
|
/* 16 bit read access */
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr1, 2);
|
2005-01-04 02:35:10 +03:00
|
|
|
stw_p(buf, val);
|
2004-01-24 18:23:36 +03:00
|
|
|
l = 2;
|
|
|
|
} else {
|
2005-09-03 14:49:04 +04:00
|
|
|
/* 8 bit read access */
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr1, 1);
|
2005-01-04 02:35:10 +03:00
|
|
|
stb_p(buf, val);
|
2004-01-24 18:23:36 +03:00
|
|
|
l = 1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* RAM case */
|
2010-09-16 16:57:49 +04:00
|
|
|
ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
|
|
|
|
memcpy(buf, ptr + (addr & ~TARGET_PAGE_MASK), l);
|
|
|
|
qemu_put_ram_ptr(ptr);
|
2004-01-24 18:23:36 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
}
|
2005-01-29 01:37:22 +03:00
|
|
|
|
2006-04-23 21:14:48 +04:00
|
|
|
/* used for ROM loading : can write in RAM and ROM */
|
2009-10-02 01:12:16 +04:00
|
|
|
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
|
2006-04-23 21:14:48 +04:00
|
|
|
const uint8_t *buf, int len)
|
|
|
|
{
|
|
|
|
int l;
|
|
|
|
uint8_t *ptr;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t page;
|
2006-04-23 21:14:48 +04:00
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2006-04-23 21:14:48 +04:00
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
p = phys_page_find(page >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2012-01-01 23:15:42 +04:00
|
|
|
if (!is_ram_rom_romd(pd)) {
|
2006-04-23 21:14:48 +04:00
|
|
|
/* do nothing */
|
|
|
|
} else {
|
|
|
|
unsigned long addr1;
|
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
/* ROM/RAM case */
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(addr1);
|
2006-04-23 21:14:48 +04:00
|
|
|
memcpy(ptr, buf, l);
|
2010-09-16 16:57:49 +04:00
|
|
|
qemu_put_ram_ptr(ptr);
|
2006-04-23 21:14:48 +04:00
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-22 19:59:11 +03:00
|
|
|
typedef struct {
|
|
|
|
void *buffer;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t addr;
|
|
|
|
target_phys_addr_t len;
|
2009-01-22 19:59:11 +03:00
|
|
|
} BounceBuffer;
|
|
|
|
|
|
|
|
static BounceBuffer bounce;
|
|
|
|
|
2009-01-22 19:59:16 +03:00
|
|
|
typedef struct MapClient {
|
|
|
|
void *opaque;
|
|
|
|
void (*callback)(void *opaque);
|
2009-09-12 11:36:22 +04:00
|
|
|
QLIST_ENTRY(MapClient) link;
|
2009-01-22 19:59:16 +03:00
|
|
|
} MapClient;
|
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
static QLIST_HEAD(map_client_list, MapClient) map_client_list
|
|
|
|
= QLIST_HEAD_INITIALIZER(map_client_list);
|
2009-01-22 19:59:16 +03:00
|
|
|
|
|
|
|
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
|
|
|
|
{
|
2011-08-21 07:09:37 +04:00
|
|
|
MapClient *client = g_malloc(sizeof(*client));
|
2009-01-22 19:59:16 +03:00
|
|
|
|
|
|
|
client->opaque = opaque;
|
|
|
|
client->callback = callback;
|
2009-09-12 11:36:22 +04:00
|
|
|
QLIST_INSERT_HEAD(&map_client_list, client, link);
|
2009-01-22 19:59:16 +03:00
|
|
|
return client;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_unregister_map_client(void *_client)
|
|
|
|
{
|
|
|
|
MapClient *client = (MapClient *)_client;
|
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
QLIST_REMOVE(client, link);
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(client);
|
2009-01-22 19:59:16 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_notify_map_clients(void)
|
|
|
|
{
|
|
|
|
MapClient *client;
|
|
|
|
|
2009-09-12 11:36:22 +04:00
|
|
|
while (!QLIST_EMPTY(&map_client_list)) {
|
|
|
|
client = QLIST_FIRST(&map_client_list);
|
2009-01-22 19:59:16 +03:00
|
|
|
client->callback(client->opaque);
|
2009-06-26 13:57:18 +04:00
|
|
|
cpu_unregister_map_client(client);
|
2009-01-22 19:59:16 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-22 19:59:11 +03:00
|
|
|
/* Map a physical memory region into a host virtual address.
|
|
|
|
* May map a subset of the requested range, given by and returned in *plen.
|
|
|
|
* May return NULL if resources needed to perform the mapping are exhausted.
|
|
|
|
* Use only for reads OR writes - not for read-modify-write operations.
|
2009-01-22 19:59:16 +03:00
|
|
|
* Use cpu_register_map_client() to know when retrying the map operation is
|
|
|
|
* likely to succeed.
|
2009-01-22 19:59:11 +03:00
|
|
|
*/
|
2009-10-02 01:12:16 +04:00
|
|
|
void *cpu_physical_memory_map(target_phys_addr_t addr,
|
|
|
|
target_phys_addr_t *plen,
|
2009-01-22 19:59:11 +03:00
|
|
|
int is_write)
|
|
|
|
{
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t len = *plen;
|
2011-05-19 21:35:45 +04:00
|
|
|
target_phys_addr_t todo = 0;
|
2009-01-22 19:59:11 +03:00
|
|
|
int l;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t page;
|
2009-01-22 19:59:11 +03:00
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2011-07-20 12:17:42 +04:00
|
|
|
ram_addr_t raddr = RAM_ADDR_MAX;
|
2011-06-27 21:26:06 +04:00
|
|
|
ram_addr_t rlen;
|
|
|
|
void *ret;
|
2009-01-22 19:59:11 +03:00
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
p = phys_page_find(page >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2009-01-22 19:59:11 +03:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
|
2011-05-19 21:35:45 +04:00
|
|
|
if (todo || bounce.buffer) {
|
2009-01-22 19:59:11 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
|
|
|
|
bounce.addr = addr;
|
|
|
|
bounce.len = l;
|
|
|
|
if (!is_write) {
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_read(addr, bounce.buffer, l);
|
2009-01-22 19:59:11 +03:00
|
|
|
}
|
2011-05-19 21:35:45 +04:00
|
|
|
|
|
|
|
*plen = l;
|
|
|
|
return bounce.buffer;
|
2009-01-22 19:59:11 +03:00
|
|
|
}
|
2011-06-27 21:26:06 +04:00
|
|
|
if (!todo) {
|
|
|
|
raddr = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
}
|
2009-01-22 19:59:11 +03:00
|
|
|
|
|
|
|
len -= l;
|
|
|
|
addr += l;
|
2011-05-19 21:35:45 +04:00
|
|
|
todo += l;
|
2009-01-22 19:59:11 +03:00
|
|
|
}
|
2011-06-27 21:26:06 +04:00
|
|
|
rlen = todo;
|
|
|
|
ret = qemu_ram_ptr_length(raddr, &rlen);
|
|
|
|
*plen = rlen;
|
|
|
|
return ret;
|
2009-01-22 19:59:11 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Unmaps a memory region previously mapped by cpu_physical_memory_map().
|
|
|
|
* Will also mark the memory as dirty if is_write == 1. access_len gives
|
|
|
|
* the amount of memory that was actually read or written by the caller.
|
|
|
|
*/
|
2009-10-02 01:12:16 +04:00
|
|
|
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
|
|
|
|
int is_write, target_phys_addr_t access_len)
|
2009-01-22 19:59:11 +03:00
|
|
|
{
|
|
|
|
if (buffer != bounce.buffer) {
|
|
|
|
if (is_write) {
|
2010-10-11 22:31:19 +04:00
|
|
|
ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer);
|
2009-01-22 19:59:11 +03:00
|
|
|
while (access_len) {
|
|
|
|
unsigned l;
|
|
|
|
l = TARGET_PAGE_SIZE;
|
|
|
|
if (l > access_len)
|
|
|
|
l = access_len;
|
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
|
|
|
|
/* set dirty bit */
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_set_dirty_flags(
|
|
|
|
addr1, (0xff & ~CODE_DIRTY_FLAG));
|
2009-01-22 19:59:11 +03:00
|
|
|
}
|
|
|
|
addr1 += l;
|
|
|
|
access_len -= l;
|
|
|
|
}
|
|
|
|
}
|
2011-06-22 00:59:09 +04:00
|
|
|
if (xen_enabled()) {
|
2011-06-22 00:59:08 +04:00
|
|
|
xen_invalidate_map_cache_entry(buffer);
|
2010-09-16 16:57:49 +04:00
|
|
|
}
|
2009-01-22 19:59:11 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (is_write) {
|
|
|
|
cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
|
|
|
|
}
|
2010-01-25 00:23:56 +03:00
|
|
|
qemu_vfree(bounce.buffer);
|
2009-01-22 19:59:11 +03:00
|
|
|
bounce.buffer = NULL;
|
2009-01-22 19:59:16 +03:00
|
|
|
cpu_notify_map_clients();
|
2009-01-22 19:59:11 +03:00
|
|
|
}
|
2006-04-23 21:14:48 +04:00
|
|
|
|
2005-01-29 01:37:22 +03:00
|
|
|
/* warning: addr must be aligned */
|
2011-07-06 11:09:23 +04:00
|
|
|
static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
|
|
|
|
enum device_endian endian)
|
2005-01-29 01:37:22 +03:00
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint32_t val;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2005-01-29 01:37:22 +03:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2012-01-01 23:15:42 +04:00
|
|
|
if (!is_ram_rom_romd(pd)) {
|
2005-01-29 01:37:22 +03:00
|
|
|
/* I/O case */
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr, 4);
|
2011-07-06 11:09:23 +04:00
|
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
|
|
if (endian == DEVICE_LITTLE_ENDIAN) {
|
|
|
|
val = bswap32(val);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (endian == DEVICE_BIG_ENDIAN) {
|
|
|
|
val = bswap32(val);
|
|
|
|
}
|
|
|
|
#endif
|
2005-01-29 01:37:22 +03:00
|
|
|
} else {
|
|
|
|
/* RAM case */
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
2005-01-29 01:37:22 +03:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
2011-07-06 11:09:23 +04:00
|
|
|
switch (endian) {
|
|
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
|
|
val = ldl_le_p(ptr);
|
|
|
|
break;
|
|
|
|
case DEVICE_BIG_ENDIAN:
|
|
|
|
val = ldl_be_p(ptr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
val = ldl_p(ptr);
|
|
|
|
break;
|
|
|
|
}
|
2005-01-29 01:37:22 +03:00
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2011-07-06 11:09:23 +04:00
|
|
|
uint32_t ldl_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t ldl_le_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t ldl_be_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
|
|
|
}
|
|
|
|
|
2005-11-29 00:19:04 +03:00
|
|
|
/* warning: addr must be aligned */
|
2011-07-06 11:09:23 +04:00
|
|
|
static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
|
|
|
|
enum device_endian endian)
|
2005-11-29 00:19:04 +03:00
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint64_t val;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2005-11-29 00:19:04 +03:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2012-01-01 23:15:42 +04:00
|
|
|
if (!is_ram_rom_romd(pd)) {
|
2005-11-29 00:19:04 +03:00
|
|
|
/* I/O case */
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2011-07-06 11:09:23 +04:00
|
|
|
|
|
|
|
/* XXX This is broken when device endian != cpu endian.
|
|
|
|
Fix and add "endian" variable check */
|
2005-11-29 00:19:04 +03:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr, 4) << 32;
|
|
|
|
val |= io_mem_read(io_index, addr + 4, 4);
|
2005-11-29 00:19:04 +03:00
|
|
|
#else
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr, 4);
|
|
|
|
val |= io_mem_read(io_index, addr + 4, 4) << 32;
|
2005-11-29 00:19:04 +03:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
/* RAM case */
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
2005-11-29 00:19:04 +03:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
2011-07-06 11:09:23 +04:00
|
|
|
switch (endian) {
|
|
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
|
|
val = ldq_le_p(ptr);
|
|
|
|
break;
|
|
|
|
case DEVICE_BIG_ENDIAN:
|
|
|
|
val = ldq_be_p(ptr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
val = ldq_p(ptr);
|
|
|
|
break;
|
|
|
|
}
|
2005-11-29 00:19:04 +03:00
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2011-07-06 11:09:23 +04:00
|
|
|
uint64_t ldq_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t ldq_le_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t ldq_be_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
|
|
|
}
|
|
|
|
|
2005-10-30 23:48:42 +03:00
|
|
|
/* XXX: optimize */
|
2009-10-02 01:12:16 +04:00
|
|
|
uint32_t ldub_phys(target_phys_addr_t addr)
|
2005-10-30 23:48:42 +03:00
|
|
|
{
|
|
|
|
uint8_t val;
|
|
|
|
cpu_physical_memory_read(addr, &val, 1);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2010-04-06 15:18:19 +04:00
|
|
|
/* warning: addr must be aligned */
|
2011-07-06 11:09:23 +04:00
|
|
|
static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
|
|
|
|
enum device_endian endian)
|
2005-10-30 23:48:42 +03:00
|
|
|
{
|
2010-04-06 15:18:19 +04:00
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint64_t val;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2010-04-06 15:18:19 +04:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2010-04-06 15:18:19 +04:00
|
|
|
|
2012-01-01 23:15:42 +04:00
|
|
|
if (!is_ram_rom_romd(pd)) {
|
2010-04-06 15:18:19 +04:00
|
|
|
/* I/O case */
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2011-11-21 14:27:03 +04:00
|
|
|
val = io_mem_read(io_index, addr, 2);
|
2011-07-06 11:09:23 +04:00
|
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
|
|
if (endian == DEVICE_LITTLE_ENDIAN) {
|
|
|
|
val = bswap16(val);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (endian == DEVICE_BIG_ENDIAN) {
|
|
|
|
val = bswap16(val);
|
|
|
|
}
|
|
|
|
#endif
|
2010-04-06 15:18:19 +04:00
|
|
|
} else {
|
|
|
|
/* RAM case */
|
|
|
|
ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
2011-07-06 11:09:23 +04:00
|
|
|
switch (endian) {
|
|
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
|
|
val = lduw_le_p(ptr);
|
|
|
|
break;
|
|
|
|
case DEVICE_BIG_ENDIAN:
|
|
|
|
val = lduw_be_p(ptr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
val = lduw_p(ptr);
|
|
|
|
break;
|
|
|
|
}
|
2010-04-06 15:18:19 +04:00
|
|
|
}
|
|
|
|
return val;
|
2005-10-30 23:48:42 +03:00
|
|
|
}
|
|
|
|
|
2011-07-06 11:09:23 +04:00
|
|
|
uint32_t lduw_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t lduw_le_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t lduw_be_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
|
|
|
}
|
|
|
|
|
2005-01-29 01:37:22 +03:00
|
|
|
/* warning: addr must be aligned. The ram page is not masked as dirty
|
|
|
|
and the code inside is not invalidated. It is useful if the dirty
|
|
|
|
bits are used to track modified PTEs */
|
2009-10-02 01:12:16 +04:00
|
|
|
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
|
2005-01-29 01:37:22 +03:00
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2005-01-29 01:37:22 +03:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr, val, 4);
|
2005-01-29 01:37:22 +03:00
|
|
|
} else {
|
2008-10-06 18:02:03 +04:00
|
|
|
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(addr1);
|
2005-01-29 01:37:22 +03:00
|
|
|
stl_p(ptr, val);
|
2008-10-06 18:02:03 +04:00
|
|
|
|
|
|
|
if (unlikely(in_migration)) {
|
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
|
|
|
|
/* set dirty bit */
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_set_dirty_flags(
|
|
|
|
addr1, (0xff & ~CODE_DIRTY_FLAG));
|
2008-10-06 18:02:03 +04:00
|
|
|
}
|
|
|
|
}
|
2005-01-29 01:37:22 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
|
2007-04-04 11:55:12 +04:00
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2007-04-04 11:55:12 +04:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2007-04-04 11:55:12 +04:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr, val >> 32, 4);
|
|
|
|
io_mem_write(io_index, addr + 4, (uint32_t)val, 4);
|
2007-04-04 11:55:12 +04:00
|
|
|
#else
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr, (uint32_t)val, 4);
|
|
|
|
io_mem_write(io_index, addr + 4, val >> 32, 4);
|
2007-04-04 11:55:12 +04:00
|
|
|
#endif
|
|
|
|
} else {
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
2007-04-04 11:55:12 +04:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
|
|
|
stq_p(ptr, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-01-29 01:37:22 +03:00
|
|
|
/* warning: addr must be aligned */
|
2011-07-06 11:09:23 +04:00
|
|
|
static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
|
|
|
|
enum device_endian endian)
|
2005-01-29 01:37:22 +03:00
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2005-01-29 01:37:22 +03:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2011-07-06 11:09:23 +04:00
|
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
|
|
if (endian == DEVICE_LITTLE_ENDIAN) {
|
|
|
|
val = bswap32(val);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (endian == DEVICE_BIG_ENDIAN) {
|
|
|
|
val = bswap32(val);
|
|
|
|
}
|
|
|
|
#endif
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr, val, 4);
|
2005-01-29 01:37:22 +03:00
|
|
|
} else {
|
|
|
|
unsigned long addr1;
|
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
/* RAM case */
|
2009-04-11 18:47:08 +04:00
|
|
|
ptr = qemu_get_ram_ptr(addr1);
|
2011-07-06 11:09:23 +04:00
|
|
|
switch (endian) {
|
|
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
|
|
stl_le_p(ptr, val);
|
|
|
|
break;
|
|
|
|
case DEVICE_BIG_ENDIAN:
|
|
|
|
stl_be_p(ptr, val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
stl_p(ptr, val);
|
|
|
|
break;
|
|
|
|
}
|
2005-08-21 13:26:42 +04:00
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
|
|
|
|
/* set dirty bit */
|
2010-03-23 10:39:53 +03:00
|
|
|
cpu_physical_memory_set_dirty_flags(addr1,
|
|
|
|
(0xff & ~CODE_DIRTY_FLAG));
|
2005-08-21 13:26:42 +04:00
|
|
|
}
|
2005-01-29 01:37:22 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-06 11:09:23 +04:00
|
|
|
void stl_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
void stl_le_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
void stl_be_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
|
|
|
|
}
|
|
|
|
|
2005-10-30 23:48:42 +03:00
|
|
|
/* XXX: optimize */
|
2009-10-02 01:12:16 +04:00
|
|
|
void stb_phys(target_phys_addr_t addr, uint32_t val)
|
2005-10-30 23:48:42 +03:00
|
|
|
{
|
|
|
|
uint8_t v = val;
|
|
|
|
cpu_physical_memory_write(addr, &v, 1);
|
|
|
|
}
|
|
|
|
|
2010-04-06 15:18:19 +04:00
|
|
|
/* warning: addr must be aligned */
|
2011-07-06 11:09:23 +04:00
|
|
|
static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
|
|
|
|
enum device_endian endian)
|
2005-10-30 23:48:42 +03:00
|
|
|
{
|
2010-04-06 15:18:19 +04:00
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
2011-11-20 19:52:22 +04:00
|
|
|
PhysPageDesc p;
|
2010-04-06 15:18:19 +04:00
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
2011-11-20 19:52:22 +04:00
|
|
|
pd = p.phys_offset;
|
2010-04-06 15:18:19 +04:00
|
|
|
|
2012-01-02 02:32:15 +04:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
|
2012-01-02 19:21:07 +04:00
|
|
|
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
|
2011-11-20 19:52:22 +04:00
|
|
|
addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
|
2011-07-06 11:09:23 +04:00
|
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
|
|
if (endian == DEVICE_LITTLE_ENDIAN) {
|
|
|
|
val = bswap16(val);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (endian == DEVICE_BIG_ENDIAN) {
|
|
|
|
val = bswap16(val);
|
|
|
|
}
|
|
|
|
#endif
|
2011-11-21 14:27:03 +04:00
|
|
|
io_mem_write(io_index, addr, val, 2);
|
2010-04-06 15:18:19 +04:00
|
|
|
} else {
|
|
|
|
unsigned long addr1;
|
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
/* RAM case */
|
|
|
|
ptr = qemu_get_ram_ptr(addr1);
|
2011-07-06 11:09:23 +04:00
|
|
|
switch (endian) {
|
|
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
|
|
stw_le_p(ptr, val);
|
|
|
|
break;
|
|
|
|
case DEVICE_BIG_ENDIAN:
|
|
|
|
stw_be_p(ptr, val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
stw_p(ptr, val);
|
|
|
|
break;
|
|
|
|
}
|
2010-04-06 15:18:19 +04:00
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + 2, 0);
|
|
|
|
/* set dirty bit */
|
|
|
|
cpu_physical_memory_set_dirty_flags(addr1,
|
|
|
|
(0xff & ~CODE_DIRTY_FLAG));
|
|
|
|
}
|
|
|
|
}
|
2005-10-30 23:48:42 +03:00
|
|
|
}
|
|
|
|
|
2011-07-06 11:09:23 +04:00
|
|
|
void stw_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
void stw_le_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
|
|
|
|
}
|
|
|
|
|
|
|
|
void stw_be_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
|
|
|
|
}
|
|
|
|
|
2005-10-30 23:48:42 +03:00
|
|
|
/* XXX: optimize */
|
2009-10-02 01:12:16 +04:00
|
|
|
void stq_phys(target_phys_addr_t addr, uint64_t val)
|
2005-10-30 23:48:42 +03:00
|
|
|
{
|
|
|
|
val = tswap64(val);
|
2011-03-26 23:06:56 +03:00
|
|
|
cpu_physical_memory_write(addr, &val, 8);
|
2005-10-30 23:48:42 +03:00
|
|
|
}
|
|
|
|
|
2011-07-06 11:09:23 +04:00
|
|
|
void stq_le_phys(target_phys_addr_t addr, uint64_t val)
|
|
|
|
{
|
|
|
|
val = cpu_to_le64(val);
|
|
|
|
cpu_physical_memory_write(addr, &val, 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
void stq_be_phys(target_phys_addr_t addr, uint64_t val)
|
|
|
|
{
|
|
|
|
val = cpu_to_be64(val);
|
|
|
|
cpu_physical_memory_write(addr, &val, 8);
|
|
|
|
}
|
|
|
|
|
2009-03-28 20:51:36 +03:00
|
|
|
/* virtual memory access for debug (includes writing to ROM) */
|
2007-09-17 01:08:06 +04:00
|
|
|
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
2004-02-26 02:24:04 +03:00
|
|
|
uint8_t *buf, int len, int is_write)
|
2004-01-24 18:23:36 +03:00
|
|
|
{
|
|
|
|
int l;
|
2009-10-02 01:12:16 +04:00
|
|
|
target_phys_addr_t phys_addr;
|
2007-04-07 15:21:28 +04:00
|
|
|
target_ulong page;
|
2004-01-24 18:23:36 +03:00
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
phys_addr = cpu_get_phys_page_debug(env, page);
|
|
|
|
/* if no physical page mapped, return an error */
|
|
|
|
if (phys_addr == -1)
|
|
|
|
return -1;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
2009-03-28 20:51:36 +03:00
|
|
|
phys_addr += (addr & ~TARGET_PAGE_MASK);
|
|
|
|
if (is_write)
|
|
|
|
cpu_physical_memory_write_rom(phys_addr, buf, l);
|
|
|
|
else
|
|
|
|
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
|
2004-01-24 18:23:36 +03:00
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2010-03-01 03:08:59 +03:00
|
|
|
#endif
|
2004-01-24 18:23:36 +03:00
|
|
|
|
2008-06-29 05:03:05 +04:00
|
|
|
/* in deterministic execution mode, instructions doing device I/Os
|
|
|
|
must be at the end of the TB */
|
|
|
|
void cpu_io_recompile(CPUState *env, void *retaddr)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
uint32_t n, cflags;
|
|
|
|
target_ulong pc, cs_base;
|
|
|
|
uint64_t flags;
|
|
|
|
|
|
|
|
tb = tb_find_pc((unsigned long)retaddr);
|
|
|
|
if (!tb) {
|
|
|
|
cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
|
|
|
|
retaddr);
|
|
|
|
}
|
|
|
|
n = env->icount_decr.u16.low + tb->icount;
|
2011-04-18 10:39:53 +04:00
|
|
|
cpu_restore_state(tb, env, (unsigned long)retaddr);
|
2008-06-29 05:03:05 +04:00
|
|
|
/* Calculate how many instructions had been executed before the fault
|
2008-06-30 21:22:19 +04:00
|
|
|
occurred. */
|
2008-06-29 05:03:05 +04:00
|
|
|
n = n - env->icount_decr.u16.low;
|
|
|
|
/* Generate a new TB ending on the I/O insn. */
|
|
|
|
n++;
|
|
|
|
/* On MIPS and SH, delay slot instructions can only be restarted if
|
|
|
|
they were already the first instruction in the TB. If this is not
|
2008-06-30 21:22:19 +04:00
|
|
|
the first instruction in a TB then re-execute the preceding
|
2008-06-29 05:03:05 +04:00
|
|
|
branch. */
|
|
|
|
#if defined(TARGET_MIPS)
|
|
|
|
if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
|
|
|
|
env->active_tc.PC -= 4;
|
|
|
|
env->icount_decr.u16.low++;
|
|
|
|
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
|
|
}
|
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
|
|
|
|
&& n > 1) {
|
|
|
|
env->pc -= 2;
|
|
|
|
env->icount_decr.u16.low++;
|
|
|
|
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* This should never happen. */
|
|
|
|
if (n > CF_COUNT_MASK)
|
|
|
|
cpu_abort(env, "TB too big during recompile");
|
|
|
|
|
|
|
|
cflags = n | CF_LAST_IO;
|
|
|
|
pc = tb->pc;
|
|
|
|
cs_base = tb->cs_base;
|
|
|
|
flags = tb->flags;
|
|
|
|
tb_phys_invalidate(tb, -1);
|
|
|
|
/* FIXME: In theory this could raise an exception. In practice
|
|
|
|
we have already translated the block once so it's probably ok. */
|
|
|
|
tb_gen_code(env, pc, cs_base, flags, cflags);
|
2008-06-30 21:22:19 +04:00
|
|
|
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
|
2008-06-29 05:03:05 +04:00
|
|
|
the first in the TB) then we end up generating a whole new TB and
|
|
|
|
repeating the fault, which is horribly inefficient.
|
|
|
|
Better would be to execute just this insn uncached, or generate a
|
|
|
|
second new TB. */
|
|
|
|
cpu_resume_from_signal(env, NULL);
|
|
|
|
}
|
|
|
|
|
2010-03-12 19:54:58 +03:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
|
2010-10-23 01:03:32 +04:00
|
|
|
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
|
2005-01-27 01:00:47 +03:00
|
|
|
{
|
|
|
|
int i, target_code_size, max_target_code_size;
|
|
|
|
int direct_jmp_count, direct_jmp2_count, cross_page;
|
|
|
|
TranslationBlock *tb;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2005-01-27 01:00:47 +03:00
|
|
|
target_code_size = 0;
|
|
|
|
max_target_code_size = 0;
|
|
|
|
cross_page = 0;
|
|
|
|
direct_jmp_count = 0;
|
|
|
|
direct_jmp2_count = 0;
|
|
|
|
for(i = 0; i < nb_tbs; i++) {
|
|
|
|
tb = &tbs[i];
|
|
|
|
target_code_size += tb->size;
|
|
|
|
if (tb->size > max_target_code_size)
|
|
|
|
max_target_code_size = tb->size;
|
|
|
|
if (tb->page_addr[1] != -1)
|
|
|
|
cross_page++;
|
|
|
|
if (tb->tb_next_offset[0] != 0xffff) {
|
|
|
|
direct_jmp_count++;
|
|
|
|
if (tb->tb_next_offset[1] != 0xffff) {
|
|
|
|
direct_jmp2_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* XXX: avoid using doubles ? */
|
2008-02-01 13:50:11 +03:00
|
|
|
cpu_fprintf(f, "Translation buffer state:\n");
|
2010-10-23 01:03:32 +04:00
|
|
|
cpu_fprintf(f, "gen code size %td/%ld\n",
|
2008-05-28 16:30:31 +04:00
|
|
|
code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
|
|
|
|
cpu_fprintf(f, "TB count %d/%d\n",
|
|
|
|
nb_tbs, code_gen_max_blocks);
|
2007-09-17 01:08:06 +04:00
|
|
|
cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
|
2005-01-27 01:00:47 +03:00
|
|
|
nb_tbs ? target_code_size / nb_tbs : 0,
|
|
|
|
max_target_code_size);
|
2010-10-23 01:03:32 +04:00
|
|
|
cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n",
|
2005-01-27 01:00:47 +03:00
|
|
|
nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
|
|
|
|
target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
|
2007-09-17 01:08:06 +04:00
|
|
|
cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
|
|
|
|
cross_page,
|
2005-01-27 01:00:47 +03:00
|
|
|
nb_tbs ? (cross_page * 100) / nb_tbs : 0);
|
|
|
|
cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
|
2007-09-17 01:08:06 +04:00
|
|
|
direct_jmp_count,
|
2005-01-27 01:00:47 +03:00
|
|
|
nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
|
|
|
|
direct_jmp2_count,
|
|
|
|
nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
|
2008-02-01 13:50:11 +03:00
|
|
|
cpu_fprintf(f, "\nStatistics:\n");
|
2005-01-27 01:00:47 +03:00
|
|
|
cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
|
|
|
|
cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
|
|
|
|
cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
|
2008-05-23 13:57:34 +04:00
|
|
|
tcg_dump_info(f, cpu_fprintf);
|
2005-01-27 01:00:47 +03:00
|
|
|
}
|
|
|
|
|
2012-01-02 01:35:10 +04:00
|
|
|
/* NOTE: this function can trigger an exception */
|
|
|
|
/* NOTE2: the returned address is not exactly the physical address: it
|
|
|
|
is the offset relative to phys_ram_base */
|
|
|
|
tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
|
|
|
|
{
|
|
|
|
int mmu_idx, page_index, pd;
|
|
|
|
void *p;
|
|
|
|
|
|
|
|
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
mmu_idx = cpu_mmu_index(env1);
|
|
|
|
if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
|
|
|
|
(addr & TARGET_PAGE_MASK))) {
|
|
|
|
ldub_code(addr);
|
|
|
|
}
|
|
|
|
pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
|
2012-01-02 02:32:15 +04:00
|
|
|
if (pd != io_mem_ram.ram_addr && pd != io_mem_rom.ram_addr
|
2012-01-02 17:40:52 +04:00
|
|
|
&& !is_romd(pd)) {
|
2012-01-02 01:35:10 +04:00
|
|
|
#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
|
|
|
|
cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
|
|
|
|
#else
|
|
|
|
cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
|
|
|
|
return qemu_ram_addr_from_host_nofail(p);
|
|
|
|
}
|
|
|
|
|
2012-01-10 05:35:11 +04:00
|
|
|
/*
|
|
|
|
* A helper function for the _utterly broken_ virtio device model to find out if
|
|
|
|
* it's running on a big endian machine. Don't do this at home kids!
|
|
|
|
*/
|
|
|
|
bool virtio_is_big_endian(void);
|
|
|
|
bool virtio_is_big_endian(void)
|
|
|
|
{
|
|
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
|
|
return true;
|
|
|
|
#else
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2003-10-28 00:22:23 +03:00
|
|
|
#define MMUSUFFIX _cmmu
|
2011-09-21 22:13:16 +04:00
|
|
|
#undef GETPC
|
2003-10-28 00:22:23 +03:00
|
|
|
#define GETPC() NULL
|
|
|
|
#define env cpu_single_env
|
2004-10-03 19:07:13 +04:00
|
|
|
#define SOFTMMU_CODE_ACCESS
|
2003-10-28 00:22:23 +03:00
|
|
|
|
|
|
|
#define SHIFT 0
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 1
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 2
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 3
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#undef env
|
|
|
|
|
|
|
|
#endif
|