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Cleanup SPARC/TCX framebuffer allocation.

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Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7059 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2009-04-09 22:21:07 +00:00
parent 7ffa47675c
commit dc828ca1b5
5 changed files with 26 additions and 16 deletions
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2
cpu-all.h
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@ -906,6 +906,8 @@ static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
/* This should only be used for ram local to a device. */
void *qemu_get_ram_ptr(ram_addr_t addr);
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,

8
exec.c
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@ -2427,6 +2427,14 @@ void qemu_ram_free(ram_addr_t addr)
{
}
/* Return a host pointer to ram allocated with qemu_ram_alloc.
This may only be used if you actually allocated the ram, and
aready know how but the ram block is. */
void *qemu_get_ram_ptr(ram_addr_t addr)
{
return phys_ram_base + addr;
}
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED

21
hw/sun4m.c
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@ -382,7 +382,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
qemu_irq *esp_reset, *le_reset;
qemu_irq *fdc_tc;
qemu_irq *cpu_halt;
ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset;
ram_addr_t ram_offset, prom_offset, idreg_offset;
unsigned long kernel_size;
int ret;
char buf[1024];
@ -478,9 +478,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_offset = qemu_ram_alloc(hwdef->vram_size);
tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
@ -1183,7 +1182,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
*espdma_irq, *ledma_irq;
qemu_irq *esp_reset, *le_reset;
ram_addr_t ram_offset, prom_offset, tcx_offset;
ram_addr_t ram_offset, prom_offset;
unsigned long kernel_size;
int ret;
char buf[1024];
@ -1264,9 +1263,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_offset = qemu_ram_alloc(hwdef->vram_size);
tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
@ -1409,7 +1407,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq *fdc_tc;
ram_addr_t ram_offset, prom_offset, tcx_offset;
ram_addr_t ram_offset, prom_offset;
unsigned long kernel_size;
int ret;
char buf[1024];
@ -1481,9 +1479,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_offset = qemu_ram_alloc(hwdef->vram_size);
tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);

3
hw/sun4m.h
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@ -24,8 +24,7 @@ static inline void sparc_iommu_memory_write(void *opaque,
}
/* tcx.c */
void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height,
void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
int depth);
/* slavio_intctl.c */

8
hw/tcx.c
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@ -497,13 +497,17 @@ static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
tcx_dummy_writel,
};
void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height,
void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
int depth)
{
TCXState *s;
int io_memory, dummy_memory;
ram_addr_t vram_offset;
int size;
uint8_t *vram_base;
vram_offset = qemu_ram_alloc(vram_size);
vram_base = qemu_get_ram_ptr(vram_offset);
s = qemu_mallocz(sizeof(TCXState));
s->addr = addr;