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savevm: Add DeviceState param

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When available, we'd like to be able to access the DeviceState
when registering a savevm.  For buses with a get_dev_path()
function, this will allow us to create more unique savevm
id strings.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Alex Williamson 2010-06-25 11:09:07 -06:00 committed by Anthony Liguori
parent 4f43c1ff3b
commit 0be71e324f
85 changed files with 163 additions and 138 deletions
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2
audio/audio.c
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@ -1901,7 +1901,7 @@ static void audio_init (void)
}
QLIST_INIT (&s->card_head);
vmstate_register (0, &vmstate_audio, s);
vmstate_register (NULL, 0, &vmstate_audio, s);
}
void AUD_register_card (const char *name, QEMUSoundCard *card)

4
block-migration.c
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@ -638,6 +638,6 @@ void blk_mig_init(void)
QSIMPLEQ_INIT(&block_mig_state.bmds_list);
QSIMPLEQ_INIT(&block_mig_state.blk_list);
register_savevm_live("block", 0, 1, block_set_params, block_save_live,
NULL, block_load, &block_mig_state);
register_savevm_live(NULL, "block", 0, 1, block_set_params,
block_save_live, NULL, block_load, &block_mig_state);
}

4
exec.c
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@ -641,8 +641,8 @@ void cpu_exec_init(CPUState *env)
cpu_list_unlock();
#endif
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
vmstate_register(cpu_index, &vmstate_cpu_common, env);
register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
#endif
}

4
hw/adb.c
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@ -305,7 +305,7 @@ void adb_kbd_init(ADBBusState *bus)
d = adb_register_device(bus, ADB_KEYBOARD, adb_kbd_request,
adb_kbd_reset, s);
qemu_add_kbd_event_handler(adb_kbd_put_keycode, d);
register_savevm("adb_kbd", -1, 1, adb_kbd_save,
register_savevm(NULL, "adb_kbd", -1, 1, adb_kbd_save,
adb_kbd_load, s);
}
@ -475,6 +475,6 @@ void adb_mouse_init(ADBBusState *bus)
d = adb_register_device(bus, ADB_MOUSE, adb_mouse_request,
adb_mouse_reset, s);
qemu_add_mouse_event_handler(adb_mouse_event, d, 0, "QEMU ADB Mouse");
register_savevm("adb_mouse", -1, 1, adb_mouse_save,
register_savevm(NULL, "adb_mouse", -1, 1, adb_mouse_save,
adb_mouse_load, s);
}

2
hw/ads7846.c
View File

@ -151,7 +151,7 @@ static int ads7846_init(SSISlave *dev)
ads7846_int_update(s);
register_savevm("ads7846", -1, 0, ads7846_save, ads7846_load, s);
register_savevm(NULL, "ads7846", -1, 0, ads7846_save, ads7846_load, s);
return 0;
}

2
hw/arm_gic.c
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@ -744,5 +744,5 @@ static void gic_init(gic_state *s)
s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
gic_dist_writefn, s);
gic_reset(s);
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
}

4
hw/arm_timer.c
View File

@ -174,7 +174,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq)
bh = qemu_bh_new(arm_timer_tick, s);
s->timer = ptimer_init(bh);
register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
register_savevm(NULL, "arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
return s;
}
@ -271,7 +271,7 @@ static int sp804_init(SysBusDevice *dev)
iomemtype = cpu_register_io_memory(sp804_readfn,
sp804_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
register_savevm(&dev->qdev, "sp804", -1, 1, sp804_save, sp804_load, s);
return 0;
}

2
hw/armv7m_nvic.c
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@ -397,7 +397,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
gic_init(&s->gic);
cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);
s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
register_savevm(&dev->qdev, "armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
return 0;
}

2
hw/cirrus_vga.c
View File

@ -3128,7 +3128,7 @@ void isa_cirrus_vga_init(void)
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
vmstate_register(0, &vmstate_cirrus_vga, s);
vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
rom_add_vga(VGABIOS_CIRRUS_FILENAME);
/* XXX ISA-LFB support */
}

2
hw/cuda.c
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@ -763,6 +763,6 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, s);
}

4
hw/dma.c
View File

@ -548,8 +548,8 @@ void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
high_page_enable ? 0x480 : -1, cpu_request_exit);
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
high_page_enable ? 0x488 : -1, cpu_request_exit);
vmstate_register (0, &vmstate_dma, &dma_controllers[0]);
vmstate_register (1, &vmstate_dma, &dma_controllers[1]);
vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
dma_bh = qemu_bh_new(DMA_run_bh, NULL);
}

4
hw/eepro100.c
View File

@ -1834,7 +1834,7 @@ static int pci_nic_uninit(PCIDevice *pci_dev)
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
cpu_unregister_io_memory(s->mmio_index);
vmstate_unregister(s->vmstate, s);
vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
eeprom93xx_free(s->eeprom);
qemu_del_vlan_client(&s->nic->nc);
return 0;
@ -1893,7 +1893,7 @@ static int e100_nic_init(PCIDevice *pci_dev)
s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
s->vmstate->name = s->nic->nc.model;
vmstate_register(-1, s->vmstate, s);
vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
return 0;
}

4
hw/eeprom93xx.c
View File

@ -316,7 +316,7 @@ eeprom_t *eeprom93xx_new(uint16_t nwords)
/* Output DO is tristate, read results in 1. */
eeprom->eedo = 1;
logout("eeprom = 0x%p, nwords = %u\n", eeprom, nwords);
vmstate_register(0, &vmstate_eeprom, eeprom);
vmstate_register(NULL, 0, &vmstate_eeprom, eeprom);
return eeprom;
}
@ -324,7 +324,7 @@ void eeprom93xx_free(eeprom_t *eeprom)
{
/* Destroy EEPROM. */
logout("eeprom = 0x%p\n", eeprom);
vmstate_unregister(&vmstate_eeprom, eeprom);
vmstate_unregister(NULL, &vmstate_eeprom, eeprom);
qemu_free(eeprom);
}

2
hw/g364fb.c
View File

@ -598,7 +598,7 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
s->irq = irq;
qemu_register_reset(g364fb_reset, s);
register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);
register_savevm(NULL, "g364fb", 0, 1, g364fb_save, g364fb_load, s);
g364fb_reset(s);
s->ds = graphic_console_init(g364fb_update_display,

4
hw/grackle_pci.c
View File

@ -113,8 +113,8 @@ static int pci_grackle_init_device(SysBusDevice *dev)
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
&s->host_state);
register_savevm(&dev->qdev, "grackle", 0, 1, pci_grackle_save,
pci_grackle_load, &s->host_state);
qemu_register_reset(pci_grackle_reset, &s->host_state);
return 0;
}

3
hw/gt64xxx.c
View File

@ -1146,7 +1146,8 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
gt64120_reset(s);
register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
register_savevm(&d->qdev, "GT64120 PCI Bus", 0, 1,
gt64120_save, gt64120_load, d);
return s->pci->bus;
}

2
hw/heathrow_pic.c
View File

@ -224,7 +224,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
s->irqs = irqs[0];
*pmem_index = cpu_register_io_memory(pic_read, pic_write, s);
register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
register_savevm(NULL, "heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);
qemu_register_reset(heathrow_pic_reset, s);
return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);

18
hw/hw.h
View File

@ -245,14 +245,16 @@ typedef int SaveLiveStateHandler(Monitor *mon, QEMUFile *f, int stage,
void *opaque);
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
int register_savevm(const char *idstr,
int register_savevm(DeviceState *dev,
const char *idstr,
int instance_id,
int version_id,
SaveStateHandler *save_state,
LoadStateHandler *load_state,
void *opaque);
int register_savevm_live(const char *idstr,
int register_savevm_live(DeviceState *dev,
const char *idstr,
int instance_id,
int version_id,
SaveSetParamsHandler *set_params,
@ -261,7 +263,7 @@ int register_savevm_live(const char *idstr,
LoadStateHandler *load_state,
void *opaque);
void unregister_savevm(const char *idstr, void *opaque);
void unregister_savevm(DeviceState *dev, const char *idstr, void *opaque);
typedef void QEMUResetHandler(void *opaque);
@ -765,11 +767,13 @@ extern int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
void *opaque, int version_id);
extern void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
void *opaque);
extern int vmstate_register(int instance_id, const VMStateDescription *vmsd,
void *base);
extern int vmstate_register_with_alias_id(int instance_id,
extern int vmstate_register(DeviceState *dev, int instance_id,
const VMStateDescription *vmsd, void *base);
extern int vmstate_register_with_alias_id(DeviceState *dev,
int instance_id,
const VMStateDescription *vmsd,
void *base, int alias_id,
int required_for_version);
void vmstate_unregister(const VMStateDescription *vmsd, void *opaque);
void vmstate_unregister(DeviceState *dev, const VMStateDescription *vmsd,
void *opaque);
#endif

2
hw/i2c.c
View File

@ -62,7 +62,7 @@ i2c_bus *i2c_init_bus(DeviceState *parent, const char *name)
i2c_bus *bus;
bus = FROM_QBUS(i2c_bus, qbus_create(&i2c_bus_info, parent, name));
vmstate_register(-1, &vmstate_i2c_bus, bus);
vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
return bus;
}

2
hw/i8254.c
View File

@ -508,7 +508,7 @@ PITState *pit_init(int base, qemu_irq irq)
s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
s->irq = irq;
vmstate_register(base, &vmstate_pit, pit);
vmstate_register(NULL, base, &vmstate_pit, pit);
qemu_register_reset(pit_reset, pit);
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
register_ioport_read(base, 3, 1, pit_ioport_read, pit);

2
hw/i8259.c
View File

@ -483,7 +483,7 @@ static void pic_init1(int io_addr, int elcr_addr, PicState *s)
register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
}
vmstate_register(io_addr, &vmstate_pic, s);
vmstate_register(NULL, io_addr, &vmstate_pic, s);
qemu_register_reset(pic_reset, s);
}

2
hw/ide/cmd646.c
View File

@ -263,7 +263,7 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
ide_init2(&d->bus[0], irq[0]);
ide_init2(&d->bus[1], irq[1]);
vmstate_register(0, &vmstate_ide_pci, d);
vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
qemu_register_reset(cmd646_reset, d);
return 0;
}

2
hw/ide/isa.c
View File

@ -71,7 +71,7 @@ static int isa_ide_initfn(ISADevice *dev)
ide_init_ioport(&s->bus, s->iobase, s->iobase2);
isa_init_irq(dev, &s->irq, s->isairq);
ide_init2(&s->bus, s->irq);
vmstate_register(0, &vmstate_ide_isa, s);
vmstate_register(&dev->qdev, 0, &vmstate_ide_isa, s);
return 0;
};

2
hw/ide/macio.c
View File

@ -321,7 +321,7 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
pmac_ide_write, d);
vmstate_register(0, &vmstate_pmac, d);
vmstate_register(NULL, 0, &vmstate_pmac, d);
qemu_register_reset(pmac_ide_reset, d);
return pmac_ide_memory;

2
hw/ide/microdrive.c
View File

@ -545,7 +545,7 @@ PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv)
md->bus.ifs[0].mdata_size = METADATA_SIZE;
md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
vmstate_register(-1, &vmstate_microdrive, md);
vmstate_register(NULL, -1, &vmstate_microdrive, md);
return &md->card;
}

2
hw/ide/mmio.c
View File

@ -133,7 +133,7 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
cpu_register_physical_memory(membase, 16 << shift, mem1);
cpu_register_physical_memory(membase2, 2 << shift, mem2);
vmstate_register(0, &vmstate_ide_mmio, s);
vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
qemu_register_reset(mmio_ide_reset, s);
}

2
hw/ide/piix.c
View File

@ -128,7 +128,7 @@ static int pci_piix_ide_initfn(PCIIDEState *d)
pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
vmstate_register(0, &vmstate_ide_pci, d);
vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
ide_bus_new(&d->bus[0], &d->dev.qdev);
ide_bus_new(&d->bus[1], &d->dev.qdev);

2
hw/m48t59.c
View File

@ -694,7 +694,7 @@ static void m48t59_init_common(M48t59State *s)
}
qemu_get_timedate(&s->alarm, 0);
register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
register_savevm(NULL, "m48t59", -1, 1, m48t59_save, m48t59_load, s);
}
static int m48t59_init_isa1(ISADevice *dev)

2
hw/mac_dbdma.c
View File

@ -845,7 +845,7 @@ void* DBDMA_init (int *dbdma_mem_index)
s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
register_savevm(NULL, "dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, s);
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);

4
hw/mac_nvram.c
View File

@ -140,8 +140,8 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
*mem_index = s->mem_index;
register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
s);
register_savevm(NULL, "macio_nvram", -1, 1, macio_nvram_save,
macio_nvram_load, s);
qemu_register_reset(macio_nvram_reset, s);
return s;

3
hw/max111x.c
View File

@ -143,7 +143,8 @@ static int max111x_init(SSISlave *dev, int inputs)
s->input[7] = 0x80;
s->com = 0;
register_savevm("max111x", -1, 0, max111x_save, max111x_load, s);
register_savevm(&dev->qdev, "max111x", -1, 0,
max111x_save, max111x_load, s);
return 0;
}

2
hw/mips_fulong2e.c
View File

@ -282,7 +282,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
exit(1);
}
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
qemu_register_reset(main_cpu_reset, env);
/* fulong 2e has 256M ram. */

4
hw/mipsnet.c
View File

@ -239,7 +239,7 @@ static void mipsnet_cleanup(VLANClientState *nc)
{
MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
unregister_savevm("mipsnet", s);
unregister_savevm(NULL, "mipsnet", s);
isa_unassign_ioport(s->io_base, 36);
@ -284,5 +284,5 @@ void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
}
mipsnet_reset(s);
register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
register_savevm(NULL, "mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}

3
hw/mst_fpga.c
View File

@ -234,6 +234,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
iomemtype = cpu_register_io_memory(mst_fpga_readfn,
mst_fpga_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s);
register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
mst_fpga_load, s);
return qi;
}

2
hw/nand.c
View File

@ -502,7 +502,7 @@ NANDFlashState *nand_init(int manf_id, int chip_id)
is used. */
s->ioaddr = s->io;
register_savevm("nand", -1, 0, nand_save, nand_load, s);
register_savevm(NULL, "nand", -1, 0, nand_save, nand_load, s);
return s;
}

5
hw/openpic.c
View File

@ -1234,7 +1234,8 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
opp->irq_out = irq_out;
opp->need_swap = 1;
register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, opp);
opp->irq_raise = openpic_irq_raise;
@ -1692,7 +1693,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
mpp->irq_raise = mpic_irq_raise;
mpp->reset = mpic_reset;
register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
qemu_register_reset(mpic_reset, mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);

2
hw/pci.c
View File

@ -232,7 +232,7 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
QLIST_INIT(&bus->child);
pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
vmstate_register(-1, &vmstate_pcibus, bus);
vmstate_register(NULL, -1, &vmstate_pcibus, bus);
qemu_register_reset(pci_bus_reset, bus);
}

2
hw/pckbd.c
View File

@ -418,7 +418,7 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
s->irq_mouse = mouse_irq;
s->mask = mask;
vmstate_register(0, &vmstate_kbd, s);
vmstate_register(NULL, 0, &vmstate_kbd, s);
s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
cpu_register_physical_memory(base, size, s_io_memory);

2
hw/piix4.c
View File

@ -87,7 +87,7 @@ static int piix4_initfn(PCIDevice *d)
uint8_t *pci_conf;
isa_bus_new(&d->qdev);
register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
register_savevm(&d->qdev, "PIIX4", 0, 2, piix_save, piix_load, d);
pci_conf = d->config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);

2
hw/pl011.c
View File

@ -306,7 +306,7 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id)
qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s);
register_savevm(&dev->qdev, "pl011_uart", -1, 1, pl011_save, pl011_load, s);
return 0;
}

2
hw/pl022.c
View File

@ -299,7 +299,7 @@ static int pl022_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->ssi = ssi_create_bus(&dev->qdev, "ssi");
pl022_reset(s);
register_savevm("pl022_ssp", -1, 1, pl022_save, pl022_load, s);
register_savevm(&dev->qdev, "pl022_ssp", -1, 1, pl022_save, pl022_load, s);
return 0;
}

2
hw/pl061.c
View File

@ -303,7 +303,7 @@ static int pl061_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
qdev_init_gpio_out(&dev->qdev, s->out, 8);
pl061_reset(s);
register_savevm("pl061_gpio", -1, 1, pl061_save, pl061_load, s);
register_savevm(&dev->qdev, "pl061_gpio", -1, 1, pl061_save, pl061_load, s);
return 0;
}

4
hw/ppc4xx_pci.c
View File

@ -392,8 +392,8 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
qemu_register_reset(ppc4xx_pci_reset, controller);
/* XXX load/save code not tested. */
register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
ppc4xx_pci_save, ppc4xx_pci_load, controller);
register_savevm(&controller->pci_dev->qdev, "ppc4xx_pci", ppc4xx_pci_id++,
1, ppc4xx_pci_save, ppc4xx_pci_load, controller);
return controller->pci_state.bus;

4
hw/ppce500_pci.c
View File

@ -310,8 +310,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
PCIE500_REG_SIZE, index);
/* XXX load/save code not tested. */
register_savevm("ppce500_pci", ppce500_pci_id++, 1,
ppce500_pci_save, ppce500_pci_load, controller);
register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
1, ppce500_pci_save, ppce500_pci_load, controller);
return controller->pci_state.bus;

4
hw/ps2.c
View File

@ -595,7 +595,7 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg)
s->common.update_irq = update_irq;
s->common.update_arg = update_arg;
s->scancode_set = 2;
vmstate_register(0, &vmstate_ps2_keyboard, s);
vmstate_register(NULL, 0, &vmstate_ps2_keyboard, s);
qemu_add_kbd_event_handler(ps2_put_keycode, s);
qemu_register_reset(ps2_kbd_reset, s);
return s;
@ -607,7 +607,7 @@ void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg)
s->common.update_irq = update_irq;
s->common.update_arg = update_arg;
vmstate_register(0, &vmstate_ps2_mouse, s);
vmstate_register(NULL, 0, &vmstate_ps2_mouse, s);
qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse");
qemu_register_reset(ps2_mouse_reset, s);
return s;

27
hw/pxa2xx.c
View File

@ -860,7 +860,7 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm("pxa2xx_ssp", -1, 0,
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
s->bus = ssi_create_bus(&dev->qdev, "ssi");
@ -1515,7 +1515,7 @@ PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
cpu_register_physical_memory(base & ~region_size,
region_size + 1, iomemtype);
vmstate_register(base, &vmstate_pxa2xx_i2c, s);
vmstate_register(NULL, base, &vmstate_pxa2xx_i2c, s);
return s;
}
@ -1751,7 +1751,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
pxa2xx_i2s_writefn, s);
cpu_register_physical_memory(base, 0x100000, iomemtype);
register_savevm("pxa2xx_i2s", base, 0,
register_savevm(NULL, "pxa2xx_i2s", base, 0,
pxa2xx_i2s_save, pxa2xx_i2s_load, s);
return s;
@ -2014,7 +2014,8 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
pxa2xx_fir_rx, pxa2xx_fir_event, s);
register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
pxa2xx_fir_load, s);
return s;
}
@ -2099,7 +2100,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
@ -2110,13 +2111,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
pxa2xx_pm_writefn, s);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa27x_ssp[i].io_base; i ++);
s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
@ -2140,7 +2141,8 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
pxa2xx_rtc_writefn, s);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
pxa2xx_rtc_load, s);
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
@ -2219,7 +2221,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
@ -2230,13 +2232,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
pxa2xx_pm_writefn, s);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa255_ssp[i].io_base; i ++);
s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
@ -2260,7 +2262,8 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
pxa2xx_rtc_writefn, s);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
pxa2xx_rtc_load, s);
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);

2
hw/pxa2xx_dma.c
View File

@ -507,7 +507,7 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
pxa2xx_dma_writefn, s);
cpu_register_physical_memory(base, 0x00010000, iomemtype);
register_savevm("pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);
register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);
return s;
}

2
hw/pxa2xx_gpio.c
View File

@ -312,7 +312,7 @@ PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
pxa2xx_gpio_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
register_savevm("pxa2xx_gpio", 0, 0,
register_savevm(NULL, "pxa2xx_gpio", 0, 0,
pxa2xx_gpio_save, pxa2xx_gpio_load, s);
return s;

2
hw/pxa2xx_keypad.c
View File

@ -317,7 +317,7 @@ PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
pxa2xx_keypad_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm("pxa2xx_keypad", 0, 0,
register_savevm(NULL, "pxa2xx_keypad", 0, 0,
pxa2xx_keypad_save, pxa2xx_keypad_load, s);
return s;

2
hw/pxa2xx_lcd.c
View File

@ -970,7 +970,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
exit(1);
}
register_savevm("pxa2xx_lcdc", 0, 0,
register_savevm(NULL, "pxa2xx_lcdc", 0, 0,
pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
return s;

2
hw/pxa2xx_mmci.c
View File

@ -534,7 +534,7 @@ PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
/* Instantiate the actual storage */
s->card = sd_init(bd, 0);
register_savevm("pxa2xx_mmci", 0, 0,
register_savevm(NULL, "pxa2xx_mmci", 0, 0,
pxa2xx_mmci_save, pxa2xx_mmci_load, s);
return s;

3
hw/pxa2xx_pic.c
View File

@ -306,7 +306,8 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
/* Enable IC coprocessor access. */
cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
register_savevm("pxa2xx_pic", 0, 0, pxa2xx_pic_save, pxa2xx_pic_load, s);
register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save,
pxa2xx_pic_load, s);
return qi;
}

2
hw/pxa2xx_timer.c
View File

@ -455,7 +455,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
pxa2xx_timer_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
register_savevm("pxa2xx_timer", 0, 0,
register_savevm(NULL, "pxa2xx_timer", 0, 0,
pxa2xx_timer_save, pxa2xx_timer_load, s);
return s;

4
hw/qdev.c
View File

@ -280,7 +280,7 @@ int qdev_init(DeviceState *dev)
}
qemu_register_reset(qdev_reset, dev);
if (dev->info->vmsd) {
vmstate_register_with_alias_id(-1, dev->info->vmsd, dev,
vmstate_register_with_alias_id(dev, -1, dev->info->vmsd, dev,
dev->instance_id_alias,
dev->alias_required_for_version);
}
@ -342,7 +342,7 @@ void qdev_free(DeviceState *dev)
qbus_free(bus);
}
if (dev->info->vmsd)
vmstate_unregister(dev->info->vmsd, dev);
vmstate_unregister(dev, dev->info->vmsd, dev);
if (dev->info->exit)
dev->info->exit(dev);
if (dev->opts)

2
hw/rc4030.c
View File

@ -813,7 +813,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
s->jazz_bus_irq = jazz_bus;
qemu_register_reset(rc4030_reset, s);
register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
rc4030_reset(s);
s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);

4
hw/serial.c
View File

@ -813,7 +813,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
s->chr = chr;
serial_init_core(s);
vmstate_register(base, &vmstate_serial, s);
vmstate_register(NULL, base, &vmstate_serial, s);
register_ioport_write(base, 8, 1, serial_ioport_write, s);
register_ioport_read(base, 8, 1, serial_ioport_read, s);
@ -948,7 +948,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
s->chr = chr;
serial_init_core(s);
vmstate_register(base, &vmstate_serial, s);
vmstate_register(NULL, base, &vmstate_serial, s);
if (ioregister) {
if (be) {

9
hw/spitz.c
View File

@ -178,7 +178,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
sl_writefn, s);
cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
register_savevm(NULL, "sl_flash", 0, 0, sl_save, sl_load, s);
}
/* Spitz Keyboard */
@ -508,7 +508,7 @@ static void spitz_keyboard_register(PXA2xxState *cpu)
spitz_keyboard_pre_map(s);
qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
register_savevm("spitz_keyboard", 0, 0,
register_savevm(NULL, "spitz_keyboard", 0, 0,
spitz_keyboard_save, spitz_keyboard_load, s);
}
@ -613,7 +613,7 @@ static int spitz_lcdtg_init(SSISlave *dev)
s->bl_power = 0;
s->bl_intensity = 0x20;
register_savevm("spitz-lcdtg", -1, 1,
register_savevm(&dev->qdev, "spitz-lcdtg", -1, 1,
spitz_lcdtg_save, spitz_lcdtg_load, s);
return 0;
}
@ -708,7 +708,8 @@ static int corgi_ssp_init(SSISlave *dev)
s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
register_savevm("spitz_ssp", -1, 1, spitz_ssp_save, spitz_ssp_load, s);
register_savevm(&dev->qdev, "spitz_ssp", -1, 1,
spitz_ssp_save, spitz_ssp_load, s);
return 0;
}

3
hw/ssd0323.c
View File

@ -335,7 +335,8 @@ static int ssd0323_init(SSISlave *dev)
qdev_init_gpio_in(&dev->qdev, ssd0323_cd, 1);
register_savevm("ssd0323_oled", -1, 1, ssd0323_save, ssd0323_load, s);
register_savevm(&dev->qdev, "ssd0323_oled", -1, 1,
ssd0323_save, ssd0323_load, s);
return 0;
}

2
hw/ssi-sd.c
View File

@ -236,7 +236,7 @@ static int ssi_sd_init(SSISlave *dev)
s->mode = SSI_SD_CMD;
bs = qdev_init_bdrv(&dev->qdev, IF_SD);
s->sd = sd_init(bs, 1);
register_savevm("ssi_sd", -1, 1, ssi_sd_save, ssi_sd_load, s);
register_savevm(&dev->qdev, "ssi_sd", -1, 1, ssi_sd_save, ssi_sd_load, s);
return 0;
}

11
hw/stellaris.c
View File

@ -354,7 +354,8 @@ static int stellaris_gptm_init(SysBusDevice *dev)
s->opaque[0] = s->opaque[1] = s;
s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]);
s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]);
register_savevm("stellaris_gptm", -1, 1, gptm_save, gptm_load, s);
register_savevm(&dev->qdev, "stellaris_gptm", -1, 1,
gptm_save, gptm_load, s);
return 0;
}
@ -673,7 +674,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
ssys_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
ssys_reset(s);
register_savevm("stellaris_sys", -1, 1, ssys_save, ssys_load, s);
register_savevm(NULL, "stellaris_sys", -1, 1, ssys_save, ssys_load, s);
return 0;
}
@ -887,7 +888,7 @@ static int stellaris_i2c_init(SysBusDevice * dev)
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* ??? For now we only implement the master interface. */
stellaris_i2c_reset(s);
register_savevm("stellaris_i2c", -1, 1,
register_savevm(&dev->qdev, "stellaris_i2c", -1, 1,
stellaris_i2c_save, stellaris_i2c_load, s);
return 0;
}
@ -1196,7 +1197,7 @@ static int stellaris_adc_init(SysBusDevice *dev)
sysbus_init_mmio(dev, 0x1000, iomemtype);
stellaris_adc_reset(s);
qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
register_savevm("stellaris_adc", -1, 1,
register_savevm(&dev->qdev, "stellaris_adc", -1, 1,
stellaris_adc_save, stellaris_adc_load, s);
return 0;
}
@ -1256,7 +1257,7 @@ static int stellaris_ssi_bus_init(SSISlave *dev)
s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);
register_savevm("stellaris_ssi_bus", -1, 1,
register_savevm(&dev->qdev, "stellaris_ssi_bus", -1, 1,
stellaris_ssi_bus_save, stellaris_ssi_bus_load, s);
return 0;
}

4
hw/stellaris_enet.c
View File

@ -389,7 +389,7 @@ static void stellaris_enet_cleanup(VLANClientState *nc)
{
stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
unregister_savevm("stellaris_enet", s);
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
cpu_unregister_io_memory(s->mmio_index);
@ -419,7 +419,7 @@ static int stellaris_enet_init(SysBusDevice *dev)
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
stellaris_enet_reset(s);
register_savevm("stellaris_enet", -1, 1,
register_savevm(&s->busdev.qdev, "stellaris_enet", -1, 1,
stellaris_enet_save, stellaris_enet_load, s);
return 0;
}

2
hw/stellaris_input.c
View File

@ -86,6 +86,6 @@ void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode)
}
s->num_buttons = n;
qemu_add_kbd_event_handler(stellaris_gamepad_put_key, s);
register_savevm("stellaris_gamepad", -1, 1,
register_savevm(NULL, "stellaris_gamepad", -1, 1,
stellaris_gamepad_save, stellaris_gamepad_load, s);
}

2
hw/syborg_fb.c
View File

@ -526,7 +526,7 @@ static int syborg_fb_init(SysBusDevice *dev)
if (!s->rows)
s->rows = ds_get_height(s->ds);
register_savevm("syborg_framebuffer", -1, 1,
register_savevm(&dev->qdev, "syborg_framebuffer", -1, 1,
syborg_fb_save, syborg_fb_load, s);
return 0;
}

3
hw/syborg_interrupt.c
View File

@ -214,7 +214,8 @@ static int syborg_int_init(SysBusDevice *dev)
sysbus_init_mmio(dev, 0x1000, iomemtype);
s->flags = qemu_mallocz(s->num_irqs * sizeof(syborg_int_flags));
register_savevm("syborg_int", -1, 1, syborg_int_save, syborg_int_load, s);
register_savevm(&dev->qdev, "syborg_int", -1, 1, syborg_int_save,
syborg_int_load, s);
return 0;
}

2
hw/syborg_keyboard.c
View File

@ -220,7 +220,7 @@ static int syborg_keyboard_init(SysBusDevice *dev)
qemu_add_kbd_event_handler(syborg_keyboard_event, s);
register_savevm("syborg_keyboard", -1, 1,
register_savevm(&dev->qdev, "syborg_keyboard", -1, 1,
syborg_keyboard_save, syborg_keyboard_load, s);
return 0;
}

2
hw/syborg_pointer.c
View File

@ -218,7 +218,7 @@ static int syborg_pointer_init(SysBusDevice *dev)
qemu_add_mouse_event_handler(syborg_pointer_event, s, s->absolute,
"Syborg Pointer");
register_savevm("syborg_pointer", -1, 1,
register_savevm(&dev->qdev, "syborg_pointer", -1, 1,
syborg_pointer_save, syborg_pointer_load, s);
return 0;
}

3
hw/syborg_rtc.c
View File

@ -136,7 +136,8 @@ static int syborg_rtc_init(SysBusDevice *dev)
qemu_get_timedate(&tm, 0);
s->offset = (uint64_t)mktime(&tm) * 1000000000;
register_savevm("syborg_rtc", -1, 1, syborg_rtc_save, syborg_rtc_load, s);
register_savevm(&dev->qdev, "syborg_rtc", -1, 1,
syborg_rtc_save, syborg_rtc_load, s);
return 0;
}

2
hw/syborg_serial.c
View File

@ -335,7 +335,7 @@ static int syborg_serial_init(SysBusDevice *dev)
}
s->read_fifo = qemu_mallocz(s->fifo_size * sizeof(s->read_fifo[0]));
register_savevm("syborg_serial", -1, 1,
register_savevm(&dev->qdev, "syborg_serial", -1, 1,
syborg_serial_save, syborg_serial_load, s);
return 0;
}

2
hw/syborg_timer.c
View File

@ -221,7 +221,7 @@ static int syborg_timer_init(SysBusDevice *dev)
bh = qemu_bh_new(syborg_timer_tick, s);
s->timer = ptimer_init(bh);
ptimer_set_freq(s->timer, s->freq);
register_savevm("syborg_timer", -1, 1,
register_savevm(&dev->qdev, "syborg_timer", -1, 1,
syborg_timer_save, syborg_timer_load, s);
return 0;
}

2
hw/tsc2005.c
View File

@ -548,7 +548,7 @@ void *tsc2005_init(qemu_irq pintdav)
"QEMU TSC2005-driven Touchscreen");
qemu_register_reset((void *) tsc2005_reset, s);
register_savevm("tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);
register_savevm(NULL, "tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);
return s;
}

4
hw/tsc210x.c
View File

@ -1143,7 +1143,7 @@ uWireSlave *tsc2102_init(qemu_irq pint)
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
register_savevm(s->name, -1, 0,
register_savevm(NULL, s->name, -1, 0,
tsc210x_save, tsc210x_load, s);
return &s->chip;
@ -1194,7 +1194,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s);
register_savevm(NULL, s->name, -1, 0, tsc210x_save, tsc210x_load, s);
return &s->chip;
}

6
hw/unin_pci.c
View File

@ -158,7 +158,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
register_savevm(&dev->qdev, "uninorth", 0, 1,
pci_unin_save, pci_unin_load, &s->host_state);
qemu_register_reset(pci_unin_reset, &s->host_state);
return 0;
}
@ -178,7 +179,8 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
register_savevm(&dev->qdev, "uninorth", 0, 1,
pci_unin_save, pci_unin_load, &s->host_state);
qemu_register_reset(pci_unin_reset, &s->host_state);
return 0;

2
hw/vga-isa-mm.c
View File

@ -100,7 +100,7 @@ static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);
vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
vmstate_register(0, &vmstate_vga_common, s);
vmstate_register(NULL, 0, &vmstate_vga_common, s);
cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
s->vga.bank_offset = 0;

2
hw/vga-isa.c
View File

@ -37,7 +37,7 @@ int isa_vga_init(void)
vga_common_init(s, VGA_RAM_SIZE);
vga_init(s);
vmstate_register(0, &vmstate_vga_common, s);
vmstate_register(NULL, 0, &vmstate_vga_common, s);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);

3
hw/virtio-balloon.c
View File

@ -270,7 +270,8 @@ VirtIODevice *virtio_balloon_init(DeviceState *dev)
reset_stats(s);
qemu_add_balloon_handler(virtio_balloon_to_target, s);
register_savevm("virtio-balloon", -1, 1, virtio_balloon_save, virtio_balloon_load, s);
register_savevm(dev, "virtio-balloon", -1, 1,
virtio_balloon_save, virtio_balloon_load, s);
return &s->vdev;
}

2
hw/virtio-blk.c
View File

@ -498,7 +498,7 @@ VirtIODevice *virtio_blk_init(DeviceState *dev, BlockConf *conf)
s->vq = virtio_add_queue(&s->vdev, 128, virtio_blk_handle_output);
qemu_add_vm_change_state_handler(virtio_blk_dma_restart_cb, s);
register_savevm("virtio-blk", virtio_blk_id++, 2,
register_savevm(dev, "virtio-blk", virtio_blk_id++, 2,
virtio_blk_save, virtio_blk_load, s);
bdrv_set_removable(s->bs, 0);

4
hw/virtio-net.c
View File

@ -923,7 +923,7 @@ VirtIODevice *virtio_net_init(DeviceState *dev, NICConf *conf)
n->vlans = qemu_mallocz(MAX_VLAN >> 3);
register_savevm("virtio-net", virtio_net_id++, VIRTIO_NET_VM_VERSION,
register_savevm(NULL, "virtio-net", virtio_net_id++, VIRTIO_NET_VM_VERSION,
virtio_net_save, virtio_net_load, n);
n->vmstate = qemu_add_vm_change_state_handler(virtio_net_vmstate_change, n);
@ -941,7 +941,7 @@ void virtio_net_exit(VirtIODevice *vdev)
qemu_purge_queued_packets(&n->nic->nc);
unregister_savevm("virtio-net", n);
unregister_savevm(NULL, "virtio-net", n);
qemu_free(n->mac_table.macs);
qemu_free(n->vlans);

2
hw/virtio-serial-bus.c
View File

@ -784,7 +784,7 @@ VirtIODevice *virtio_serial_init(DeviceState *dev, uint32_t max_nr_ports)
* Register for the savevm section with the virtio-console name
* to preserve backward compat
*/
register_savevm("virtio-console", -1, 2, virtio_serial_save,
register_savevm(dev, "virtio-console", -1, 2, virtio_serial_save,
virtio_serial_load, vser);
return vdev;

2
hw/vmmouse.c
View File

@ -274,7 +274,7 @@ void *vmmouse_init(void *m)
vmport_register(VMMOUSE_STATUS, vmmouse_ioport_read, s);
vmport_register(VMMOUSE_COMMAND, vmmouse_ioport_read, s);
vmport_register(VMMOUSE_DATA, vmmouse_ioport_read, s);
vmstate_register(0, &vmstate_vmmouse, s);
vmstate_register(NULL, 0, &vmstate_vmmouse, s);
return s;
}

2
hw/vmware_vga.c
View File

@ -1169,7 +1169,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
vga_common_init(&s->vga, vga_ram_size);
vga_init(&s->vga);
vmstate_register(0, &vmstate_vga_common, &s->vga);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
vga_init_vbe(&s->vga);

2
hw/zaurus.c
View File

@ -230,7 +230,7 @@ ScoopInfo *scoop_init(PXA2xxState *cpu,
iomemtype = cpu_register_io_memory(scoop_readfn,
scoop_writefn, s);
cpu_register_physical_memory(target_base, 0x1000, iomemtype);
register_savevm("scoop", instance, 1, scoop_save, scoop_load, s);
register_savevm(NULL, "scoop", instance, 1, scoop_save, scoop_load, s);
return s;
}

2
qemu-timer.c
View File

@ -662,7 +662,7 @@ static const VMStateDescription vmstate_timers = {
void configure_icount(const char *option)
{
vmstate_register(0, &vmstate_timers, &timers_state);
vmstate_register(NULL, 0, &vmstate_timers, &timers_state);
if (!option)
return;

22
savevm.c
View File

@ -1023,7 +1023,8 @@ static int calculate_new_instance_id(const char *idstr)
of the system, so instance_id should be removed/replaced.
Meanwhile pass -1 as instance_id if you do not already have a clearly
distinguishing id for all instances of your device class. */
int register_savevm_live(const char *idstr,
int register_savevm_live(DeviceState *dev,
const char *idstr,
int instance_id,
int version_id,
SaveSetParamsHandler *set_params,
@ -1055,18 +1056,19 @@ int register_savevm_live(const char *idstr,
return 0;
}
int register_savevm(const char *idstr,
int register_savevm(DeviceState *dev,
const char *idstr,
int instance_id,
int version_id,
SaveStateHandler *save_state,
LoadStateHandler *load_state,
void *opaque)
{
return register_savevm_live(idstr, instance_id, version_id,
return register_savevm_live(dev, idstr, instance_id, version_id,
NULL, NULL, save_state, load_state, opaque);
}
void unregister_savevm(const char *idstr, void *opaque)
void unregister_savevm(DeviceState *dev, const char *idstr, void *opaque)
{
SaveStateEntry *se, *new_se;
@ -1078,7 +1080,7 @@ void unregister_savevm(const char *idstr, void *opaque)
}
}
int vmstate_register_with_alias_id(int instance_id,
int vmstate_register_with_alias_id(DeviceState *dev, int instance_id,
const VMStateDescription *vmsd,
void *opaque, int alias_id,
int required_for_version)
@ -1109,13 +1111,15 @@ int vmstate_register_with_alias_id(int instance_id,
return 0;
}
int vmstate_register(int instance_id, const VMStateDescription *vmsd,
void *opaque)
int vmstate_register(DeviceState *dev, int instance_id,
const VMStateDescription *vmsd, void *opaque)
{
return vmstate_register_with_alias_id(instance_id, vmsd, opaque, -1, 0);
return vmstate_register_with_alias_id(dev, instance_id, vmsd,
opaque, -1, 0);
}
void vmstate_unregister(const VMStateDescription *vmsd, void *opaque)
void vmstate_unregister(DeviceState *dev, const VMStateDescription *vmsd,
void *opaque)
{
SaveStateEntry *se, *new_se;

5
slirp/slirp.c
View File

@ -232,7 +232,8 @@ Slirp *slirp_init(int restricted, struct in_addr vnetwork,
slirp->opaque = opaque;
register_savevm("slirp", 0, 3, slirp_state_save, slirp_state_load, slirp);
register_savevm(NULL, "slirp", 0, 3,
slirp_state_save, slirp_state_load, slirp);
QTAILQ_INSERT_TAIL(&slirp_instances, slirp, entry);
@ -243,7 +244,7 @@ void slirp_cleanup(Slirp *slirp)
{
QTAILQ_REMOVE(&slirp_instances, slirp, entry);
unregister_savevm("slirp", slirp);
unregister_savevm(NULL, "slirp", slirp);
qemu_free(slirp->tftp_prefix);
qemu_free(slirp->bootp_filename);

2
vl.c
View File

@ -2794,7 +2794,7 @@ int main(int argc, char **argv, char **envp)
if (qemu_opts_foreach(&qemu_drive_opts, drive_init_func, &machine->use_scsi, 1) != 0)
exit(1);
register_savevm_live("ram", 0, 3, NULL, ram_save_live, NULL,
register_savevm_live(NULL, "ram", 0, 3, NULL, ram_save_live, NULL,
ram_load, NULL);
if (nb_numa_nodes > 0) {