The softfloat implementation is still missing (only corner cases are supported).
Extend softfloat floatNN_class methods to distinguish between SNaN and QNaN.
//
// The table lookup was reverse-engineered from VRSQRT14SS instruction implementation available
// in the Intel Software Development Emulator rev6.20 (released February 13, 2014)
// http://software.intel.com/en-us/articles/intel-software-development-emulator/
//
// TODO: find better way to emulate these instructions, I am sure the HW doesn't have 64K entry lookup tables
Now only missed AVX-512 opcodes now are:
512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
//
// The table lookup was reverse-engineered from VRCP14SS instruction implementation available
// in the Intel Software Development Emulator rev6.20 (released February 13, 2014)
// http://software.intel.com/en-us/articles/intel-software-development-emulator/
//
// TODO: find better way to emulate these instructions, I am sure the HW doesn't have 64K entry lookup table
Now only missed AVX-512 opcodes now are:
512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD
512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.
Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code
Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)
Huge patch. Almost all source files wre modified.
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
MSDEV workspaces updated with new file
CPUID will detect and CPU will execute FXSAVE/FXRSTOR instructions when cpu-level-hacked=6 and not only when cpu-level=6
