[ bochs-Bugs-1562172 ] TLB_init() fails to initialize priv_check array if USE_TLB 0
2. Paging is always exists for i386+
To disable paging it is better to use normal model without special code, only by setting cr0.pg=0
* don't initialize cpu specific parameters for the wx debugger if they already
exist
* separate siminterface method init_save_restore() added
* old wx specific handling in quit_sim() removed
* new bx_list_c method clear() deletes all parameters from the list
* moved devices cleanup code from the pc_system to a new devices method exit()
* pc_system init code now sets ticksTotal to 0
2. In init.cc save and restore BX_CPU_THIS__PTR trace value, allows to enable/disable tracing using save/restore.
3. in iret.cc - cleanup3. in iret.cc - cleanup3. in iret.cc - cleanup
* changed data format of text files for save/restore (looks like C/C++ structures,
similar to the format used in old save/restore branches)
* don't set the initial value of shadow bool parameters
* don't set the initial value of bool parameters twice
* cpu/init.cc: missing #undef added
* ne2k.cc: variable tx_timer_active was never set to 1 (type now bx_bool)
* floppy.cc: missing initialization of the 'eot' array in reset() added
* pic.h: type of member 'byte_expected' changed to Bit8u
* pit_wrap.h: unused members removed
* fixed minimum limit of signed variable types
* don't set the initial value of shadow parameters
* fixed range check for shadow parameters
* added support for setting the value base (decimal/hex) of numeric shadow parameters.
The text format hex number is now initialized in the constructor
* added missing newline after filename for binary data
* fixed data size of 64-bit shadow parameters
* fixed save/restore output format of numeric parameters (signed/unsigned/64-bit)
* cpu/init.cc: fixed macro name and added missing #undef line
- Fixed critical bug in CPU code added with one of the prev commits
- Disasm support for SSE4
- Rename PNI->SSE3 everywhere in the code
- Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
- Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
- Fixed ENTER and LEAVE instructions in x86-64 mode
- Added ability to turn ON instruction trace, only GUI support is missed.
Instruction trace could be enabled if Bochs was compiled with disasm
- More changes Bit32u -> bx_phy_address
- Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
- Small code cleanup
- Update CHANGES and user docs
Added two functions to query NMI and SMI from Bochs debugger.
In future they could be used for generating NMI or SMI by user request using GUI button (could be implemented separatelly later and under configure-time or .bocshrc option)
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
I would like all next commits be aware of SMM mode.
It can't be implemented right now (too many questions w/o answers) but it will be done till next major release definitelly.
