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1. Fixed bug report

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[ bochs-Bugs-1562172 ] TLB_init() fails to initialize priv_check array if USE_TLB 0
2. Paging is always exists for i386+
   To disable paging it is better to use normal model without special code, only by setting cr0.pg=0
This commit is contained in:
Stanislav Shwartsman 2006-09-20 17:02:20 +00:00
parent fad22265b5
commit 3ab94305a0
6 changed files with 24 additions and 79 deletions
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1
bochs/config.h.in
View File

@ -135,7 +135,6 @@
// When there are collisions, the old entry is overwritten with
// one for the newest access.
#define BX_SUPPORT_PAGING 1
#define BX_USE_TLB 1
#define BX_TLB_SIZE 1024

4
bochs/cpu/cpu.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.165 2006-06-25 21:44:46 sshwarts Exp $
// $Id: cpu.cc,v 1.166 2006-09-20 17:02:20 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -663,14 +663,12 @@ void BX_CPU_C::prefetch(void)
}
}
#if BX_SUPPORT_PAGING
if (BX_CPU_THIS_PTR cr0.pg) {
// aligned block guaranteed to be all in one page, same A20 address
pAddr = itranslate_linear(laddr, CPL==3);
pAddr = A20ADDR(pAddr);
}
else
#endif // BX_SUPPORT_PAGING
{
pAddr = A20ADDR(laddr);
}

4
bochs/cpu/init.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.123 2006-09-07 18:50:51 vruppert Exp $
// $Id: init.cc,v 1.124 2006-09-20 17:02:20 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -996,11 +996,9 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR EXT = 0;
#if BX_SUPPORT_PAGING
#if BX_USE_TLB
TLB_init();
#endif // BX_USE_TLB
#endif // BX_SUPPORT_PAGING
// invalidate the prefetch queue
BX_CPU_THIS_PTR eipPageBias = 0;

69
bochs/cpu/paging.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.76 2006-06-17 12:09:55 sshwarts Exp $
// $Id: paging.cc,v 1.77 2006-09-20 17:02:20 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -276,8 +276,6 @@
// - Pentium Pro+ processors maintain separate 4K and 4M TLBs.
#endif
#if BX_SUPPORT_PAGING
#define BX_INVALID_TLB_ENTRY 0xffffffff
#if BX_USE_QUICK_TLB_INVALIDATE
@ -292,6 +290,8 @@
# define BX_PRIV_CHECK_SIZE 16
#endif
static unsigned priv_check[BX_PRIV_CHECK_SIZE];
// The 'priv_check' array is used to decide if the current access
// has the proper paging permissions. An index is formed, based
// on parameters such as the access type and level, the write protect
@ -372,18 +372,8 @@
#define TLB_ReadUserPtrOK 0x02
#define TLB_ReadSysPtrOK 0x01
#ifdef __GNUC__
#warning "Move priv_check to CPU fields, or init.cc"
#endif
static unsigned priv_check[BX_PRIV_CHECK_SIZE];
#define PAGE_DIRECTORY_NX_BIT (BX_CONST64(0x8000000000000000))
// === TLB Instrumentation section ==============================
// Note: this is an approximation of what Peter Tattam had.
@ -474,22 +464,25 @@ BX_CPU_C::CR3_change(bx_phy_address value)
BX_CPU_THIS_PTR cr3_masked = value & 0xfffff000;
}
// Called to initialize the TLB upon startup.
// Unconditional initialization of all TLB entries.
void BX_CPU_C::TLB_init(void)
{
// Called to initialize the TLB upon startup.
// Unconditional initialization of all TLB entries.
unsigned i, wp, us_combined, rw_combined, us_current, rw_current;
#if BX_USE_TLB
unsigned i;
unsigned wp, us_combined, rw_combined, us_current, rw_current;
for (i=0; i<BX_TLB_SIZE; i++)
BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
#if BX_USE_QUICK_TLB_INVALIDATE
BX_CPU_THIS_PTR TLB.tlb_invalidate = BX_MAX_TLB_INVALIDATE;
#endif
#endif // #if BX_USE_TLB
//
// Setup privilege check matrix.
//
for (i=0; i<BX_PRIV_CHECK_SIZE; i++) {
wp = (i & 0x10) >> 4;
us_current = (i & 0x08) >> 3;
@ -518,12 +511,6 @@ void BX_CPU_C::TLB_init(void)
}
}
}
#if BX_USE_QUICK_TLB_INVALIDATE
BX_CPU_THIS_PTR TLB.tlb_invalidate = BX_MAX_TLB_INVALIDATE;
#endif
#endif // #if BX_USE_TLB
}
void BX_CPU_C::TLB_flush(bx_bool invalidateGlobal)
@ -1417,35 +1404,3 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
}
}
}
#else // BX_SUPPORT_PAGING
// stub functions for non-support of paging
void BX_CPU_C::CR3_change(bx_phy_address value32)
{
BX_INFO(("CR3_change(): flush TLB cache"));
BX_INFO(("Page Directory Base %08x", (unsigned) value32));
}
void BX_CPU_C::access_linear(Bit32u laddr, unsigned length, unsigned pl,
unsigned rw, void *data)
{
/* perhaps put this check before all code which calls this function,
* so we don't have to here
*/
if (BX_CPU_THIS_PTR cr0.pg == 0) {
if (rw == BX_READ)
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, laddr, length, data);
else
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, laddr, length, data);
return;
}
BX_PANIC(("access_linear: paging not supported"));
}
void BX_CPU_C::INVLPG(bxInstruction_c* i)
{}
#endif // BX_SUPPORT_PAGING

21
bochs/cpu/tasking.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: tasking.cc,v 1.37 2006-08-31 18:18:17 sshwarts Exp $
// $Id: tasking.cc,v 1.38 2006-09-20 17:02:20 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -195,18 +195,14 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
BX_INFO(("TASK SWITCH: switching to the same TSS !"));
}
#if BX_SUPPORT_PAGING
// Check that old TSS, new TSS, and all segment descriptors
// used in the task switch are paged in.
if (BX_CPU_THIS_PTR cr0.pg)
{
// Old TSS
(void) dtranslate_linear(obase32, 0, BX_WRITE);
(void) dtranslate_linear(obase32 + old_TSS_max, 0, BX_WRITE);
// New TSS
(void) dtranslate_linear(nbase32, 0, BX_READ);
(void) dtranslate_linear(nbase32 + new_TSS_max, 0, BX_READ);
dtranslate_linear(obase32, 0, BX_WRITE); // new TSS
dtranslate_linear(obase32 + old_TSS_max, 0, BX_WRITE);
dtranslate_linear(nbase32, 0, BX_READ); // old TSS
dtranslate_linear(nbase32 + new_TSS_max, 0, BX_READ);
// ??? Humm, we check the new TSS region with READ above,
// but sometimes we need to write the link field in that
@ -215,13 +211,12 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
// the written state consistent (ie, we don't encounter a
// page fault in the middle).
if (source==BX_TASK_FROM_CALL_OR_INT)
if (source == BX_TASK_FROM_CALL_OR_INT)
{
(void) dtranslate_linear(nbase32, 0, BX_WRITE);
(void) dtranslate_linear(nbase32 + 2, 0, BX_WRITE);
dtranslate_linear(nbase32, 0, BX_WRITE);
dtranslate_linear(nbase32 + 2, 0, BX_WRITE);
}
}
#endif // BX_SUPPORT_PAGING
// Privilege and busy checks done in CALL, JUMP, INT, IRET

4
bochs/main.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: main.cc,v 1.343 2006-09-16 14:47:40 vruppert Exp $
// $Id: main.cc,v 1.344 2006-09-20 17:02:19 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -954,7 +954,7 @@ int bx_init_hardware()
BX_INFO((" APIC support: %s",BX_SUPPORT_APIC?"yes":"no"));
BX_INFO(("CPU configuration"));
BX_INFO((" level: %d",BX_CPU_LEVEL));
BX_INFO((" paging support: %s, tlb enabled: %s",BX_SUPPORT_PAGING?"yes":"no",BX_USE_TLB?"yes":"no"));
BX_INFO((" TLB enabled: %s",BX_USE_TLB?"yes":"no"));
#if BX_SUPPORT_SMP
BX_INFO((" SMP support: yes, quantum=%d", SIM->get_param_num(BXPN_SMP_QUANTUM)->get()));
#else