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92 Commits

Author SHA1 Message Date
Stanislav Shwartsman
7cc9cffeed remove siminterface.h from bochs.h and include it only where required 2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature 2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
902ff1ef52 Part of the SF patch #548: Support Windows Hyper-V in Bochs by Xinyang 
When BX_SUPPORT_SMP is not defined, clear the bit in CPUID.[EAX=1].Bit[28] to indicate Hyper-Threading is unavailable.
 2020-01-11 06:18:13 +00:00
Stanislav Shwartsman
311ef81e87 fixed comment 2019-12-09 18:16:29 +00:00
Stanislav Shwartsman
0c604d27d1 fixed compilation with no PKEYS enabled 2017-11-12 20:15:48 +00:00
Stanislav Shwartsman
8261a91ce9 implemented GFNI instructions 2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
77a62a4dcd implemented (experimental, still untested) AVX512 VBMI2 extensions 2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
15ba88c195 implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ 2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
944f37b1f2 implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions 2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e implemented AVX-512 VNNI instructions 2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
69f27439db added new cpuid flags mentioned in new Intel SDM future extensions rev030 doc 2017-10-13 20:27:52 +00:00
Stanislav Shwartsman
1a3ff4b438 fixed bogus error message 2017-04-11 18:35:17 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
be4b73c6d2 extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class 2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
b60d7d3154 Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class 
Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
 2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
6700a3f5e6 fix cpuid patch merged 2014-12-16 06:52:24 +00:00
Volker Ruppert
b7c8323633 Fixed panic in case x86-64 support is not present (Bochs 2.6.7 P4-SMP release 
binaries are already fixed).
Usual updates after release (version strings, release tag).
 2014-11-02 14:14:36 +00:00
Stanislav Shwartsman
5f4e7f8b49 fixed compilation when APIC if snot enabled 2014-11-01 10:25:42 +00:00
Stanislav Shwartsman
54a009ccf9 update CHANGES. added BX_INFO prints related to Perfmon usage 2014-10-15 19:04:28 +00:00
Stanislav Shwartsman
caab07e580 move common code (extended topology leaf) into base cpuid class to save code duplication 2014-10-15 14:25:08 +00:00
Stanislav Shwartsman
f8267ec3a7 rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented 2014-10-15 08:04:38 +00:00
Stanislav Shwartsman
e2e6f5a62b Update CPUID defines after recently published 
Intel Architecture Instruction Set Extensions Programming Reference rev-021

Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions

still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
 2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
5413b5c31b don't forget to initialize (clear) cpu features bitmask in the beginning ... 2014-08-31 19:48:58 +00:00
Stanislav Shwartsman
9f57e70d5f Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions 
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
 2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
97d2965d58 continue xsave code rework 2014-03-16 20:37:47 +00:00
Stanislav Shwartsman
9d8d895b52 cpuid fixes 2014-03-15 20:19:30 +00:00
Stanislav Shwartsman
5724013e7d updates to AVX512 decoding and CPUID 2013-10-07 20:39:34 +00:00
Stanislav Shwartsman
b6c39a3176 merge AVX and SSE .bochsrc options to single SIMD option which will configure SSE and AVX together 2013-09-16 19:50:36 +00:00
Stanislav Shwartsman
0fd4e3450c update (c) for few files 2013-09-05 18:40:14 +00:00
Volker Ruppert
7c0a261751 final fix for BX_CPU_LEVEL 4 2013-09-05 06:42:17 +00:00
Stanislav Shwartsman
bb695fd5f5 remove redundant (and incorrect) check 2013-09-04 16:47:52 +00:00
Stanislav Shwartsman
c2558f52d6 generic_cpuid: fixed xsave cpuid leaf when xsave is disabled (need to clear output) 2013-08-29 19:58:31 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
852b5c3749 implemented SHA new instructions announced in recent Intel SDM extensions document rev015 2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
fd71b03353 add some definitions introduced in recent Intel SDM extensions document (rev015) 2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
91b3417e57 small bugfix 2013-06-23 15:45:25 +00:00
Stanislav Shwartsman
b950de7155 add more vmx capabilities to generic cpu 2013-05-20 18:18:52 +00:00
Stanislav Shwartsman
694dc8a0e1 fixed generic cpuid leafs - all std leafs > 2 were corrupted 2013-05-06 20:33:27 +00:00
Stanislav Shwartsman
139ec7d538 PANIC on options which require P6 when CPU_LEVEL is set to 5 instead of ignoring them 2013-04-17 20:24:12 +00:00
Stanislav Shwartsman
9b958b3a05 allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6 2013-04-17 19:46:11 +00:00
Stanislav Shwartsman
ce2751a13c move misaligned_sse from compile time to .bochsrc option 2012-12-20 19:43:11 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
5d66e8450e implemented ADCX/ADOX instructions from rev013 of arch extensions published by Intel 2012-07-12 14:51:54 +00:00
Stanislav Shwartsman
7bae496840 fixed valgrind issues in apic initialization and generic cpuid reported in SF bug report 2012-06-04 14:27:34 +00:00
Stanislav Shwartsman
6180a0a733 remove unused leafs from generic_cpuid 2012-05-11 06:51:04 +00:00
Stanislav Shwartsman
f48317affc SVM: Added EXITINFO2 write on VMEXIT (missed in prev commit) 
Added phenom_8650_toliman <AMD Phenom X3 8650 (Toliman)> comment into .bochsrc example with all other supported CPU configs.
Added missed SVM definitions into Toliman CPUDB module
 2012-02-19 20:15:23 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit ! 
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
 2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
f5d55f5eb6 - Implemented Task Switch intercept in SVM, cleanup in task switch handling code 
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
 2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
8d698c7087 fixed compilation err ith cpu-level=5 and cleanups 2012-01-09 20:52:15 +00:00