mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10,143 Commits 11 Branches 185 Tags 48 MiB
81affbe328
Commit Graph

2821 Commits

Author SHA1 Message Date
Stanislav Shwartsman
81affbe328 fixed incorrect lock prefix detection 2013-08-30 20:08:04 +00:00
Stanislav Shwartsman
c2558f52d6 generic_cpuid: fixed xsave cpuid leaf when xsave is disabled (need to clear output) 2013-08-29 19:58:31 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
7e2ab5ca81 decode simplification for AMD XOP prefix 2013-08-28 19:56:19 +00:00
Stanislav Shwartsman
5d61c19b0b evex support - step2 2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
5fe5bf1ed6 fixed alias typo corrupting avx opcodes 2013-08-27 19:45:31 +00:00
Stanislav Shwartsman
c5f72033ad correct vzeroupper opcode 2013-08-27 06:57:48 +00:00
Stanislav Shwartsman
735154a755 oops, typo bug in prev commit 2013-08-24 19:46:04 +00:00
Stanislav Shwartsman
65e6760915 small decode optimization 2013-08-24 19:29:43 +00:00
Stanislav Shwartsman
748a0da712 one more step in the way towards avx-512 which have more vector registers 2013-08-24 12:12:10 +00:00
Stanislav Shwartsman
701d88388e fixed FCS/FDS deprecation 2013-08-22 20:21:36 +00:00
Stanislav Shwartsman
3a7e336cb6 more opcode alias - now VEX.W alias 2013-08-21 18:45:36 +00:00
Stanislav Shwartsman
115ec37a4c make decoder tables smaller using decode aliases 2013-08-21 04:52:49 +00:00
Stanislav Shwartsman
33a7063e60 bug fixes 2013-08-05 15:33:41 +00:00
Stanislav Shwartsman
362b99eba0 fixed typo in last commit 2013-08-04 19:47:19 +00:00
Stanislav Shwartsman
3fabcb00b7 VMX: CMPXHG instructions should always write to the memory destination, even if the value unchanged - it affects VMEXIT conditions for the full apic virtualization 
Fixed also CMPXHG16B instruction (last one, others were fixed earlier)
 2013-08-04 19:37:04 +00:00
Stanislav Shwartsman
7005afd3a8 clean up BxRepeatable attribute - not needed anymore after VL AVX field moved to new location 2013-07-26 15:42:49 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
0da1d659d3 CMPXHG should always write to memory dest - affects APIC virtualization VMEXIT conditions 2013-07-24 21:06:24 +00:00
Stanislav Shwartsman
54d3dc4353 properly added sha.cc to the tree 2013-07-24 18:56:37 +00:00
Stanislav Shwartsman
2357dc5ccc Fixed number of invocations of the BX_INSTR_LIN_ACCESS instrumentation callback in cpu/access32.cc, cpu/access64.cc and cpu/paging.cc specify the BX_READ memory access type where BX_RW really applies. 
SF Patch #1335 by Mateusz Jurczyk
 2013-07-24 18:54:18 +00:00
Stanislav Shwartsman
4c7031962e added new sha.cc file 2013-07-24 18:47:28 +00:00
Stanislav Shwartsman
852b5c3749 implemented SHA new instructions announced in recent Intel SDM extensions document rev015 2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
fd71b03353 add some definitions introduced in recent Intel SDM extensions document (rev015) 2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
4a36fb3edc fixed debug print message for BOUND instruction 2013-07-22 18:52:15 +00:00
Stanislav Shwartsman
148cb1aee0 Thanks to avanced trace linking 256K entries ICache is not needed anymore. 
Reduce to 64K entries and save memory.
 2013-06-29 10:25:56 +00:00
Stanislav Shwartsman
ef0d2142ab Allow cross-page trace linking again. 
The SMC problem was solved in following manner:

 - Every trace linked to another remembers when it was linked (a special timestamp value called traceLinkTimeStamp)
 - When true SMC happens it incremements the traceLinkTimeStamp
 - Jump to the linked trace won't be allowed if traceLinkTimeStamp in the link doesn't match traceLinkTimeStamp

So SMC effectively breaks all trace links and therefore I should not care for them anymore

5%-10% speedup on OS boot benchamarks observed
 2013-06-29 10:16:28 +00:00
Stanislav Shwartsman
0276bdfb3e still not allow cross page linking until SMC issue will be solved - cause Win98 crash 2013-06-28 07:51:42 +00:00
Stanislav Shwartsman
c42afb0a2d allow linking of traces cross 4K page boundary 2013-06-23 21:12:03 +00:00
Stanislav Shwartsman
91b3417e57 small bugfix 2013-06-23 15:45:25 +00:00
Stanislav Shwartsman
d30d1ac93a small bugfix 2013-06-21 14:12:46 +00:00
Stanislav Shwartsman
c7698a5589 implemented fcs/fds deprecation. added haswell to cpudb.h as well 2013-06-20 20:12:53 +00:00
Stanislav Shwartsman
b335f472bd Added Haswell configuration to CPUDB 2013-06-20 19:33:30 +00:00
Stanislav Shwartsman
769d35b06c remove debug print from Sandy Bridge CPUID wrongly commited 2013-06-15 17:57:03 +00:00
Stanislav Shwartsman
edc3003f35 do not use cpuid:level param when it doesn't exists 2013-06-15 17:53:49 +00:00
Stanislav Shwartsman
9651b5d53c bugfix: vmx preemption timer vmexit should not wakeup CPU from sleep state. cpuid: added definitions from recently published intel SDM rev047 2013-06-04 20:28:27 +00:00
Stanislav Shwartsman
b950de7155 add more vmx capabilities to generic cpu 2013-05-20 18:18:52 +00:00
Stanislav Shwartsman
964583a40f Added X2APIC support to Ivy Bridge configuration 2013-05-20 18:15:35 +00:00
Stanislav Shwartsman
2bca9b8273 updates in CPUID defines after new published AMD SDM 2013-05-17 19:41:57 +00:00
Stanislav Shwartsman
1304b3fb4b Do not report Architectural Performance Monitoring in CPUID 
Reporting true capabilities breaks Win7 x64 installation
 2013-05-07 15:34:58 +00:00
Stanislav Shwartsman
694dc8a0e1 fixed generic cpuid leafs - all std leafs > 2 were corrupted 2013-05-06 20:33:27 +00:00
Stanislav Shwartsman
b2b42dd714 small fix for LOAD_SS interrupts inhibit 2013-05-04 19:10:50 +00:00
Stanislav Shwartsman
139ec7d538 PANIC on options which require P6 when CPU_LEVEL is set to 5 instead of ignoring them 2013-04-17 20:24:12 +00:00
Stanislav Shwartsman
3fbdf7ff03 do not recognize MTRR MSRs when mtrr is not enabled 2013-04-17 19:59:56 +00:00
Stanislav Shwartsman
9b958b3a05 allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6 2013-04-17 19:46:11 +00:00
Stanislav Shwartsman
025fb15461 properly handle RDMSR/WRMSR of MSR_PAT when PAT feature is disabled 2013-04-11 19:41:54 +00:00
Stanislav Shwartsman
f1c7d163a1 activity state is ignored when vmenter injecting event 2013-04-09 20:36:02 +00:00
Stanislav Shwartsman
a277d60d89 implemented vmentering to non-active cpu state 2013-04-09 15:43:15 +00:00
Stanislav Shwartsman
6a8357105b fix for guest segment AR field size 2013-04-08 17:29:00 +00:00
Stanislav Shwartsman
13a6524acb hw task switch tempdr6 hanlding fix 2013-03-15 08:26:22 +00:00