Commit Graph

2796 Commits

Author SHA1 Message Date
Stanislav Shwartsman
148cb1aee0 Thanks to avanced trace linking 256K entries ICache is not needed anymore.
Reduce to 64K entries and save memory.
2013-06-29 10:25:56 +00:00
Stanislav Shwartsman
ef0d2142ab Allow cross-page trace linking again.
The SMC problem was solved in following manner:

 - Every trace linked to another remembers when it was linked (a special timestamp value called traceLinkTimeStamp)
 - When true SMC happens it incremements the traceLinkTimeStamp
 - Jump to the linked trace won't be allowed if traceLinkTimeStamp in the link doesn't match traceLinkTimeStamp

So SMC effectively breaks all trace links and therefore I should not care for them anymore

5%-10% speedup on OS boot benchamarks observed
2013-06-29 10:16:28 +00:00
Stanislav Shwartsman
0276bdfb3e still not allow cross page linking until SMC issue will be solved - cause Win98 crash 2013-06-28 07:51:42 +00:00
Stanislav Shwartsman
c42afb0a2d allow linking of traces cross 4K page boundary 2013-06-23 21:12:03 +00:00
Stanislav Shwartsman
91b3417e57 small bugfix 2013-06-23 15:45:25 +00:00
Stanislav Shwartsman
d30d1ac93a small bugfix 2013-06-21 14:12:46 +00:00
Stanislav Shwartsman
c7698a5589 implemented fcs/fds deprecation. added haswell to cpudb.h as well 2013-06-20 20:12:53 +00:00
Stanislav Shwartsman
b335f472bd Added Haswell configuration to CPUDB 2013-06-20 19:33:30 +00:00
Stanislav Shwartsman
769d35b06c remove debug print from Sandy Bridge CPUID wrongly commited 2013-06-15 17:57:03 +00:00
Stanislav Shwartsman
edc3003f35 do not use cpuid:level param when it doesn't exists 2013-06-15 17:53:49 +00:00
Stanislav Shwartsman
9651b5d53c bugfix: vmx preemption timer vmexit should not wakeup CPU from sleep state. cpuid: added definitions from recently published intel SDM rev047 2013-06-04 20:28:27 +00:00
Stanislav Shwartsman
b950de7155 add more vmx capabilities to generic cpu 2013-05-20 18:18:52 +00:00
Stanislav Shwartsman
964583a40f Added X2APIC support to Ivy Bridge configuration 2013-05-20 18:15:35 +00:00
Stanislav Shwartsman
2bca9b8273 updates in CPUID defines after new published AMD SDM 2013-05-17 19:41:57 +00:00
Stanislav Shwartsman
1304b3fb4b Do not report Architectural Performance Monitoring in CPUID
Reporting true capabilities breaks Win7 x64 installation
2013-05-07 15:34:58 +00:00
Stanislav Shwartsman
694dc8a0e1 fixed generic cpuid leafs - all std leafs > 2 were corrupted 2013-05-06 20:33:27 +00:00
Stanislav Shwartsman
b2b42dd714 small fix for LOAD_SS interrupts inhibit 2013-05-04 19:10:50 +00:00
Stanislav Shwartsman
139ec7d538 PANIC on options which require P6 when CPU_LEVEL is set to 5 instead of ignoring them 2013-04-17 20:24:12 +00:00
Stanislav Shwartsman
3fbdf7ff03 do not recognize MTRR MSRs when mtrr is not enabled 2013-04-17 19:59:56 +00:00
Stanislav Shwartsman
9b958b3a05 allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6 2013-04-17 19:46:11 +00:00
Stanislav Shwartsman
025fb15461 properly handle RDMSR/WRMSR of MSR_PAT when PAT feature is disabled 2013-04-11 19:41:54 +00:00
Stanislav Shwartsman
f1c7d163a1 activity state is ignored when vmenter injecting event 2013-04-09 20:36:02 +00:00
Stanislav Shwartsman
a277d60d89 implemented vmentering to non-active cpu state 2013-04-09 15:43:15 +00:00
Stanislav Shwartsman
6a8357105b fix for guest segment AR field size 2013-04-08 17:29:00 +00:00
Stanislav Shwartsman
13a6524acb hw task switch tempdr6 hanlding fix 2013-03-15 08:26:22 +00:00
Stanislav Shwartsman
913e3defd1 fixed SIPI delivery bug from one the latest checkins 2013-03-13 19:06:55 +00:00
Stanislav Shwartsman
53d14c01b5 correctly signal bit 12 (nmi unblocking by iret) in vmx interruption info. todo: find how to implement it clean way 2013-03-06 21:11:23 +00:00
Stanislav Shwartsman
1a770dd260 implementation of virtual NMI 2013-03-05 21:12:43 +00:00
Stanislav Shwartsman
39ae66b5a3 Suppress 'entering paged real mode' CR0 check for SVM guest
After a lot of thinking and browsing in the SVM arch forums I assume now that it shold be fine to enter to paged real mode under SVM guest.
The test case to consider:

  (paged) real mode guest -> entering Pmode (not paged) -> disabling the Pmode back

Ths assumption still should be validated with real AMD hardware

Context: AMD's manual about CR0 intercept priority :
	"Checks non-memory exceptions (CPL, illegal bit combinations, etc.) before the intercept"

The check for 'paged real mode' suposed to be illegal bit combination ...
2013-02-27 19:11:28 +00:00
Stanislav Shwartsman
ab63b22a68 SVM: implemented missed RSM, LDTR READ/WRITE, TR READ/WRITE and IRET intercepts 2013-02-25 19:36:41 +00:00
Stanislav Shwartsman
8708d05bea rename some VMX controls to match intel docs. added missed VMX consistency check 2013-02-24 20:22:22 +00:00
Volker Ruppert
058c0e05fb - removed wx debugger dialogs (enhanced gui debugger now almost stable with wx) 2013-02-16 12:22:13 +00:00
Stanislav Shwartsman
e43ac349a6 fixed injected exception err code check for unrestricted guests 2013-02-14 19:31:42 +00:00
Stanislav Shwartsman
40669115e1 use different formatter for printing phy address in paging dbg messages 2013-02-14 19:30:59 +00:00
Volker Ruppert
97de484efb use enhanced gui debugger instead of classic wx debugger if BX_DEBUGGER_GUI == 1
The Windows version looks almost stable, but the GTK version fails in some cases.
That's why the classic wx debugger is still available if BX_DEBUGGER_GUI is set to 0.
- added function close_debug_dialog() to handle the simulation stop case in wx
- disable all the wx debugger related code if BX_DEBUGGER_GUI is set to 1
- added enhanced debugger specific init code similar to the code in sdl.cc
- include debugger related resources on Windows
- TODO: make the GTK / wxGTK case stable and remove the wx debugger
2013-02-12 21:08:35 +00:00
Stanislav Shwartsman
ec971d0ce8 add #VE exception specific VMCS fields into VMCS bitmap 2013-01-28 20:20:54 +00:00
Stanislav Shwartsman
863e1a0f8a fixed compilation with debugger enabled 2013-01-28 18:26:56 +00:00
Stanislav Shwartsman
64df073617 implemented virtualization exception feature 2013-01-28 16:30:25 +00:00
Stanislav Shwartsman
d38fce8218 preparation for future extension in translate_linear - I would like to return data to caller through tlbEntry 2013-01-27 19:27:30 +00:00
Stanislav Shwartsman
016e112ac2 fixed compilation err with vmx=1 2013-01-23 19:04:53 +00:00
Stanislav Shwartsman
a0c9522fef fix compilation with no vmx enabled 2013-01-22 19:06:20 +00:00
Stanislav Shwartsman
8865df606a fixed typo bug in VMX code 2013-01-22 08:39:41 +00:00
Stanislav Shwartsman
608775cd5a vmread/vmwrite should always check for CPL, also when in vmx guest 2013-01-21 20:20:14 +00:00
Stanislav Shwartsman
3ab0331307 implemented VMCS shadowing (Intel SDM rev045) 2013-01-21 19:55:00 +00:00
Stanislav Shwartsman
9e896ce0bf SFENCE instruction doesn't require SSE2 2013-01-20 17:56:08 +00:00
Stanislav Shwartsman
4bed791ccb Added year 2013 to Copyright in all files already modified in new year 2013-01-19 20:45:03 +00:00
Stanislav Shwartsman
05d36f0acc fixed performance bug in smap/smep fix - tlb never had user executable page permission 2013-01-19 20:14:44 +00:00
Stanislav Shwartsman
eda28b95f4 unfortunately this change is rquired to make SMAP and SMEP features to work.
I observed ~5% emulation slowdown ... thinking about possible mitigations

this fixes TLB issue with SMAP and SMEP features.
these features introduce a new behavior when page can be inaccessible by System (CPL=0).
Current behavior is accessBits was not supporting it but legacy (from Bochs 2.3.6) was.
The wrong behavior can be observed if user access a user page and system access the same page later.
user access is fine and pass SMEP/SMA checks and stores the translation in TLB.
the system access will hit the TLB and nobody could detect that system cannot access that page.
2013-01-16 17:28:20 +00:00
Stanislav Shwartsman
c337b7babb Intel Software Developers Manual rev45 was released
Added CPUID bits and preparations for newly documented VMX features
2013-01-16 16:57:48 +00:00
Stanislav Shwartsman
c96f5e27a9 flush tlb also when cr4.smap changes 2013-01-14 17:02:51 +00:00