Stanislav Shwartsman
74c73e5a76
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-20 15:34:14 +00:00
Stanislav Shwartsman
0e5d843597
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-20 14:58:56 +00:00
Stanislav Shwartsman
cff6a67adb
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-20 14:57:42 +00:00
Stanislav Shwartsman
9fbf974e6b
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-20 13:45:00 +00:00
Stanislav Shwartsman
222185ad11
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-20 13:42:59 +00:00
Stanislav Shwartsman
ec5f526ac0
ENBRANCH and RDSSP should remain NOP when CET not enabled, this means they not require an specifical CPU feature to be decoded into the hnadler
2019-12-20 13:16:52 +00:00
Stanislav Shwartsman
f90e5f4f44
Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
...
Only missing items (to be added soon):
- Supervisor Shadow Stack EPT Control is not implemented yet
- SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
39aee8773f
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-19 21:21:24 +00:00
Stanislav Shwartsman
682fbda5af
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-19 21:12:47 +00:00
Stanislav Shwartsman
2df60c3b3f
AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
2019-12-19 20:08:49 +00:00
Stanislav Shwartsman
019c934cfd
decode GFNI opcodes in 64-bit mode too
2019-12-18 19:55:04 +00:00
Stanislav Shwartsman
6d612df280
AVX512_BITALG: Fixed decoding of VPSHUFBITQMB instruction
2019-12-13 14:11:08 +00:00
Stanislav Shwartsman
c9ac9a1e43
AVX512_VBMI: Fixed decoding of VPERMB instruction
2019-12-13 13:24:02 +00:00
Stanislav Shwartsman
fc79466dcb
AVX512_VBMI: Fixed decoding of VPERMI2B/VPERMT2B instructions
2019-12-13 13:08:45 +00:00
Stanislav Shwartsman
eb009ddd00
fixed VPACKSSDW/VPACKUSDW opcodes - allow broadcast
2019-12-13 12:53:48 +00:00
Stanislav Shwartsman
f9d04849b3
fixed decoding for VPSHLDVW/VPSHRDVW/VPSHLDVD/VPSHLDVQ/VPSHRDVD/VPSHRDVQ
2019-12-13 12:34:16 +00:00
Stanislav Shwartsman
9bbf43ed4b
fixed decoding of AVX512_VNNI instructions
2019-12-13 08:39:23 +00:00
Stanislav Shwartsman
27e96c807c
fixed decoding of VPBROADCASTMW2D opcode
2019-12-13 08:09:18 +00:00
Stanislav Shwartsman
44b3ebeca2
remove BX_TRUE/BX_FALSE macros, use stdc++ true/false instead
2019-12-09 16:44:36 +00:00
Stanislav Shwartsman
4e9e3f85de
simplify code by merging two opcodes with similar behavior
2019-11-27 15:31:32 +00:00
Stanislav Shwartsman
7833a82347
fixed bug in instruction decoding - regression before release
2019-11-22 17:46:54 +00:00
Stanislav Shwartsman
46b862fe5e
do not truncate disasm branch target in 64-bit mode
2019-11-20 20:41:03 +00:00
Stanislav Shwartsman
a030d03935
fixed bug in instruction decoding - regression before release
2019-11-20 20:18:22 +00:00
Stanislav Shwartsman
83846cc821
fixed bug in instruction decoding - regression before release
2019-11-20 20:11:00 +00:00
Stanislav Shwartsman
82b6f7cb6c
fixed bug in instruction decoding - regression before release
2019-11-20 19:58:51 +00:00
Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
eec720c62b
convert bochs.h macros to inline functions with strong types
2019-10-16 20:46:00 +00:00
Stanislav Shwartsman
f0245b5f2b
introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode
2019-10-14 06:40:19 +00:00
Stanislav Shwartsman
49ebaf8397
typofix: attached MASK_K0 attr to wrong opcode
2019-05-25 19:10:55 +00:00
Stanislav Shwartsman
bc4af1b08d
add missing break statement in disasm.cc
2019-05-25 19:08:39 +00:00
Stanislav Shwartsman
4d10852c04
impemented recently published VP2INTERSECTD/Q instructions
2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
662b252507
added missing endif
2019-04-17 16:04:34 +00:00
Stanislav Shwartsman
a022d71774
fixed compilation
2019-04-14 04:05:04 +00:00
Stanislav Shwartsman
54bdb24e4b
remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name
2019-02-22 19:15:53 +00:00
Stanislav Shwartsman
3e007fbdea
fixed copy-pasted issue with decoding
2019-02-17 21:54:38 +00:00
Stanislav Shwartsman
c3f7a34cf5
fixed copy-pasted issue with decoding
2019-02-17 21:41:45 +00:00
Stanislav Shwartsman
3da93728b3
split some opcode reference tables in new decoder between x86-64 and 32 for better perf
2019-02-17 21:22:54 +00:00
Stanislav Shwartsman
cd79d22113
fixes for 32-bit mode only compilation
2019-02-16 19:42:04 +00:00
Stanislav Shwartsman
4f625b23e0
enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
2019-02-16 15:23:24 +00:00
Stanislav Shwartsman
61dcc4ace7
remove unreferenced decode table
2019-01-29 13:44:39 +00:00
Stanislav Shwartsman
f8ec18acd5
fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes
2019-01-27 18:52:03 +00:00
Stanislav Shwartsman
0b18a42e4e
fixed decoding of AVX-512 opcodes
2019-01-27 17:35:21 +00:00
Stanislav Shwartsman
5cb4639891
fixed decoding of AVX-512 opcodes
2019-01-27 17:31:28 +00:00
Stanislav Shwartsman
6dc5cfe80b
fixed typo in opcode name
2019-01-24 20:10:46 +00:00
Stanislav Shwartsman
af75c2a81e
fixed comment in the opcode table for EVEX
2019-01-22 18:31:39 +00:00
Stanislav Shwartsman
9bc7faf493
dump all supported CPU fetures into Bochs log from CPUID object
2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
fcd9ce1634
fix compilation without x86_64
2018-04-15 14:22:16 +00:00
Stanislav Shwartsman
d000e21001
added MOVDIRI opcode implementation
2018-04-06 05:06:36 +00:00
Stanislav Shwartsman
fd15b61d94
keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
8c9f7f54b6
update CPUID definitions with recently published EAS-33 extensions document
2018-04-04 18:15:44 +00:00
