Stanislav Shwartsman 83846cc821 fixed bug in instruction decoding - regression before release

2019-11-20 20:11:00 +00:00

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decoder.h

implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition

2019-10-26 20:09:30 +00:00

disasm.cc

add missing break statement in disasm.cc

2019-05-25 19:08:39 +00:00

fetchdecode32.cc

introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode

2019-10-14 06:40:19 +00:00

fetchdecode64.cc

introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode

2019-10-14 06:40:19 +00:00

fetchdecode_avx.h

fixed bug in instruction decoding - regression before release

2019-11-20 20:11:00 +00:00

fetchdecode_evex.h

typofix: attached MASK_K0 attr to wrong opcode

2019-05-25 19:10:55 +00:00

fetchdecode_opmap_0f3a.h

enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore

2019-02-16 15:23:24 +00:00

fetchdecode_opmap_0f38.h

added missing endif

2019-04-17 16:04:34 +00:00

fetchdecode_opmap.h

introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode

2019-10-14 06:40:19 +00:00

fetchdecode_x87.h

…

fetchdecode_xop.h

enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore

2019-02-16 15:23:24 +00:00

fetchdecode.h

convert bochs.h macros to inline functions with strong types

2019-10-16 20:46:00 +00:00

ia_opcodes.def

introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode

2019-10-14 06:40:19 +00:00

ia_opcodes.h

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instr.h

split some opcode reference tables in new decoder between x86-64 and 32 for better perf

2019-02-17 21:22:54 +00:00