mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
12,953 Commits 11 Branches 185 Tags 48 MiB
620d091264
Commit Graph

210 Commits

Author SHA1 Message Date
Stanislav Shwartsman
18deee022f
make CPU to use C++ template for implementation of CPU methods (#115) 
this allow to remove a lot of code from CPU common methods
 2023-10-30 06:57:16 +02:00
Shwartsman
221cac7972 fixed compilation with no EVEX 2023-10-16 08:14:03 +03:00
Stanislav Shwartsman
a3d2fec111 Merge branch 'master' of https://github.com/bochs-emu/Bochs 2023-10-16 00:19:45 +03:00
Stanislav Shwartsman
035695f73c define CPU feature's enum together with feature name in one place 2023-10-15 23:56:11 +03:00
Stanislav Shwartsman
8e6bdcb4d9 define CPU feature's enum together with feature name in one place 2023-10-15 23:43:14 +03:00
Stanislav Shwartsman
8316d7698f
implemented Linear Address Separation extension (LASS) (#90) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-15 14:32:01 +03:00
Stanislav Shwartsman
ffa64461ab
implementation of AVX-NE-CONVERT ISA (#89) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-14 14:55:12 +03:00
Stanislav Shwartsman
9917227a56 enable CPUID reporting for recently added ISA extensions 
more steps towards more generic CPUID code
 2023-10-12 21:48:09 +03:00
Stanislav Shwartsman
dd7d4dbd82 implement SERIALIZE instruction 
enable CPUID reporting for all recently added ISA extensions
 2023-10-12 14:46:27 +03:00
Stanislav Shwartsman
4a309478f9
SHA512 instructions implemented (#88) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 21:33:16 +03:00
Stanislav Shwartsman
3234e9b88e
implemented AVX VNNI INT16 ISA extension (#87) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 20:22:07 +03:00
Stanislav Shwartsman
44eea71f37
implemented SM3 instructions (#84) 
add rol/ror methods to scalar_arith.h and use in more places

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-07 21:34:04 +03:00
Stanislav Shwartsman
7e909a6fa5 rename CPUID flags to match leaf numbers 2023-10-07 18:10:20 +03:00
Shwartsman
6307786ded automatically determine MCE/MCA CPUID flags 2023-10-07 01:51:18 +03:00
Shwartsman
6d83b5239e another code duplication fix in CPUDB code 2023-10-07 01:36:05 +03:00
Shwartsman
20dfe7c7d0 improve comment 2023-10-07 01:09:22 +03:00
Shwartsman
672c93c7c4 reduce code duplication using new CPUID methods 2023-10-07 01:02:39 +03:00
Shwartsman
5fc6302b1b add one more CPUID method for future use + fix compilation after prev commit 2023-10-07 00:10:18 +03:00
Shwartsman
f50419429d Fix code duplication for CPUID ECX leaf 0x1, implement with common function for all CPUs 2023-10-06 22:53:30 +03:00
Stanislav Shwartsman
0e4524f38f Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
Stanislav Shwartsman
a56144833a add support for AVX encoded VNNI INT8 extensions 2022-10-02 23:00:46 +03:00
Stanislav Shwartsman
3a20495db8 implemented WRMSRNS extension - Non Serializing version of WRMSR opcode 2022-10-02 22:16:02 +03:00
Stanislav Shwartsman
9f76eaacea implemented AVX IFMA instructions 2022-10-02 22:08:20 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
2ab50c7d66 solve code duplication between different cpudb models 2021-02-16 18:57:49 +00:00
Stanislav Shwartsman
7cc9cffeed remove siminterface.h from bochs.h and include it only where required 2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature 2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
c6050a99d1 implemented AVX encoded VNNI instructions published in recent SDM - not tested yet 2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d implemented (experimental) TSC Adjust MSR 2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
8c385f2a9a fix in cpu features print 2019-12-06 11:05:05 +00:00
Stanislav Shwartsman
7861ff5160 fixed typo in feature name 2019-12-06 10:39:42 +00:00
Stanislav Shwartsman
0c75e0beaf extract xcr0_support bits calculation to a function 2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
893aa10359 cosmetic changes 2019-12-04 19:53:08 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
2eb47f866f added minor clarifications based on most recent AMD SDM published 2019-07-30 18:17:21 +00:00
Stanislav Shwartsman
4d10852c04 impemented recently published VP2INTERSECTD/Q instructions 2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
0c28705b18 fixed compilation under MAC env 2019-05-18 04:50:07 +00:00
Stanislav Shwartsman
54bdb24e4b remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name 2019-02-22 19:15:53 +00:00
Stanislav Shwartsman
9bc7faf493 dump all supported CPU fetures into Bochs log from CPUID object 2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
a8413aa838 update comments base on latest AMD spec 2018-05-27 18:13:24 +00:00
Stanislav Shwartsman
31d29734d6 some comments about more CPUID leaf 80000008.EBX by Ryzen 2017-03-28 19:11:42 +00:00
Stanislav Shwartsman
e5c64b3b56 cleanup of warning messages from cpuid code 2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
ebbf8f9e0f adjustments in AMD Ryzen CPUID 2017-03-15 22:14:10 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
402e2cfad0 move cpuid warning messages to base cpuid class - reduce code cleanup 2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
980eaa7937 move cpuid leaf 80000008 to base bx_cpuid_t class to remove code dupolication 2017-03-09 21:25:18 +00:00