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76 Commits

Author SHA1 Message Date
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
8099fd9efd implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8 2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
9693bacacb syscall/sysret in legacy mode is supported in k6-2. preparing code to it ... 2011-08-30 20:41:00 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
ed9b8478b5 undo RDTSC commit 2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf separate TSC to uniq feature that can be disabled in CPU configuration 2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
35ec48d17d small fixes 2011-08-13 18:39:17 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
6344c6a719 Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class 
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
 2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
5451be2676 remove duplicated code 2011-08-03 18:09:07 +00:00
Stanislav Shwartsman
b9a44a9dbf added const to all cpudb methods 2011-08-01 18:10:48 +00:00
Stanislav Shwartsman
d84dbcd02b fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h 2011-07-31 20:09:04 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
1a051f9f00 Added several predefined CPUs that can be selected from .bochsrc using new CPU::MODEL option. 
Selecting CPU MODEL from .bochsrc automatically chooses real HW CPUID and also configures Bochs emulator to emulate this specific CPU including all its features only.
Supported CPUs to choose from:
	core2_extreme_x9770
	corei7_sandy_bridge_2600K
	p4_prescott_celeron_336
 2011-07-29 15:03:54 +00:00
Stanislav Shwartsman
78327d3e5e First step toward completely configurable CPU. 
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
 2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
a69eeb13f3 move cpuid defs to cpuid.h 2011-07-19 21:14:07 +00:00
Stanislav Shwartsman
8399dee24c implemented AVX float16 convert instructions 2011-06-11 13:12:32 +00:00
Stanislav Shwartsman
77e15511be AVX2 and BMI instructions were published on http://software.intel.com/en-us/avx 2011-06-10 08:46:10 +00:00
Stanislav Shwartsman
04e9254e2c AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A 2011-05-30 20:15:50 +00:00
Stanislav Shwartsman
6ace540891 update for rev39 of Intel SDM 2011-05-28 20:20:25 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
734744847e fix cpuid.h (c) 2011-04-03 03:40:25 +00:00
Stanislav Shwartsman
16021a0ddb rename model_specific.h to be cpuid.h 2011-03-19 17:35:18 +00:00