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update for rev39 of Intel SDM

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This commit is contained in:
Stanislav Shwartsman 2011-05-28 20:20:25 +00:00
parent 75ec0f835e
commit 6ace540891
4 changed files with 35 additions and 5 deletions
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4
bochs/CHANGES
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@ -8,8 +8,8 @@ Bochs repository moved to the SVN version control !
- Added support for AVX instruction set emulation, to enable configure with
--enable-avx option.
When compiled in, AVX still could be disabled using .bochsrc CPUID option.
- Updated/Fixed instrumentation callbacks
- Bugfixes for CPU emulation correctness and stability
- Updated/Fixed instrumentation callbacks.
- Bugfixes for CPU emulation correctness and stability.
- Configure and compile
- Fixed Bochs manifest for Win64 compilation using Microsoft Visual Studio

10
bochs/cpu/cpuid.cc
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@ -165,10 +165,14 @@ Bit32u BX_CPU_C::get_ext3_cpuid_features(void)
{
Bit32u features = 0;
// [0:0] FS/GS BASE access instructions
// [31:1] Reserved
// [0:0] FS/GS BASE access instructions
// [6:1] Reserved
// [7:7] SMEP: Supervisor Mode Execution Protection
// [8:8] Reserved
// [9:9] Support for Enhanced REP MOVSB/STOSB
// [31:10] Reserved
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_FSGSBASE))
features |= 1;
features |= BX_CPUID_EXT3_FSGSBASE;
return features;
}

23
bochs/cpu/cpuid.h
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@ -169,6 +169,29 @@ struct cpuid_function_t {
#define BX_CPUID_EXT_RDRAND (1 << 30)
#define BX_CPUID_EXT_RESERVED31 (1 << 31)
// CPUID defines - EXT3 features CPUID[0x00000007].EBX
// -----------------------------
// [0:0] FS/GS BASE access instructions
// [6:1] reserved
// [7:7] SMEP: Supervisor Mode Execution Protection
// [8:8] reserved
// [9:9] Support for Enhanced REP MOVSB/STOSB
// [31:10] reserved
#define BX_CPUID_EXT3_FSGSBASE (1 << 0)
#define BX_CPUID_EXT3_RESERVED1 (1 << 1)
#define BX_CPUID_EXT3_RESERVED2 (1 << 2)
#define BX_CPUID_EXT3_RESERVED3 (1 << 3)
#define BX_CPUID_EXT3_RESERVED4 (1 << 4)
#define BX_CPUID_EXT3_RESERVED5 (1 << 5)
#define BX_CPUID_EXT3_RESERVED6 (1 << 6)
#define BX_CPUID_EXT3_SMEP (1 << 7)
#define BX_CPUID_EXT3_RESERVED8 (1 << 8)
#define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS (1 << 9)
// ...
// CPUID defines - STD2 features CPUID[0x80000001].EDX
// -----------------------------

3
bochs/cpu/crregs.h
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@ -92,6 +92,7 @@ struct bx_cr0_t {
#define BX_CR4_FSGSBASE_MASK (1 << 16)
#define BX_CR4_PCIDE_MASK (1 << 17)
#define BX_CR4_OSXSAVE_MASK (1 << 18)
#define BX_CR4_SMEP_MASK (1 << 20)
struct bx_cr4_t {
Bit32u val32; // 32bit value of register
@ -110,11 +111,13 @@ struct bx_cr4_t {
#if BX_SUPPORT_VMX
IMPLEMENT_CRREG_ACCESSORS(VMXE, 13);
#endif
IMPLEMENT_CRREG_ACCESSORS(SMXE, 14);
#if BX_SUPPORT_X86_64
IMPLEMENT_CRREG_ACCESSORS(FSGSBASE, 16);
IMPLEMENT_CRREG_ACCESSORS(PCIDE, 17);
#endif
IMPLEMENT_CRREG_ACCESSORS(OSXSAVE, 18);
IMPLEMENT_CRREG_ACCESSORS(SMEP, 20);
BX_CPP_INLINE Bit32u get32() const { return val32; }
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }