it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop. Hopefully this covers the NEC 41[x]1. Could
not find info for those processors.
and large page support. This version is a bit more intelligent about
how it deals with kernel text pages.
Now that this is fixed, don't map the kernel text read-write if
DDB is configured.
Currently, the major onboard devices are supported (disk, network,
rs232 and VMEbus). However, work is still need to support the remaining
devices (eg. IndustryPack sites).
These boards are available with a dazzling array of build options. At
this time, the following options are *required*:
o Real floating point hardware (the 68LC040 model isn't tested),
o The VMEchip2 must be present,
o If offboard VMEbus RAM is not present, at least 8MB of onboard
RAM is required.
o Even if offboard VMEbus RAM *is* present, at least 4MB of onboard
RAM is required. (Boards with 1 or 2MB onboard RAM *can* be
supported with offboard RAM, but not without some funky values in
the VMEbus Master mapping registers.)
There is no support for boards other than those in the -LX 200/300 series.
Give rest of clock interrupt code a revamp. Because we are using an external
cycle counter we can now handle loosing several hundred interrupts without
the time slipping.
- Return FALSE if the PTE does not have PG_V set (previously, you would
get always get true of the PDE was valid, even if the PTE was not).
- Teach it about 4MB pages.
* For MIPS RISC/os based diskl labels create partition 8 which is used
by sash (and where bootstrap code hides).
* If existing MIPS RISC/os label is present update disk parameter information
issueing a 'DIOCGPART' at every read. Avoid re-reading the label at
every format-verify (or read/write on the block-device) by fetching the label
at open-time and caching it until we close.
- dialog style main window
- support to read compressed kernel image
- automatic boot with timer
- human readable configrarion file
version no gets '1.15.00 2000.08.29'
If the machine uses a Z85230 ESCC device with deep buffers, we observe
output glitches when printing the zstty{0,1} probe lines when the device
is reset & reprogrammed during startup.
There is no easy 'hook' in the MI Z8530 driver, so we wait for output
buffer to drain before changing the baud rate generator prescaler value.
consistant with other ports.
Prevent uninitialized time from being written back to the RTC (1-Jan-1970)
if the machine is halted from the root device name prompt
(bootflags & RB_ASKNAME)
If the DMA chaning interrupt couldn't be serviced immediately (higher spl
level when kernel doing something else) a few microseconds later the NCR
controller will fill its FIFO and also interrupt the CPU.
The SCSI interrupt sees the terminal count has been reached, calls
asc_dma_intr to finish the job off. The FIFO cannot be flushed because
the block count hasn't been setup for the last dma segment (DMA chaining
still wasn't serviced).
Since the NCR 53c94 FIFO is only 16 bytes in size, any short DMA in this
size combined with the machine 'doing something else' causes the problem
to occur.
Servicing the DMA chaining interrupt before the NCR SCSI interrupt solves
this problem.
Add tests to ensure the DMA FIFO has been flushed correctly at the end of
each DMA operation just to be on the safe side.
never got the wired bit set. This caused panics if a swapped out process
was swapped in again and the kernel stack had not yet been unmapped.
While here, add a forgotten lock initializer.
locked, cpu_exit needs to do that too. Since in the lock debug case we
have to use a CALLS which wipes out R0-R6, change the convention for Swtch
so that the proc is passed in R6 and that R6 is clobbered. This is so
Swtch itself doesn't have to save/restore the proc pointer explicitly.
the stack, and remove the no-longer-necessary PHOLD()/PRELE() calls
in fdformat().
(This eliminates 1/3 of the instances of PHOLD()/PRELE() in the kernel code.)
XXX We still have too many mostly-redundant floppy drivers.
All compatable values are copied from the MIPS volume header to the
BSD disklabel structures.
* Add support for writing Mips volume header.
* Remove support for writing NetBSD label directly (this was broken)
These changes allow the kernel to read either a BSD disklabel created under
NetBSD/sparc or a MIPS volume header created under RISC/os.
There is a small amount of losage with the conversion between the 2
types of disk labels (mainly to do with file system types).
A table is used to map partition numbers and types between the two
types, and unless someone does something real fancy (or crazy) it should
work in both senario's
This change will allow the stand alone shell to directly load a NetBSD
kernel and mount a file system, avoiding the need for a seperate disk or
bootp server to bootstrapping NetBSD.
NetBSD/mipsco is now self sufficiant. We are not far from having a
miniroot filesystem and removing the need to have another NetBSD
machine to create the base filesystems.
Minor Trap for young players:
The root partition must be created with 'newfs -O' in order for the
stand alone shell to boot the kernel
TODO:
Add support for writing NetBSD disk labels back in - it will be useful
for non boot disks. I'm just not sure how to control the 2 behavours
treated as just another available VMEbus slave image as far as
bus_dma(9) is concerned.
To preserve faster onboard memory, mvmebus_dmamem_alloc() will
allocate first from the offboard VMEbus RAM slave image if present,
and assuming its address modifier matches the caller's constraints.
This can be overidden by specifying the BUS_DMA_ONBOARD_RAM flag.
deal with dynamic address modifier generation based on the CPU's
function code pins.
Also implement VMEbus slave mode for mvme147. (Not yet 100% working.)
in the non-MULTIPROCESSOR case (LOCKDEBUG requires it). Scheduler
lock is held upon entry to mi_switch() and cpu_switch(), and
cpu_switch() releases the lock before returning.
Largely from Bill Sommerfeld, with some minor bug fixes and
machine-dependent code hacking from me.
vme_dmamem*.
This is still a work in progress, but seems to DTRT on mvme167 so far.
TODO:
. Get VMEbus slave mode going on mvme147. This should be easy.
. Fix up the A16 slave mappings.
. Bounce buffer support. (Messy, but pretty much a `must have'.)
. Figure out how to deal with `location monitor' interrupts
within the framework. (Useful for Busnet, among other things.)
. It would be nice to make use of the VMEchip2's DMA facilities...
- Using the prom getenv function determine the correct console port
- Remove old prom function hooks
- Tidy up bootflags (remove upper case names, fixup RB_ASKNAME) as
recommended by Jaromír Doleèek
code ignore the new partition types, and look for the new "USR" partition
flag.
From SUNAGAWA Keiki <kei_sun@ba2.so-net.ne.jp> with slight changes by me.
Closes PR port-macppc/10046
as used on later arm26 system (A5000, A4, A3010, A3020, A4000).
What we have got:
...
upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00
fdc at upc0 offset 0x3f4 not configured
wdc0 at upc0 offset 0x1f0
lpt0 at upc0 offset 0x278
com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo
...
What we haven't got:
- FDC support (found, but not configured).
- Clearing lpt interrupts on arm26 systems (needs help from IOEB).
- A upc(4) manual page.
- More than minimal testing (my A3020s don't have root devices).
- A proper probe routine (arm26 can't use one anyway).
need to access this when we have the proclist locked for reading,
and thus cannot store it in the PCB (which may be swapped out).
As part of this, call pmap_activate() from cpu_switch() to switch
to the new address space, and refresh the PCB's copy of the LDT
selector from the pmap structure (see above paragraph). We need
to do this for MP support anyhow.
Fixes a "panic: spinlock_switchcheck: CPU 0 has 1 spin locks" via
gdt_compact() reported by Nathan Williams.
so that special setup functions needed for some CPUs will be run before
some things (like UVM) are inited.
Add vm_page_zero_enable = FALSE to the cyrix 6x86 case, as page zeroing
while idle causes problems.
I-sync in pmap_remove_mapping() if the old mapping had PG_EXEC, and
kick curcpu (IMB) or other CPUs (via an IPI) only if the pmap was
the kernel pmap or active on other CPUs (curcpu is handled in userret()).
- Use lazy I-sync everywhere, (hopefully) eliminating the last of the
I-sync issues for multiprocessor support.
- Eliminate some memory barriers added in a couple of previous revisions,
after some discussion on port-alpha/tech-smp.
Still some lazy I-sync optimization possibilites:
- pmap_changebit() does not need to I-sync when only write-protecting
a page.
- pmap_asn_alloc() may be able to cancel a pending lazy I-sync when a
new ASN is allocated. Need to double check against Green Book or
Brown Book.
handler to hook up device interrupts and softc callbacks.
Suggested by: Jason Thorpe and Toru Nishimura
* Fixup the indenting in a few places to conform to NetBSD style
the DMA FIFO on non block aligned writes. Not doing this causes large
writes (>4k) that are not aligned to incorrectly write 64bytes
of data every 4k interval. This only occurs on raw devices - typically
newfs fails to create a clean filesystem.
- pmap_zero_page() and pmap_copy_page(): if MULTIPROCESSOR, issue
a memory barrier after we zero/copy the page, to ensure that
other CPUs see the correct data.
- XXX Should we use MB, or is WMB good enough?
Also, bzero -> memset, bcopy -> memcpy.
- Make sure to do an MB after a PTE is set to a new value, so that
other processors see it.
- Use lazy I-sync in two pmap_page_protect() and in pmap_changebit(),
so that it is MP-safe. XXX Two more places where IMB is used in
the raw, but they're not in the common path.
There'll be some more lazy I-sync cleanups soon.
while suspended. When waking up the power hooks are again called at
splhigh() and then the level is lowered.
This prevents interrupts from reaching a device before the power hook
has reinitialized it.
driver and make it MI):
Set the ByteSwap bit on big-endian hosts, so we can use 16-bit transfers to get
at packets whatever.
Treat Tx/Rx headers as arrays of four bytes rather than as 32-bit words.
Transmit and receive buffer sizes aren't an intrinsic property of the card,
so they belong in if_ea.c rather than if_eareg.h.
Correct some comments in if_ea.c
Under this option, if only one IRQ is available for the link,
we assumes that the IRQ is already connected, and configure
PCI Interrupt Configuration Register accordingly.
This is what Linux pcmcia-cs-3.1.19 does by default.
This fixes unconfigured pccbb interrupt problem of
Sharp Mebius MN-5500. It's interrupt router is ITExpress Inc. IT8330G.
(http://www.ite.com.tw/, vendor=0x1283, product=0x8330)
Problem reporeted by Kitagawa <sk@kiu.ac.jp> in
http://www.kaynet.or.jp/~kay/ml/netbsd-pcmcia/msg/msg00608.html
one to perform a kernel traceback of any (non-swapped-out) process in
the system. For example, to show the traceback for PID 178:
db> t/t 0t178
trace: pid 178 at 0xabcd68
_mi_switch(0x109f60) + 164
...
db>
- MB_LEN_MAX is increased to 32.
- To ensure binary compatibility for old executables
under multibyte locale, versioned setlocale is added.
- __mb_len_cur definision is added in setlocale.c
and enable it in stdlib.h .
It is also important for multibyte locale stuffs,
but I just forgot.
This may happen on machines missing parts of the instruction set (like
some floating point formats).
Only one new instruction added; POLYD, so that the libm assembly files can
be used on architectures missing that instruction.
Also; include emulation code if compile-time option INSN_EMULATE is defined
instead of trying to match on which cputype it is.
N.B. POLYD isn't fully implemented, just enough to make libm happy.
Debugger(). Use db_printf() instead.
This fixes a problem whereby it was impossible to enter the debugger
if the CPU was spinning in lockmgr() for the proclist lock, because
printf() calls logwakeup(), which eventually calls proclist_lock_read(),
which then spins in lockmgr() yet again...
[Note: This change was prematurely committed to the 1.5 branch by
mistake. Since it would've been pulled up anyway, I won't
be sending a pullup request.]
Avoid interpreting the upper 32 bits of 64-bit BARs as a 32-bit BAR.
Otherwise, the code would assume that the value 0 was incorrect and either:
(a) [on bus 0] "fix up" the address to some nonzero value, thus placing
the decoded address range outside of 32-bit address space, or
(b) [elsewhere] completely disable the device.
The fact that this behaviour depends on the bus number of the device is
already XXX'd.
XXX: This will need revisiting if and when we ever want to handle a PCI bus
XXX: with more than 32 bits of address space on an i386.
The onboard Adaptec 7890 on my Dell Precision Workstation 410 works again.
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss. Since this is now done in both
ICache flush routines, no need to do it in pmap.c. Fixed R4400
stability problems with setregs() cache flushing.
