Add fpu emulation instrumentation and fixup FCMP and FCMPE emulation for v9.
And rename the 128-bit `x' routines to `q' to match v9 terminology: i - 32-bit int x - 64-bit int s - 32-bit fp d - 64-bit fp q - 128-bit fp
This commit is contained in:
parent
5e868d1e49
commit
dd5c54d05c
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fpu.c,v 1.7 2000/06/18 06:54:17 mrg Exp $ */
|
||||
/* $NetBSD: fpu.c,v 1.8 2000/08/03 18:32:07 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
@ -57,6 +57,27 @@
|
|||
#include <sparc/fpu/fpu_emu.h>
|
||||
#include <sparc/fpu/fpu_extern.h>
|
||||
|
||||
int fpe_debug = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
/*
|
||||
* Dump a `fpn' structure.
|
||||
*/
|
||||
void
|
||||
fpu_dumpfpn(struct fpn *fp)
|
||||
{
|
||||
static char *class[] = {
|
||||
"SNAN", "QNAN", "ZERO", "NUM", "INF"
|
||||
};
|
||||
|
||||
printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2],
|
||||
fp->fp_sign ? '-' : ' ',
|
||||
fp->fp_mant[0], fp->fp_mant[1],
|
||||
fp->fp_mant[2], fp->fp_mant[3],
|
||||
fp->fp_exp);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* fpu_execute returns the following error numbers (0 = no error):
|
||||
*/
|
||||
|
@ -292,39 +313,46 @@ fpu_execute(fe, instr)
|
|||
if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) {
|
||||
switch (opf >>= 2) {
|
||||
case FMVFC0 >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n"));
|
||||
cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK;
|
||||
if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FMVFC1 >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n"));
|
||||
cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK;
|
||||
if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FMVFC2 >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n"));
|
||||
cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK;
|
||||
if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FMVFC3 >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n"));
|
||||
cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK;
|
||||
if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FMVIC >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n"));
|
||||
cond = (curproc->p_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC;
|
||||
if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FMVXC >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n"));
|
||||
cond = (curproc->p_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC;
|
||||
if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FMVRZ >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n"));
|
||||
rs1 = instr.i_fmovr.i_rs1;
|
||||
if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] != 0)
|
||||
return (0); /* success */
|
||||
|
@ -332,6 +360,7 @@ fpu_execute(fe, instr)
|
|||
goto mov;
|
||||
case FMVRLEZ >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n"));
|
||||
rs1 = instr.i_fmovr.i_rs1;
|
||||
if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] > 0)
|
||||
return (0); /* success */
|
||||
|
@ -339,6 +368,7 @@ fpu_execute(fe, instr)
|
|||
goto mov;
|
||||
case FMVRLZ >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n"));
|
||||
rs1 = instr.i_fmovr.i_rs1;
|
||||
if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] >= 0)
|
||||
return (0); /* success */
|
||||
|
@ -346,6 +376,7 @@ fpu_execute(fe, instr)
|
|||
goto mov;
|
||||
case FMVRNZ >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n"));
|
||||
rs1 = instr.i_fmovr.i_rs1;
|
||||
if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] == 0)
|
||||
return (0); /* success */
|
||||
|
@ -353,6 +384,7 @@ fpu_execute(fe, instr)
|
|||
goto mov;
|
||||
case FMVRGZ >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n"));
|
||||
rs1 = instr.i_fmovr.i_rs1;
|
||||
if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] <= 0)
|
||||
return (0); /* success */
|
||||
|
@ -360,39 +392,16 @@ fpu_execute(fe, instr)
|
|||
goto mov;
|
||||
case FMVRGEZ >> 2:
|
||||
/* Presume we're curproc */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n"));
|
||||
rs1 = instr.i_fmovr.i_rs1;
|
||||
if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] < 0)
|
||||
return (0); /* success */
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
case FCMP >> 2:
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fpu_compare(fe, 0);
|
||||
goto cmpdone;
|
||||
|
||||
case FCMPE >> 2:
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fpu_compare(fe, 1);
|
||||
cmpdone:
|
||||
/*
|
||||
* The only possible exception here is NV; catch it
|
||||
* early and get out, as there is no result register.
|
||||
*/
|
||||
cx = fe->fe_cx;
|
||||
fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT);
|
||||
if (cx != 0) {
|
||||
if (fsr & (FSR_NV << FSR_TEM_SHIFT)) {
|
||||
fs->fs_fsr = (fsr & ~FSR_FTT) |
|
||||
(FSR_TT_IEEE << FSR_FTT_SHIFT);
|
||||
return (FPE);
|
||||
}
|
||||
fsr |= FSR_NV << FSR_AX_SHIFT;
|
||||
}
|
||||
fs->fs_fsr = fsr;
|
||||
return (0);
|
||||
goto mov;
|
||||
default:
|
||||
DPRINTF(FPE_INSN,
|
||||
("fpu_execute: unknown v9 FP inst %x opf %x\n",
|
||||
instr.i_int, opf));
|
||||
return (NOTFPU);
|
||||
}
|
||||
}
|
||||
|
@ -400,17 +409,23 @@ fpu_execute(fe, instr)
|
|||
switch (opf >>= 2) {
|
||||
|
||||
default:
|
||||
DPRINTF(FPE_INSN,
|
||||
("fpu_execute: unknown basic FP inst %x opf %x\n",
|
||||
instr.i_int, opf));
|
||||
return (NOTFPU);
|
||||
|
||||
case FMOV >> 2: /* these should all be pretty obvious */
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n"));
|
||||
rs1 = fs->fs_regs[rs2];
|
||||
goto mov;
|
||||
|
||||
case FNEG >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n"));
|
||||
rs1 = fs->fs_regs[rs2] ^ (1 << 31);
|
||||
goto mov;
|
||||
|
||||
case FABS >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
|
||||
rs1 = fs->fs_regs[rs2] & ~(1 << 31);
|
||||
mov:
|
||||
#ifndef SUN4U
|
||||
|
@ -425,42 +440,48 @@ fpu_execute(fe, instr)
|
|||
return (0); /* success */
|
||||
|
||||
case FSQRT >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs2);
|
||||
fp = fpu_sqrt(fe);
|
||||
break;
|
||||
|
||||
case FADD >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fp = fpu_add(fe);
|
||||
break;
|
||||
|
||||
case FSUB >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fp = fpu_sub(fe);
|
||||
break;
|
||||
|
||||
case FMUL >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fp = fpu_mul(fe);
|
||||
break;
|
||||
|
||||
case FDIV >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fp = fpu_div(fe);
|
||||
break;
|
||||
|
||||
#ifndef SUN4U
|
||||
case FCMP >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fpu_compare(fe, 0);
|
||||
goto cmpdone;
|
||||
|
||||
case FCMPE >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n"));
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
fpu_explode(fe, &fe->fe_f2, type, rs2);
|
||||
fpu_compare(fe, 1);
|
||||
|
@ -482,9 +503,9 @@ fpu_execute(fe, instr)
|
|||
fs->fs_fsr = fsr;
|
||||
return (0);
|
||||
|
||||
#endif /* not SUN4U */
|
||||
case FSMULD >> 2:
|
||||
case FDMULX >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n"));
|
||||
if (type == FTYPE_EXT)
|
||||
return (NOTFPU);
|
||||
fpu_explode(fe, &fe->fe_f1, type, rs1);
|
||||
|
@ -497,14 +518,17 @@ fpu_execute(fe, instr)
|
|||
case FXTOS >> 2:
|
||||
case FXTOD >> 2:
|
||||
case FXTOQ >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n"));
|
||||
type = FTYPE_LNG;
|
||||
fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
|
||||
type = opf & 3; /* sneaky; depends on instruction encoding */
|
||||
break;
|
||||
|
||||
case FTOX >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n"));
|
||||
fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
|
||||
type = FTYPE_LNG;
|
||||
break;
|
||||
#endif /* SUN4U */
|
||||
|
||||
case FTOS >> 2:
|
||||
|
@ -515,6 +539,7 @@ fpu_execute(fe, instr)
|
|||
case FTOQ >> 2:
|
||||
#endif /* SUN4U */
|
||||
case FTOI >> 2:
|
||||
DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n"));
|
||||
fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
|
||||
type = opf & 3; /* sneaky; depends on instruction encoding */
|
||||
break;
|
||||
|
@ -542,11 +567,7 @@ fpu_execute(fe, instr)
|
|||
}
|
||||
fs->fs_fsr = fsr;
|
||||
fs->fs_regs[rd] = space[0];
|
||||
#ifndef SUN4U
|
||||
if (type >= FTYPE_DBL) {
|
||||
#else /* SUN4U */
|
||||
if (type >= FTYPE_DBL || type == FTYPE_LNG) {
|
||||
#endif /* SUN4U */
|
||||
fs->fs_regs[rd + 1] = space[1];
|
||||
if (type > FTYPE_DBL) {
|
||||
fs->fs_regs[rd + 2] = space[2];
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fpu_emu.h,v 1.3 2000/06/18 06:54:17 mrg Exp $ */
|
||||
/* $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
@ -179,16 +179,17 @@ struct fpn *fpu_newnan(struct fpemu *);
|
|||
*/
|
||||
int fpu_shr(struct fpn *, int);
|
||||
|
||||
/* Conversion to and from internal format -- note asymmetry. */
|
||||
int fpu_itofpn(struct fpn *, u_int);
|
||||
int fpu_stofpn(struct fpn *, u_int);
|
||||
int fpu_dtofpn(struct fpn *, u_int, u_int);
|
||||
int fpu_xtofpn(struct fpn *, u_int, u_int, u_int, u_int);
|
||||
|
||||
u_int fpu_fpntoi(struct fpemu *, struct fpn *);
|
||||
u_int fpu_fpntos(struct fpemu *, struct fpn *);
|
||||
u_int fpu_fpntod(struct fpemu *, struct fpn *);
|
||||
u_int fpu_fpntox(struct fpemu *, struct fpn *);
|
||||
|
||||
void fpu_explode(struct fpemu *, struct fpn *, int, int);
|
||||
void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
|
||||
|
||||
#ifdef DEBUG
|
||||
#define FPE_INSN 0x1
|
||||
#define FPE_REG 0x2
|
||||
extern int fpe_debug;
|
||||
void fpu_dumpfpn(struct fpn *);
|
||||
#define DPRINTF(x, y) if (fpe_debug & (x)) printf y
|
||||
#define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f))
|
||||
#else
|
||||
#define DPRINTF(x, y)
|
||||
#define DUMPFPN(x, f)
|
||||
#endif
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fpu_explode.c,v 1.4 2000/06/18 06:54:17 mrg Exp $ */
|
||||
/* $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
@ -110,7 +110,7 @@ fpu_itof(fp, i)
|
|||
* 64-bit int -> fpn.
|
||||
*/
|
||||
int
|
||||
fpu_xitof(fp, i)
|
||||
fpu_xtof(fp, i)
|
||||
register struct fpn *fp;
|
||||
register u_int64_t i;
|
||||
{
|
||||
|
@ -132,7 +132,7 @@ fpu_xitof(fp, i)
|
|||
}
|
||||
#endif /* SUN4U */
|
||||
|
||||
#define mask(nbits) ((1 << (nbits)) - 1)
|
||||
#define mask(nbits) ((1L << (nbits)) - 1)
|
||||
|
||||
/*
|
||||
* All external floating formats convert to internal in the same manner,
|
||||
|
@ -213,7 +213,7 @@ fpu_dtof(fp, i, j)
|
|||
* 128-bit extended -> fpn.
|
||||
*/
|
||||
int
|
||||
fpu_xtof(fp, i, j, k, l)
|
||||
fpu_qtof(fp, i, j, k, l)
|
||||
register struct fpn *fp;
|
||||
register u_int i, j, k, l;
|
||||
{
|
||||
|
@ -260,7 +260,7 @@ fpu_explode(fe, fp, type, reg)
|
|||
switch (type) {
|
||||
#ifdef SUN4U
|
||||
case FTYPE_LNG:
|
||||
s = fpu_xitof(fp, l);
|
||||
s = fpu_xtof(fp, l);
|
||||
break;
|
||||
#endif /* SUN4U */
|
||||
|
||||
|
@ -277,12 +277,13 @@ fpu_explode(fe, fp, type, reg)
|
|||
break;
|
||||
|
||||
case FTYPE_EXT:
|
||||
s = fpu_xtof(fp, s, space[1], space[2], space[3]);
|
||||
s = fpu_qtof(fp, s, space[1], space[2], space[3]);
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("fpu_explode");
|
||||
}
|
||||
|
||||
if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
|
||||
/*
|
||||
* Input is a signalling NaN. All operations that return
|
||||
|
@ -296,4 +297,12 @@ fpu_explode(fe, fp, type, reg)
|
|||
s = FPC_SNAN;
|
||||
}
|
||||
fp->fp_class = s;
|
||||
DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
|
||||
((type == FTYPE_INT) ? 'i' :
|
||||
((type == FTYPE_SNG) ? 's' :
|
||||
((type == FTYPE_DBL) ? 'd' :
|
||||
((type == FTYPE_EXT) ? 'q' : '?')))),
|
||||
reg));
|
||||
DUMPFPN(FPE_REG, fp);
|
||||
DPRINTF(FPE_REG, ("\n"));
|
||||
}
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fpu_extern.h,v 1.3 2000/06/18 06:54:17 mrg Exp $ */
|
||||
/* $NetBSD: fpu_extern.h,v 1.4 2000/08/03 18:32:08 eeh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1995 The NetBSD Foundation, Inc.
|
||||
|
@ -70,21 +70,21 @@ struct fpn *fpu_div __P((struct fpemu *));
|
|||
/* fpu_explode.c */
|
||||
int fpu_itof __P((struct fpn *, u_int));
|
||||
#ifdef SUN4U
|
||||
int fpu_xitof __P((struct fpn *, u_int64_t));
|
||||
int fpu_xtof __P((struct fpn *, u_int64_t));
|
||||
#endif /* SUN4U */
|
||||
int fpu_stof __P((struct fpn *, u_int));
|
||||
int fpu_dtof __P((struct fpn *, u_int, u_int ));
|
||||
int fpu_xtof __P((struct fpn *, u_int, u_int , u_int , u_int ));
|
||||
int fpu_qtof __P((struct fpn *, u_int, u_int , u_int , u_int ));
|
||||
void fpu_explode __P((struct fpemu *, struct fpn *, int, int ));
|
||||
|
||||
/* fpu_implode.c */
|
||||
u_int fpu_ftoi __P((struct fpemu *, struct fpn *));
|
||||
#ifdef SUN4U
|
||||
u_int fpu_ftoxi __P((struct fpemu *, struct fpn *, u_int *));
|
||||
u_int fpu_ftox __P((struct fpemu *, struct fpn *, u_int *));
|
||||
#endif /* SUN4U */
|
||||
u_int fpu_ftos __P((struct fpemu *, struct fpn *));
|
||||
u_int fpu_ftod __P((struct fpemu *, struct fpn *, u_int *));
|
||||
u_int fpu_ftox __P((struct fpemu *, struct fpn *, u_int *));
|
||||
u_int fpu_ftoq __P((struct fpemu *, struct fpn *, u_int *));
|
||||
void fpu_implode __P((struct fpemu *, struct fpn *, int, u_int *));
|
||||
|
||||
/* fpu_mul.c */
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fpu_implode.c,v 1.6 2000/07/24 04:13:45 mycroft Exp $ */
|
||||
/* $NetBSD: fpu_implode.c,v 1.7 2000/08/03 18:32:08 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
@ -241,7 +241,7 @@ fpu_ftoi(fe, fp)
|
|||
* of the SPARC instruction set).
|
||||
*/
|
||||
u_int
|
||||
fpu_ftoxi(fe, fp, res)
|
||||
fpu_ftox(fe, fp, res)
|
||||
struct fpemu *fe;
|
||||
register struct fpn *fp;
|
||||
u_int *res;
|
||||
|
@ -436,7 +436,7 @@ done:
|
|||
* so we can avoid a small bit of work.
|
||||
*/
|
||||
u_int
|
||||
fpu_ftox(fe, fp, res)
|
||||
fpu_ftoq(fe, fp, res)
|
||||
struct fpemu *fe;
|
||||
register struct fpn *fp;
|
||||
u_int *res;
|
||||
|
@ -507,7 +507,7 @@ fpu_implode(fe, fp, type, space)
|
|||
|
||||
#ifdef SUN4U
|
||||
case FTYPE_LNG:
|
||||
space[0] = fpu_ftoxi(fe, fp, space);
|
||||
space[0] = fpu_ftox(fe, fp, space);
|
||||
break;
|
||||
#endif /* SUN4U */
|
||||
|
||||
|
@ -525,7 +525,7 @@ fpu_implode(fe, fp, type, space)
|
|||
|
||||
case FTYPE_EXT:
|
||||
/* funky rounding precision options ?? */
|
||||
space[0] = fpu_ftox(fe, fp, space);
|
||||
space[0] = fpu_ftoq(fe, fp, space);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
Loading…
Reference in New Issue