msgbuf. Note that old 'dmesg' and 'syslogd' binaries will continue running,
though old 'dmesg' binaries will output a few bytes of junk at the start of
the buffer, and will miss a few bytes at the end of the buffer.
Compute CPU speed(MHz) and loop multiplier for DELAY() based on
counting empty loop between mcclock ticks. New global: cpu_mhz.
Change pmax/pmax/machdep.c to build baseboard model names from cpu_mhz.
Set 'cpuspeed' for more realistic DELAY() on mips3 models.
Mips CPU constants, testing, and calibration from D. Sean Davidson
<davidson@zk3.dec.com> and Simon Burge <simonb@telstra.com.au>.
* prototype and definition for pmap_activate(p). Updates the segtab,
and changes the active ASID if p == curproc.
* Make reserved fixed-address (UADDR) kernelstack PTEs global,
so we still have a kernel stack after pmap_activate() on curproc.
* make KSEG2 mappings for p_addr global (see above.)
Seems to detune contextswitch and NTP resolution (by 60 ms), but
thepmap_activate() interface is mandatory. Needs more thought.
of cache-index incompatible virtual mappings for a physical page may be
required for hardware without secondary (level 2) cache to detect and
correct virtual coherency problems. I'm not sure this is really needed
anymore, since pmap_prefer() took care of of the cache-index
incompatible mappings that I have seen. Count the times a page is
cache inhibited in enter_stats if DEBUG.
Wait for memory instead of panic() on failure to allocate a page for the
segtab or segmap [from OpenBSD arc port]. Also check for malloc()
failure on allocation of a new pv entry and panic().
Increment resident_count when adding a new page to a pmap [also from
OpenBSD]. Process resident size is now valid.
cache flush operations required on a virtually-indexed, physically-tagged
mips3 with no L2 cache to provide cache-coherence exceptions.
(Similar to what's needed with a virtually-indexed, virtually-tagged cache.)
faults. Use curpcb, which always points to the current pcb. If curproc
was NULL when the kernel faulted, the trap handling would fault recursively
and the kernel stack would overflow.
Has unrolled loop for aligned-to-aligned copy.
Notes:
1. this code tuned for DEC 5000/200. ioasic decstations do more unaligned
copies. Better than old non-unrolled loop, but could be improved.
2. Undoes changes made for MIPS3 with comment implying an r4000 TLB bug.
We can't reproduce this on 5000/150 (jonathan) or 5000/50 (mhitch).
Calls to previous bcopy with a bad address show similar symptoms,
reporting a trap in bcopy() after bcopy() has returned. Same thing??
Needs re-checking on an r4000 with no L2 cache.
sigcode():
executed from user-space stack.
mips1_cpu_switch_resume, mips3_cpu_switch_resume:
arguments passed in via v0, t0, t1 (outlined from cpu_switch())
mips3_VCED(), mips3_VCEI():
called from exception-vector code without any register save,
$at, $ra are live.
undone by rev 1.7:
>redo pmax/include/reg.h
>so that the definitions needed by locore.S are in a separate file,
>pmax/include/regnum.h.
* Add explicit `#include <mips/regnum.h>' where symbolic offsets
into a mips trapframe or struct reg are used..
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
ktlbmiss on the kernel stack. It was showing the temporary SP, not the
original SP.
Add a display of the first few wired entries of the TLB so when the ktblmiss
occurs, the TLB entries mapping the kernel stack can be verified.
mhitch