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3299 Commits

Author SHA1 Message Date
mrg c79ff46cb6 don't try to setup MXCC registers on non-primary CPU's on systems without 
SMP support.
 2003-01-02 09:42:09 +00:00
pk 9dd42c6155 SMP: lock kernel for soft interrupts < IPL_SCHED as well. 2003-01-01 16:17:10 +00:00
pk 3607bd7dca pmap_alloc_cpu: use flags from boot cpu for now, as the passed cpu_info 
structure has not been fully setup yet.
 2003-01-01 15:56:11 +00:00
pk 16305a65cb prom mailbox map: look for the property `mailbox-virtual' first. 2003-01-01 15:51:00 +00:00
mrg 2fff4ee989 fix a comment. 2003-01-01 08:24:48 +00:00
mrg d06249b555 KNF. 2003-01-01 06:33:29 +00:00
thorpej 9c1214153c Use aprint_normal() for cfprint routines. 2003-01-01 02:20:47 +00:00
pk 2aac3c7c89 Slight optimisation in proc_trampoline(). 2002-12-31 17:07:36 +00:00
pk 1df04e663f Make the schedintr() code common for all timers. 2002-12-31 16:45:52 +00:00
pk 7b7269ba42 New version of cpu_switch/switchexit, mostly to simplify SMP support. It's 
currently conditional on ALT_SWITCH_CODE (defaults to `on' if MULTIPROCESSOR
is defined) until more testing rounds are completed.
 2002-12-31 16:17:12 +00:00
pk 3d8def4865 Use a soft interrupt scheme to schedule schedclock(), so we can make 
splsched() less than splhigh().
 2002-12-31 15:57:26 +00:00
pk 67e16e38a4 Define IPL_SCHED at level 11 and make splsched() use it. 2002-12-31 15:51:18 +00:00
pk d358537b64 Pass the CPU context to all TLB flush routines. Because of this (and the 
fact that cache flushes are also passed the context number), most
"long-term" context switches can be eliminated from the SRMMU versions
of the pmap functions.
 2002-12-31 15:23:29 +00:00
pk 83dae8a821 * map the PROM CPU mailbox if available. 
* map MXCC error/status registers if available.
* add MXCC-specific module error interrupt handler.
* use high priority interrupt level in mp_pause_cpus()
 2002-12-31 15:10:28 +00:00
pk 2b59d26892 Add offset for `cpuinfo.ci_tt'. 2002-12-31 15:05:48 +00:00
pk c3bb05ff5b * Add level argument to raise_ipi() 
* Add diagnostic field members to cpu_info.
 2002-12-31 15:04:49 +00:00
pk 5c671fd10d nmi_sun4m: run handler at splhigh() 2002-12-31 14:34:54 +00:00
pk 43b86d0b59 rwindow debug code: display the current cpu number. 2002-12-31 13:17:23 +00:00
pk a1e9e5cae8 Add some more definitions: SRMMU and MXCC reset register. 2002-12-31 12:01:27 +00:00
mrg 122353da40 rename CPU_READY() to CPU_NOTREADY() seeing that's what it checks. 2002-12-28 02:35:56 +00:00
mrg 7d51aacb32 update the vme bus_space_tag_t to reality. 2002-12-28 01:33:00 +00:00
martin ffbcb6d927 Conditionalize T_DBPAUSE trap handling on #ifdef MULTIPROCESSOR to make 
single CPU kernels compile again.
 2002-12-26 12:14:31 +00:00
pk f8055a350c * Use correct PC value for displaying the called function. 
* Merge code to display non-kernel frames.
 2002-12-23 13:21:10 +00:00
pk f953a01835 xcallintr() receive a `clockframe *' argument, not a `trapframe *'. 
Setup a DDB context for paused CPUs by defining a soft trap (T_DBPAUSE)
which uses the generic trap handler code to get the trapframe constructed
and then calls on a debugger-defined `suspend' routine.
 2002-12-23 00:55:16 +00:00
pk 5c62f82bdf Upon trap exit, update the trapframe with data for the running CPU rather 
than the one which was the last target of the `machine cpu' command.
 2002-12-23 00:42:37 +00:00
mrg 6ee482ef5b change what 'hw.model' reports to be more inline with other netbsd ports, as 
well as reporting the actual machine model & cpu, rather than first configured
CPU.  changes for two machines are:

old:
	hw.model = TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
	hw.model = SUNW,UltraSPARC @ 143.002 MHz, version 0 FPU

new:
	hw.model = SUNW,SPARCstation-20 (TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU)
	hw.model = SUNW,Ultra-1 (SUNW,UltraSPARC @ 143.002 MHz, version 0 FPU)

as per discussion on port-sparc & port-sparc64.
 2002-12-22 02:17:24 +00:00
manu 4a06119a9d Pass the system call table to trace_enter() and ktrsys() so that it is 
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.

If NULL is given, then the regular systam call table for the process is used.
 2002-12-21 16:23:56 +00:00
pk 4e0634669b * xcallintr(): use cpuinfo directly again. 
* nmi_soft(): remove most of the obsoleted requests.
 2002-12-21 12:55:54 +00:00
pk 0408b1cbc8 tlb_flush_segment() and tlb_flush_region() now take a virtual address 
argument instead of segment and region numbers.
 2002-12-21 12:52:55 +00:00
pk 82815de0ad Use xcall() to broadcast MMU TLB flushes. 2002-12-21 12:13:38 +00:00
pk 8dcde9f5b1 * cpu_hatch(): enable interrupts upon return from cpu_setup(). 
* interrupt trap: acquire the kernel lock only for interrupt levels <= PIL_SCHED
 2002-12-21 11:57:41 +00:00
pk 1d8dc4daf2 * getcacheinfo_obp(): also initialise the cacheinfo i/d associativity fields 
in the case of a unified cache.
* xcall(): slightly optimise the `wait for other CPUs' loop.
 2002-12-21 11:48:55 +00:00
pk f0a20f1305 * mark selected fields of `struct xpmsg' as volatile, instead of the whole 
structure.
* change volatile => __volatile
 2002-12-19 16:31:38 +00:00
pk 2fba4e01ff Mark CPUs that did not spin up properly and don't enable them later on. 2002-12-19 11:20:30 +00:00
pk 75c5f270d2 Brush-up the generic cross-call routine and use it to implement the SMP 
cache flush ops.
Also a standard soft interrupt handler for standard cross-call notification
reserving the NMI level 15 softint for urgent cross calls.
 2002-12-19 10:38:28 +00:00
pk eaf530d598 Sprinkle volatiles to avoid register allocation, esp. in cross-call 
synchronisation functions used in SMP kernels.
 2002-12-19 10:30:39 +00:00
pk ec2b1c3c64 smp_cache_flush() also takes a context parameter. 2002-12-19 10:27:19 +00:00
pk 2076dbdb04 Install the sparc V8 multiply/divide routines after we've collected some 
basic information on the CPUs.
 2002-12-18 11:56:43 +00:00
mrg 1a854929dd we use nmi_hard and nmi_soft on SUN4D as well 2002-12-18 06:20:36 +00:00
pk a26cbfba69 Deal with an `unimplemented flush' trap from kernel mode. 2002-12-17 10:04:19 +00:00
pk c2ddc52f2d The cache flush routines now take a CPU context parameter. This is going 
to be necessary in SMP kernels.
 2002-12-16 16:59:09 +00:00
pk b036b089a7 Multiple inclusion protection. 2002-12-16 16:24:40 +00:00
jdc 0a3a2262cb Increment version number for match function and Cycle 5 IP changes. 2002-12-16 13:02:58 +00:00
jdc 079b83cafa Extend the matching routine to take a function pointer, so that additional 
(arbitrary) matching can be done.
Add match function and patch for Cycle 5 IP (Sparc 5 clone).

Reviewed by Uwe.
 2002-12-16 13:01:01 +00:00
martin ae7d5baab6 Fix pasto - make it compile for !MULTIPROCESSOR 2002-12-15 23:01:09 +00:00
pk 9313f9570d Disable `unimplemented flush' traps during boot. Keep it disabled on 
non-MULTIPROCESSOR kernels.
 2002-12-15 15:01:08 +00:00
christos cc079cff49 release the kernel lock if trace_enter fails. 
XXX[1]: We need to fix all platforms that do this.
XXX[2]: x86 does not check for MPSAFE syscalls before grabbing the lock.
 2002-12-14 14:52:24 +00:00
pk f4fe3fda21 dumpsys(): Use pmap_kremove() to unmap pages mapped pmap_kenter(). 2002-12-12 09:34:04 +00:00
pk 047870f66e softintr_establish(): append handler to the list for the actually choosen 
processor interrupt level.
 2002-12-11 13:21:19 +00:00
pk e675712f0d * loadfile() return a file descriptor that must be closed. 
* check the kernel size before loading
 2002-12-11 10:35:06 +00:00