Makefile.inc is going to disappear because we don't want txlt, aout2bb and
elf2bb directories to include this stuff; it is only required by bootblocks.
cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
xscale_cache_purgeD_rng to work around a bug where a D$
"invalidate by address" doesn't properly clear the dirty
bits on the cache block (i80200 errata item #25).
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$
More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:
icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range
dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range
idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range
Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.
A7000 kernels are obsolete now the ARM7500 detection is integrated. The
NC's however are not completely supported and should in the near future be
bootable with GENERIC/INSTALL too.
* This is not currently used by the in-tree evbarm interrupt code. New
interrupt code will appear "soon" which makes use of this file.
* This file will probably move to a generic ARM location eventually.
use 2 adjacent cache-size areas for global cache clean, alternating
between the two of them on each call. Without this, D-cache blocks
aren't evicted properly, and no one seems to know why.
1) Add defparam XSCALE_CCLKCFG to define a parameter for the
CCLKCFG register. Default it to '9' on the IQ80310.
2) Add a sleep call to the xscale CPU function vector (replacing
the nullop) which should drop the CPU into "idle" mode when
cpu_switch finds nothing on the run queues.
by SWI numbers above 0x9f0000, but we re-map them down to somewhere just
after the end of the usual syscall range, since NetBSD doesn't handle
sparse syscall arrays well.
The only syscall I've actually implemented in this range is cacheflush(),
which was previously being mapped to fork(), causing ... interesting results.
BIOS-bug-avoidance [fixes part of my own port-i386/11299], and (2) lets you
have APM and COMPAT_MACHO in the kernel at the same time. Also comments on
the special 8th entry and what else changing some of these values affects.
OK'ed by Frank.
This is required when two or more bridges on the same bus, and some of
them are incompletely initialized by BIOS.
Reported by NAKAGAWA Yoshihisa <y-nakaga@nwsl.mesh.ad.jp>
While we're here, enable RAIDframe (and RAID_AUTOCONFIG) by default for
architectures that I'm comfortable can deal with it being on by default.
Also: bump the number of 'raid' devices from 4 to 8, since 4 seems to
be insufficient in practise.
jdolecek