More 32-bit cleanup.
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@ -1,4 +1,4 @@
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/* $NetBSD: in4_cksum.c,v 1.1 2001/08/10 20:53:11 eeh Exp $ */
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/* $NetBSD: in4_cksum.c,v 1.2 2002/01/21 18:50:36 eeh Exp $ */
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/*
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* Copyright (c) 2001 Eduardo Horvath.
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@ -80,19 +80,38 @@ in4_cksum(m, nxt, off, len)
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ipov.ih_dst = mtod(m, struct ip *)->ip_dst;
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w = (u_char *)&ipov;
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/* assumes sizeof(ipov) == 20 */
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#ifdef __arch64__
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__asm __volatile(" lduw [%5 + 0], %1; "
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" lduw [%5 + 4], %2; "
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" lduw [%5 + 8], %3; add %0, %1, %0; "
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" lduw [%5 + 12], %1; add %0, %2, %0; "
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" lduw [%5 + 16], %2; add %0, %3, %0; "
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" mov -1, %3; "
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" add %0, %1, %0; "
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" srl %3, 0, %3; "
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" add %0, %2, %0; "
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" mov -1, %3; add %0, %1, %0; "
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" srl %3, 0, %3; add %0, %2, %0; "
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" srlx %0, 32, %2; and %0, %3, %1; "
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" add %0, %2, %0; "
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: "=r" (sum), "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
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: "0" (sum), "r" (w));
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#else
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/*
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* Can't use upper 32-bits of the registers, so this needs to
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* be recoded. So instead of accumulating the carry in the
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* upper 32-bits of the registers, we use addxcc which cannot
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* be grouped with any other instructions.
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*/
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__asm __volatile(" lduw [%5 + 0], %1; "
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" lduw [%5 + 4], %2; "
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" lduw [%5 + 8], %3; addcc %0, %1, %0; "
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" lduw [%5 + 12], %1; "
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" addxcc %0, %2, %0; "
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" lduw [%5 + 16], %2; "
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" addxcc %0, %3, %0; "
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" addxcc %0, %1, %0; "
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" addxcc %0, %2, %0; "
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" addxcc %0, 0, %0; "
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: "=r" (sum), "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
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: "0" (sum), "r" (w));
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#endif
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}
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/* skip unnecessary part */
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@ -102,6 +121,5 @@ in4_cksum(m, nxt, off, len)
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off -= m->m_len;
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m = m->m_next;
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}
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return (in_cksum_internal(m, len, off, sum));
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: in_cksum.S,v 1.4 2002/01/16 18:49:22 eeh Exp $ */
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/* $NetBSD: in_cksum.S,v 1.5 2002/01/21 18:50:37 eeh Exp $ */
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/*
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* Copyright (c) 2001 Eduardo Horvath
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@ -54,11 +54,13 @@
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*/
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#define IALIGN .align 32
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IALIGN
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ENTRY(in_cksum)
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clr %o3 ! sum = 0;
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clr %o2
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_ENTRY(_C_LABEL(in_cksum_internal))
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srl %o3, 0, %o3 ! Make sure this is a 32-bit value going in
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brz %o0, Lfinish ! for (; m && len > 0; m->m_next) {
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clr %g1 ! swapped = 0;
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brlez %o1, Lfinish
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