Fix a few more bugs.
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eeh
parent
9872e4c410
commit
112afe4fa4
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu.c,v 1.13 2001/09/22 19:58:28 eeh Exp $ */
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/* $NetBSD: fpu.c,v 1.14 2002/01/19 03:02:34 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -136,6 +136,7 @@ fpu_cleanup(p, fs)
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break;
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case FSR_TT_IEEE:
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DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_IEEE\n"));
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/* XXX missing trap address! */
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if ((i = fsr & FSR_CX) == 0)
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panic("fpu ieee trap, but no exception");
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@ -143,6 +144,7 @@ fpu_cleanup(p, fs)
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break; /* XXX should return, but queue remains */
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case FSR_TT_UNFIN:
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DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNFIN\n"));
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#ifdef SUN4U
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if (fs->fs_qsize == 0) {
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printf("fpu_cleanup: unfinished fpop");
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@ -153,6 +155,7 @@ fpu_cleanup(p, fs)
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#endif /* SUN4U */
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case FSR_TT_UNIMP:
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DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNIMP\n"));
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if (fs->fs_qsize == 0)
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panic("fpu_cleanup: unimplemented fpop");
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break;
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@ -162,6 +165,7 @@ fpu_cleanup(p, fs)
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/* NOTREACHED */
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case FSR_TT_HWERR:
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DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_HWERR\n"));
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log(LOG_ERR, "fpu hardware error (%s[%d])\n",
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p->p_comm, p->p_pid);
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uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid);
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@ -287,6 +291,12 @@ fpu_execute(fe, instr)
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#endif /* SUN4U */
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u_int space[4];
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#if defined(DEBUG) && defined(DDB)
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if (fpe_debug & FPE_INSN) {
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disasem_instr(0, instr.i_int, 0);
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}
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#endif
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/*
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* `Decode' and execute instruction. Start with no exceptions.
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* The type of any i_opf opcode is in the bottom two bits, so we
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@ -545,19 +555,32 @@ fpu_execute(fe, instr)
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break;
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case FTOX >> 2:
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DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n"));
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DPRINTF(FPE_INSN, ("fpu_execute: FTOX\n"));
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = FTYPE_LNG;
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/* Recalculate destination register */
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rd = instr.i_opf.i_rd;
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break;
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#endif /* SUN4U */
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#endif /* SUN4U */
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case FTOI >> 2:
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DPRINTF(FPE_INSN, ("fpu_execute: FTOI\n"));
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = FTYPE_INT;
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/* Recalculate destination register */
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rd = instr.i_opf.i_rd;
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break;
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case FTOS >> 2:
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case FTOD >> 2:
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case FTOQ >> 2:
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DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n"));
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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/* Recalculate rd with correct type info. */
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type = opf & 3; /* sneaky; depends on instruction encoding */
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mask = 0x3 >> (3 - type);
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rd = instr.i_opf.i_rd;
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rd = (rd & ~mask) | ((rd & mask & 0x1) << 5);
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break;
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}
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@ -582,6 +605,12 @@ fpu_execute(fe, instr)
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fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT);
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}
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fs->fs_fsr = fsr;
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DPRINTF(FPE_REG, ("-> %c%d\n", (type == FTYPE_LNG) ? 'x' :
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((type == FTYPE_INT) ? 'i' :
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((type == FTYPE_SNG) ? 's' :
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((type == FTYPE_DBL) ? 'd' :
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((type == FTYPE_EXT) ? 'q' : '?')))),
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rd));
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fs->fs_regs[rd] = space[0];
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if (type >= FTYPE_DBL || type == FTYPE_LNG) {
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fs->fs_regs[rd + 1] = space[1];
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu_explode.c,v 1.6 2001/12/04 00:05:04 darrenr Exp $ */
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/* $NetBSD: fpu_explode.c,v 1.7 2002/01/19 03:02:34 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -307,6 +307,12 @@ fpu_explode(fe, fp, type, reg)
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((type == FTYPE_DBL) ? 'd' :
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((type == FTYPE_EXT) ? 'q' : '?')))),
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reg));
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#ifdef DEBUG
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if (fpe_debug & FPE_REG) {
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if (type == FTYPE_INT) printf("%d ", s);
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if (type == FTYPE_LNG) printf("%ld ", l);
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}
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#endif
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DUMPFPN(FPE_REG, fp);
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DPRINTF(FPE_REG, ("\n"));
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu_implode.c,v 1.9 2001/12/04 00:05:05 darrenr Exp $ */
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/* $NetBSD: fpu_implode.c,v 1.10 2002/01/19 03:02:34 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -279,7 +279,9 @@ fpu_ftox(fe, fp, res)
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i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
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if (i >= ((u_int64_t)0x8000000000000000LL + sign))
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break;
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return (sign ? -i : i);
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if (sign) i = -i;
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res[1] = (int)i;
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return (i>>32);
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default: /* Inf, qNaN, sNaN */
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break;
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@ -507,6 +509,10 @@ fpu_implode(fe, fp, type, space)
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register u_int *space;
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{
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DPRINTF(FPE_REG, ("\n imploding: "));
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DUMPFPN(FPE_REG, fp);
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DPRINTF(FPE_REG, ("\n"));
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switch (type) {
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#ifdef SUN4U
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