* Clean up after briggs@ changes to support bus_dma.
* Add support for reading sMemory resources from nubus cards.
* Add support for old cards with only the board rsrc (NatSemi NB-GPIB, e.g.)
* Add a few more card identifiers.
into a strange failure mode if we do it with disabled interrupt. When
(re-)enabling interrupts reset transmitter and receiver and clear any
pending state.
cache mode. Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).
not pre-load the chip's Tx buffer, but instead waits for the Tx Ready
interrupt to transmit the first chunk of data.
* On the IOP310, set COM_HW_NO_TXPRELOAD, rather than COM_HW_TXFIFO_DISABLE.
This solves the "UART hangs" problem on the Npwr in a nicer way (i.e. we
get to use the FIFO, whee). The COM_HW_NO_TXPRELOAD happens to match the
Linux 16550 driver's Tx algorithm, and the "UART hang" was never observed
on the Npwr running Linux.
Eventually, we might want to eliminate the COM_HW_NO_TXPRELOAD, and simply
always use its algorithm. But it should be tested on more 16x50 variants
before we do that.
Kudos to Valeriy Ushakov <uwe@netbsd.org> for pointing out this solution
(which also happens to fix the stray UART interrupt issue on the Krups
Javastation), and to Allen Briggs <briggs@netbsd.org> for experimenting
with various methods of fixing this.
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.
Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.
when SA_SIGINFO is used. The IRIX process will hence find the expected
information using the third argument of the signal handler.
We do not provide code and siginfo yet.
Note: The code is written a little more cruftily than it should be. It's also
only tested on the OSB4. I'm not sure it even makes sense to have support for
`native' mode, but I put it in just in case.
This was tested using a custom INSTALL kernel. The current one is >4Mb
which the cats firmware can't currently boot. We need to decide what
needs to be removed from INSTALL.
are used- didn't make a difference, but hey...
Put in commented out GFF_ID code- for use in future attempts to search
the fabric- this probably has to go thru the management server path.
Don't whine about handles we can't find if these are aborted commands
(we know we can't find the handles because we destroy handles after
a successful mailbox abort- we don't wait for the F/W to decide whether
it wants to return a status IOCB after this happens).
read/write-allocate line allocation policy.
On the i80321, this improves nearly every lmbench benchmark, dramatically
so the ones that are sensitive to memory bandwidth (100-300% improvement
for these).
cache, as well. The mini-data cache is 2-way, so src and dst won't
clobber each other, and the smallness of the cache doesn't matter,
since we access each page once sequentially.
While we still have to do the initial clean of the source page, this
saves another 4K of main D$ pollution, and also means we don't have
to do 2 cache passes after the copy is complete (i.e. we can skip the
invalidation of the source page in the main cache, since it's no longer
there).
vs. XScale. Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.
This significantly improves every test in lmbench.
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).
the data transfer. This is mandatory for data out commands (although none are
used for now), and not forbiddend for data in commands. Also record if we
did transfers any data.
May solve kern/16159 by making the probe more robust in face of fake identify.
L1_C_PROTO_xscale; while they are supposed to be set to 1 on generic
ARM MMUs (according to the SA-110 and ARM920T manuals), they are listed
as "should be zero" in the i80200 manual.
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).
Define abstract PTE bit defintions for each MMU class. If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class. Otherwise we indirect through
varaibles set up via set_cpufuncs().
XXX The XScale bits are currently the same as the generic bits. Baby steps.
after setting up the prom-based console. If more than one cpu class
is enabled, the wbflush() handler (needed indirectly by com.c) won't
be set up.
- Purge some old pmax mcclock-based code.
- Remove a '#if 1/#endif' pair.
- Use the CPU count register for more accurate microtime (from
sbmips) and delay (based on an evbmips delay function) functions.
- Schedule the next hardclock interrupt more accurately (from
an sgimips patch by Rafal Boni). Clock drift on one board is
now ~7ppm instead of ~330ppm.
- Purge old pmax-based mcclock code.
- Correctly round off some clock-derived variable calculations.
XXX: Some of this code should be migrated to sys/arch/mips.
for the same purpose (ignoring invalid interrupts).
For cards that are not able to stop all interrupts (or we don't know a way
to do that in software, at least) run the clearirq callback even when
ignoring an interrupt because we are not enabled. Otherwise the card would
stop interrupting.
Reserve a driver specific callout handle and an int value in the generic
isic_softc to allow card drivers to implement fancy blinkenlights.
It improves playing/recording quality greatly
and it was almost done by Yosuke Sugahara <penta@fuchu.or.jp>.
Thanks a lot!
Add support of slinear8, slinear16_le, slinear16_be.
do not have ARP configured.
This can be caused by configurations including bridge, ppppoe or vlan but
no ethernet interfaces - which does not make sense. We should add a way
to config(8) to issue this kind of warnings.
pcmcia cards. Now that pcmcia attachements properly handle the activate
callback, this is no longer needed (and is suspect to cause completely
unrelated problems.)
count them when reading the NIC counters - it doubles the count. Read the
NIC counters to prevent counter overflow interrupts, but don't add them to
the interface counters. Don't bother reading the upper counts because they
are just latched when reading the totals.
Fixes final part of PR#11549.
on the following PRO/100 chips:
* i82558 step A4
* i82558 step B0
* i82559 step A0
* i82559S step A
* i82550
* i82550 step C
The interrupt delay is configurable on all microcodable chips. The
maximum "bundle" size (packet count) is configurable on all but the
i82558.
The microcode is enabled by setting IFF_LINK0 on the interface.
Derived from code in FreeBSD.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in
arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c
thorpej