ends for irq_claim() and irq_release() that will allocate and free
memory for the irqhandler structure.
Added an irqblock array that provides a quick reference to all the
interrupts that should be blocked when a particular interrupt is
received. The irq_claim() and irq_release() functions now update the
irqblock array.
Impelemented a fix for kernel locks when opening the serial post :
Revisions A->D of the SMC FDC37GT665 Peripherial controller have
a bug in the serial port that is triggered if the FIFO is enabled
while there is a byte in the rx data register resulting in the
rx ready bit being permenantly set.
podule space.
Fixed a bug in the reading of bytes from network slot cards that prevented
the correct reading of the network slot ROM description.
config code now allows duplicable devices to be attached.
on indirect-config busses a (permanent) softc that they could share
between 'match' and 'attach' routines:
Define __BROKEN_INDIRECT_CONFIG so that old autoconfiguration
interfaces are used, until drivers are converted to use the new
interfaces (actually, converted back to use the _older_ interfaces)
which prohibit indirect configuration devices from receiving a softc
in their match routine that they can share with their attach routine.
Lets users over-ride with makeoptions COPTS="..." in kernel config files.
Leave `mandatory' flags (like -msoft-float which on m68k enforces no
FP in kernel) in CFLAGS.
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
a podulebus.
Make sure the podulebus driver conforms to the Acorn expansion card
specification:
- Probe the podule bus using sync access cycles rather than slow access
cycles.
- Read the podulebus header/ROM using sync access cycles rather than slow
access cycles
Added support the new instructions defined in the ARM V4 Architecture
Reference manual (long multiplies, half word load and stores,
half word/byte signed loads).
Added support for the ARM810 IMB architecture defined SWIs.
Fixed bug in calculating some immediate constants.
Added support for the wfs, rfs, wfc, rfc instructions
Added support for the floating point compare instructions
Added ldf, stf, ldc and stc instructions.
Fixed mis-disassembly of some msr/mrs instructions.
The ldm and stm instructions will modify the direction identifier to
use the stack variations if the base register is r13.
code as video memory must be reserved from main memory for the display.
In addition this adds generic support for using DRAM for video memory
on all machines. All video memory accessing should use the video_memory_t
structure.
Added support for the RC7500 motherboard. The RC7500 support includes a
replacement init_arm() function. This also supports the RC7500 prom debug
monitor for debugging the kernel boot.
dumps now work so call dumpsys() following a panic.
Added support for the SA110. This mainly consists of making sure the data
cache is cleaned when appropriate and that the instruction cache is
kept in sync during the bootstrap and when signal handlers are built on
the stack.
Use a larger UND32 mode stack if we are configured for KGDB.
Remove KERNEL_PT_KSTACK references as these should have died with the
removal of double mapped kstacks eons ago.
Make sure we call doshutdownhooks() if boot is called while we are still
cold.
Cleaned up prototypes declarations.
Sorted out comment indentation.
clean and tlb flush code along with write buffer drains that are
dependant on the definition of CPU_SA110.
The memory reserved for the L1 pagetables is now wired into the memory map
during the pmap_init rather than at L1 pagetable allocation time.
The L1 pages tables are zeroed during initialisation and when they are
released rather than when they are allocated.
When searching for a free L1 page table start search at the page table
after the last one allocated rather than always starting from the first one.
Added some extra DIAGNOSTIC checks for invalidate page index numbers.
Removed some old debugging code that escaped the last clean up.
Idented comments in line with code.
The irq delivery code has been rewritten. On entry to the irq vector the
processor is switched to SVC32 mode so all interrupt routines now run
in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling
problems.
Interrupt latency times are now vastly improved for high priority interrupts.
Cleaned up calling ast() before returning to USR32 mode (don't need to
mess about with trapframe copying.
Cleaned up all the comments and sorted out their indentation.
Rewritten the soft interrupt delivery code.
Added generic ARM7500 support rather than just RC7500 support.
Added support for the SA110. This cpu does not need any register fix-ups
following a data abort.
Return valid signal code values on SEGV's. See machine/signal.h for
decoding SEGV signal codes.
required during pagemove() and vmapbuf() and vunmapbuf().
The kernel and undefined mode stack checks are now guarded with
#ifdef STACKCHECKS.
Tidied up comments.
cache needs to be cleans and the instruction and data caches need to
be invalidate along with the instruction and data tlbs when
the TTB is reloaded during a context switch.
if CPU_SA110 is defined. Cache cleaning is different on the SA110 as
the cache is a write back virtual cache and is split for data and instruction.
Also the cache and tlb control instructions use different coprocessor #15
registers.
Removed suspect FPA probing code, instead use the ARM FPE to probe the FPA.
Neatened up the FPE attachment code.
Recognise StrongARM class of cpu.
Updated the fpa instruction bounce handler to expect a 4th argument
when called on an undefined trap to match recent changes made to
undefined handlers.
Add acknowledgement records to the buffer following origin or bounding
box changes.
Removed prototype for strncmp().
Added support for switch mouse reports between absolute and relative
positions.
earlier stages of the NetBSD/arm32 development.
Added support for the architecture defined SWI's. Currently
The IMB and IMB-range architecture defined SWI's for the ARM810 are
currently recognised.
Various comments cleaned up.
Added the functions atmoic_set_bit() and atomic_clear_bit() that
can be used for setting and clearings bits atomically (need interrupts
to be turned off).
GPROF and PROFILE_ASM are defined.
Register usage has been changed to avoid using r11. This means we have
one less register to save during this function.
booting.
After assembling the post FP processing callback branch call
sync_icache() if CPU_SA110 is defined.
Return a valid signal code when raising a SIGFPE exception so
the cause of the SIGFPE can be determined.
Added the functions arm_fpe_getcontext() and arm_fpe_setcontext()
to obtain the FP context in a FPE independant form for the ptrace()
syscall.
In db_write_text() call sync_caches() after modifing the text area
if CPU_SA110 is defined.
Added a new machine command "frame" to print out a trapframe.
Trap the kernel break point instruction specifically and panic on
any other undefined instruction being executed in SVC mode.
motherboard.
Cleaned up a lot of code to match KNF.
When the device is attach the vidc refclk frequency is reported along
with the amount of video memory and the type.
go wrong when console blanking occurs while X is running.
The blanktime ioctl now allows blanking times to be set, force
immediate blanking or diable blanking on a per virtual console basis.
Updated the console version number to revision D.
number field and an core identity string pointer.
Labels are now defined for all the entry points in the core header
structure so that the linker can relocate the branches to the core.
The core entry points are now branch instructions relative to the
start of the core so the address of the core function does not have to
be calcuated are call time.
Define the two new fields added to the FPE core header in
the arm_fpe_mod_hdr_t structure.
Added prototypes for arm_fpe_getcontext() and arm_fpe_setcontext().
Updated the prototypes for arm_fpe_core_loadcontext() and
arm_fpe_core_savecontext() to pass a fp_context_frame pointer.
CPU_SA110 and CPU_LATE_ABORT.
Updated the CLKF_INTR() macro for changes made to the interrupt system.
Updated some of the CPU ID codes.
Added the CPU ID for the ARM8.
This is for an Acorn A7000 machine with an ARM7500 CPU and no VRAM.
This config should also work for other ARM7500 machines with an
architecture that matches Acorns.
Make fp_reg_t a typedef of fp_extended_precision_t.
Rename the fp_state structure to fpe_sp_state as it describes
the single precision FPE state held in the pcb and is internal to the
kernel.
Define a new fp_state structure that is for user access to the fp
state (e.g. via ptrace()).
the AMD AM53CF94 Enhanced SCSI Controller. The code is based on the
SFAS216 driver as these chips are very similar. There are several
differences but more will follow.
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