now uses the DMACSR_READ bit and no longer keeps _nd_dmadir in softc
unified transfer cleanup code, now in routine next_dma_finish_xfer()
fixed bounds checking on registers after transfer.
removed checking for bus errors since the bit is always set on some nexts
(specifically, on mourning, a 25mhz 68040 mono slab)
fixed a couple of dma bugs involving chaining dma buffers.
DMACSR_READ is now a CSR status bit which can be used to know if current transfer is
from cpu to device.
the old DMACSR_READ bit is renamed DMACSR_SETREAD. This is a control bit that tells
the dma transfer to be from cpu to device.
return 0 instead of EINVAL. In this case, there will only be one media
type, and the upper-level if_media code will ensure that the user is
setting to that type.
This matches changes Jason made a while back to sys/dev/ic/lance.c
managed pages, into KVA space. Since the pages are managed, we should
use pmap_enter(), not pmap_kenter_pa().
Also, when entering the mappings, enter with an access_type of
VM_PROT_READ | VM_PROT_WRITE. We do this for a couple of reasons:
(1) On systems that have H/W mod/ref attributes, the hardware
may not be able to track mod/ref done by a bus master.
(2) On systems that have to do mod/ref emulation, this prevents
a mod/ref page fault from potentially happening while in an
interrupt context, which can be problematic.
This latter change is fairly important if we ever want to be able to
transfer DMA-safe memory pages to anonymous memory objects; we will need
to know that the pages are modified, or else data could be lost!
Note that while the pages are unowned (i.e. "just DMA-safe memory pages"),
they won't consume any swap resources, as the mappings are wired, and
the pages aren't on the active or inactive queues.
directly, call the function pointer (*if_input)(ifp, m). The input routine
expects the packet header to be at the head of the packet, and will adjust
as necessary. Privatize the layer 2 input and output routines, allowing
*_ifattach() to set them up as appropriate.
* Map the message buffer with access_type = VM_PROT_READ|VM_PROT_WRITE `just
because'.
* Map the file system buffers with access_type = VM_PROT_READ|VM_PROT_WRITE to
avoid possible problems with pagemove().
* Do not use VM_PROT_EXEC with either of the above.
* Map pages for /dev/mem with access_type = prot. Also, DO NOT use
pmap_kenter() for this, as we DO NOT want to lose modification information.
* Map pages in dumpsys() with VM_PROT_READ.
* Map pages in m68k mappedcopyin()/mappedcopyout() and writeback() with
access_type = prot.
* For now, bus_dma*(), pmap_map(), vmapbuf(), and similar functions still use
access_type = 0. This should probably be revisited.
These patches include:
Added framebuffer mapping for color framebuffer to support color wscons
which is coming soon.
Renamed wskbdmap_mfii[ch] to wskbdmap_next[ch]
Changed video to be white on black instead of black on white.
Now handles and discards mouse interrupts.
Video and keyboard is now working on mono machines.
write operations appear to lose scsi interrupts and causes timeouts.
changes in this checkin include:
a nextdma bugfix causing a diagnostic check to erroneously trigger
Changed tail strategy to only use tail buffer for the minimal end slop
changed expected write dma overrun to 32 bytes.
turned on nextdma diagnostic check for dma end address since it
no longer gets triggerred by ethernet dma and helps debug scsi dma.
Added esp debugging printout and support.
a filesystem, but is not stable enough yet for general use.
increased priority of ethernet interrupts, mostly useful to aid debugging
of scsi interrupts while using an nfs disk.
added additional debugging output in the next dma driver.
perform extranneous cache flushes/purges before dma reads/ after dma writes
to aid debugging of scsi dma.
Make the initializer for BAUDLO depend on PCLK directly; it was incorrect on
some ports where PCLK is not 4.9152MHz.
XXX Is the default value actually used?
it still probes the disks ok, but is having trouble with 0xdeadbeef
in buffers read from the disk. Suspected problems with DMA alignment
and toggling the secret ninja dma control register
remove check for normal chaining interrupts and add check for combined chaining interrupts
only when used with a tail chain. This allows scsi to work for short unaligned buffers
and large aligned buffers.
This fix removes putting 0xfeedbeef in the unused restart registers.
When that was done, the machine would panic after a short while
with 0xfeedbeef in the normal dma buffer registers. A restart
cycle is probably hapenning without an interrupt or something.
Unfortunately, to get dma to work, we have to align past the end of
the buffer, which smashes other variables on the stack.
match function still disabled, as it isn't ready yet.
of DD_NEXT for regular dma transfers, and not just ethernet transmit.
Keep track of dma read/write direction and set it each time we start or
restart dma. This allows scsi to work, and doesn't appear to hinder ethernet.
drochner