minor rework of dma driver
now uses the DMACSR_READ bit and no longer keeps _nd_dmadir in softc unified transfer cleanup code, now in routine next_dma_finish_xfer() fixed bounds checking on registers after transfer. removed checking for bus errors since the bit is always set on some nexts (specifically, on mourning, a 25mhz 68040 mono slab) fixed a couple of dma bugs involving chaining dma buffers.
This commit is contained in:
dbj
parent
ec9b8358dc
commit
45ec8742b1
@ -1,4 +1,4 @@
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/* $NetBSD: nextdma.c,v 1.19 1999/08/28 09:19:05 dbj Exp $ */
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/* $NetBSD: nextdma.c,v 1.20 1999/08/29 05:56:26 dbj Exp $ */
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/*
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* Copyright (c) 1998 Darrin B. Jewell
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* All rights reserved.
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@ -71,6 +71,7 @@ void next_dma_rotate __P((struct nextdma_config *));
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void next_dma_setup_cont_regs __P((struct nextdma_config *));
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void next_dma_setup_curr_regs __P((struct nextdma_config *));
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void next_dma_finish_xfer __P((struct nextdma_config *));
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void
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nextdma_config(nd)
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@ -115,7 +116,6 @@ nextdma_init(nd)
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DPRINTF(("DMA init ipl (%ld) intr(0x%b)\n",
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NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS));
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/* @@@ should probably check and free these maps */
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nd->_nd_map = NULL;
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nd->_nd_idx = 0;
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nd->_nd_map_cont = NULL;
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@ -123,26 +123,29 @@ nextdma_init(nd)
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
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DMACSR_INITBUF | DMACSR_CLRCOMPLETE | DMACSR_RESET);
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DMACSR_RESET | DMACSR_INITBUF);
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next_dma_setup_curr_regs(nd);
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next_dma_setup_cont_regs(nd);
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#if 0 && defined(DIAGNOSTIC)
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/* Today, my computer (mourning) appears to fail this test.
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* yesterday, another NeXT (milo) didn't have this problem
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* Darrin B. Jewell <jewell@mit.edu> Mon May 25 07:53:05 1998
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*/
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#if defined(DIAGNOSTIC)
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{
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u_long state;
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state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR);
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state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR);
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#if 1
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/* mourning (a 25Mhz 68040 mono slab) appears to set BUSEXC
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* milo (a 25Mhz 68040 mono cube) didn't have this problem
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* Darrin B. Jewell <jewell@mit.edu> Mon May 25 07:53:05 1998
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*/
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state &= (DMACSR_COMPLETE | DMACSR_SUPDATE | DMACSR_ENABLE);
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#else
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state &= (DMACSR_BUSEXC | DMACSR_COMPLETE |
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DMACSR_SUPDATE | DMACSR_ENABLE);
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#endif
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if (state) {
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next_dma_print(nd);
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panic("DMA did not reset\n");
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panic("DMA did not reset");
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}
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}
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#endif
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@ -162,6 +165,8 @@ nextdma_reset(nd)
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if (nextdma_debug) next_dma_print(nd);
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#endif
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/* @@@ clean up dma maps */
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nextdma_init(nd);
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splx(s);
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}
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@ -179,22 +184,6 @@ next_dma_rotate(nd)
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DPRINTF(("DMA next_dma_rotate()\n"));
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#ifdef DIAGNOSTIC
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if (nd->_nd_map &&
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_xfer_len == 0x1234beef) {
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next_dma_print(nd);
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panic("DMA didn't set xfer length of segment");
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}
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#endif
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/* If we've reached the end of the current map, then inform
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* that we've completed that map.
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*/
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if (nd->_nd_map && ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs)) {
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if (nd->nd_completed_cb)
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(*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg);
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}
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/* Rotate the continue map into the current map */
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nd->_nd_map = nd->_nd_map_cont;
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nd->_nd_idx = nd->_nd_idx_cont;
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@ -236,95 +225,91 @@ void
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next_dma_setup_cont_regs(nd)
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struct nextdma_config *nd;
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{
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bus_addr_t dd_start;
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bus_addr_t dd_stop;
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bus_addr_t dd_saved_start;
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bus_addr_t dd_saved_stop;
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DPRINTF(("DMA next_dma_setup_regs()\n"));
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if (nd->_nd_map_cont) {
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dd_start = nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr;
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dd_stop = (nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr +
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nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len);
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if (nd->nd_intr == NEXT_I_ENETX_DMA) {
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/* Ethernet transmit needs secret magic */
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START,
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nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP,
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((nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr +
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nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len)
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+ 0x0) | 0x80000000);
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dd_stop |= 0x80000000; /* Ethernet transmit needs secret magic */
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}
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else {
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START,
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nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP,
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nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr +
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nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len);
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}
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} else {
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 0xdeadbeef);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 0xdeadbeef);
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dd_start = 0xdeadbeef;
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dd_stop = 0xdeadbeef;
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}
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#if 1 /* 0xfeedbeef in these registers leads to instability. it will
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* panic after a short while with 0xfeedbeef in the DD_START and DD_STOP
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* registers. I suspect that an unexpected hardware restart
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* is cycling the bogus values into the active registers. Until
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* that is understood, we seed these with the same as DD_START and DD_STOP
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*/
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START,
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bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START));
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP,
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bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP));
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#else
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START, 0xfeedbeef);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP, 0xfeedbeef);
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#endif
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dd_saved_start = dd_start;
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dd_saved_stop = dd_stop;
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, dd_start);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, dd_stop);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START, dd_saved_start);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP, dd_saved_stop);
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#ifdef DIAGNOSTIC
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if ((bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START) != dd_start) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP) != dd_stop) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START) != dd_saved_start) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP) != dd_saved_stop)) {
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next_dma_print(nd);
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panic("DMA failure writing to continue regs");
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}
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#endif
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}
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void
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next_dma_setup_curr_regs(nd)
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struct nextdma_config *nd;
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{
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bus_addr_t dd_next;
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bus_addr_t dd_limit;
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bus_addr_t dd_saved_next;
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bus_addr_t dd_saved_limit;
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DPRINTF(("DMA next_dma_setup_curr_regs()\n"));
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if (nd->_nd_map) {
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dd_next = nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr;
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dd_limit = (nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr +
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_len);
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if (nd->nd_intr == NEXT_I_ENETX_DMA) {
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/* Ethernet transmit needs secret magic */
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF,
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT,
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((nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr +
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_len)
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+ 0x0) | 0x80000000);
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dd_limit |= 0x80000000; /* Ethernet transmit needs secret magic */
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}
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else {
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF,
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT,
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr +
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_len);
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}
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} else {
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF,0xdeadbeef);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 0xdeadbeef);
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dd_next = 0xdeadbeef;
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dd_limit = 0xdeadbeef;
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}
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#if 1 /* See comment in next_dma_setup_cont_regs() above */
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT,
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bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF));
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT,
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bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT));
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#else
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 0xfeedbeef);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 0xfeedbeef);
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#endif
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dd_saved_next = dd_next;
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dd_saved_limit = dd_limit;
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if (nd->nd_intr == NEXT_I_ENETX_DMA) {
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF, dd_next);
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} else {
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT, dd_next);
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}
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, dd_limit);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, dd_saved_next);
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bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, dd_saved_limit);
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#ifdef DIAGNOSTIC
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if ((bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF) != dd_next) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT) != dd_next) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) != dd_limit) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT) != dd_saved_next) ||
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(bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT) != dd_saved_limit)) {
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next_dma_print(nd);
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panic("DMA failure writing to current regs");
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}
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#endif
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}
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@ -359,9 +344,12 @@ next_dma_print(nd)
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dd_saved_start = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START);
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dd_saved_stop = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP);
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/* NDMAP is Next DMA Print (really!) */
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printf("NDMAP: *intrstat = 0x%b\n",
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(*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS);
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printf("NDMAP: *intrmask = 0x%b\n",
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(*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS);
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printf("NDMAP: nd->_nd_dmadir = 0x%08x\n",nd->_nd_dmadir);
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/* NDMAP is Next DMA Print (really!) */
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if (nd->_nd_map) {
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printf("NDMAP: nd->_nd_map->dm_mapsize = %d\n",
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@ -408,6 +396,47 @@ next_dma_print(nd)
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}
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/****************************************************************/
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void
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next_dma_finish_xfer(nd)
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struct nextdma_config *nd;
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{
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bus_addr_t onext;
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bus_addr_t olimit;
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bus_addr_t slimit;
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onext = nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr;
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olimit = onext + nd->_nd_map->dm_segs[nd->_nd_idx].ds_len;
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if ((nd->_nd_map_cont == NULL) && (nd->_nd_idx+1 == nd->_nd_map->dm_nsegs)) {
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slimit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT);
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} else {
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slimit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT);
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}
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if (nd->nd_intr == NEXT_I_ENETX_DMA) {
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slimit &= ~0x80000000;
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}
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#ifdef DIAGNOSTIC
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if ((slimit < onext) || (slimit > olimit)) {
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next_dma_print(nd);
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panic("DMA: Unexpected registers in finish_xfer\n");
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}
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#endif
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_xfer_len = slimit-onext;
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/* If we've reached the end of the current map, then inform
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* that we've completed that map.
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*/
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if (nd->_nd_map && ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs)) {
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if (nd->nd_completed_cb)
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(*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg);
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}
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nd->_nd_map = 0;
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nd->_nd_idx = 0;
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}
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int
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nextdma_intr(arg)
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@ -437,78 +466,24 @@ nextdma_intr(arg)
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int state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR);
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#ifdef DIAGNOSTIC
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if (!(state & DMACSR_COMPLETE)) {
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if ((!(state & DMACSR_COMPLETE)) || (state & DMACSR_SUPDATE)) {
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next_dma_print(nd);
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printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
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panic("DMA ipl (%ld) intr(0x%b), DMACSR_COMPLETE not set in intr\n",
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NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS);
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panic("DMA Unexpected dma state in interrupt (0x%b)",state,DMACSR_BITS);
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}
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#endif
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#if 0 /* This bit gets set sometimes & I don't know why. */
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#ifdef DIAGNOSTIC
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if (state & DMACSR_BUSEXC) {
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next_dma_print(nd);
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printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
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panic("DMA ipl (%ld) intr(0x%b), DMACSR_COMPLETE not set in intr\n",
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NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS);
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}
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#endif
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#endif
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next_dma_finish_xfer(nd);
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/* Check to see if we are expecting dma to shut down */
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if (!nd->_nd_map_cont) {
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if ((nd->_nd_map == NULL) && (nd->_nd_map_cont == NULL)) {
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#ifdef DIAGNOSTIC
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#if 1 /* Sometimes the DMA registers have totally bogus values when read.
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* Until that's understood, we skip this check
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*/
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/* Verify that the registers are laid out as expected */
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{
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bus_addr_t next;
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bus_addr_t limit;
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bus_addr_t expected_limit;
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expected_limit =
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr +
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nd->_nd_map->dm_segs[nd->_nd_idx].ds_len;
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if (nd->nd_intr == NEXT_I_ENETX_DMA) {
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next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF);
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limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) & ~0x80000000;
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}
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else {
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next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT);
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limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT);
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}
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if ((next != limit) || (limit != expected_limit)) {
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next_dma_print(nd);
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printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
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panic("unexpected DMA limit at shutdown 0x%08x, 0x%08x, 0x%08x",
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next,limit,expected_limit);
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}
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}
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#endif
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#endif
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#if 1
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#ifdef DIAGNOSTIC
|
||||
if (state & (DMACSR_SUPDATE|DMACSR_ENABLE)) {
|
||||
if (state & DMACSR_ENABLE) {
|
||||
next_dma_print(nd);
|
||||
panic("DMA: unexpected bits set in DMA state at shutdown (0x%b)\n",
|
||||
panic("DMA: unexpected DMA state at shutdown (0x%b)\n",
|
||||
state,DMACSR_BITS);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs) {
|
||||
if (nd->nd_completed_cb)
|
||||
(*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg);
|
||||
}
|
||||
nd->_nd_map = 0;
|
||||
nd->_nd_idx = 0;
|
||||
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_CLRCOMPLETE | DMACSR_RESET);
|
||||
|
||||
@ -518,106 +493,45 @@ nextdma_intr(arg)
|
||||
return(1);
|
||||
}
|
||||
|
||||
#if 0
|
||||
#ifdef DIAGNOSTIC
|
||||
if (!(state & DMACSR_SUPDATE)) {
|
||||
next_dma_print(nd);
|
||||
printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
|
||||
panic("SUPDATE not set with continuing DMA");
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Check that the buffer we are interrupted for is the one we expect.
|
||||
* Shorten the buffer if the dma completed with a short buffer
|
||||
*/
|
||||
{
|
||||
bus_addr_t next;
|
||||
bus_addr_t limit;
|
||||
bus_addr_t expected_next;
|
||||
bus_addr_t expected_limit;
|
||||
|
||||
expected_next = nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr;
|
||||
expected_limit = expected_next + nd->_nd_map->dm_segs[nd->_nd_idx].ds_len;
|
||||
|
||||
#if 0 /* for some unknown reason, somtimes DD_SAVED_NEXT has value from
|
||||
* nd->_nd_map and sometimes it has value from nd->_nd_map_cont.
|
||||
* Somtimes, it has a completely different unknown value.
|
||||
* Until that's understood, we won't sanity check the expected_next value.
|
||||
*/
|
||||
next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT);
|
||||
#else
|
||||
next = expected_next;
|
||||
#endif
|
||||
limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT);
|
||||
|
||||
if (nd->nd_intr == NEXT_I_ENETX_DMA) {
|
||||
limit &= ~0x80000000;
|
||||
}
|
||||
|
||||
if ((limit-next < 0) ||
|
||||
(limit-next >= expected_limit-expected_next)) {
|
||||
#ifdef DIAGNOSTIC
|
||||
#if 0 /* Sometimes, (under load I think) even DD_SAVED_LIMIT has
|
||||
* a bogus value. Until that's understood, we don't panic
|
||||
* here.
|
||||
*/
|
||||
next_dma_print(nd);
|
||||
printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
|
||||
panic("Unexpected saved registers values.");
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* @@@ we pretend the entire buffer transferred ok.
|
||||
* we might consider throwing away this transfer instead
|
||||
*/
|
||||
nd->_nd_map->dm_segs[nd->_nd_idx].ds_xfer_len = expected_limit-expected_next;
|
||||
} else {
|
||||
nd->_nd_map->dm_segs[nd->_nd_idx].ds_xfer_len = limit-next;
|
||||
expected_limit = expected_next + (limit-next);
|
||||
}
|
||||
|
||||
#if 0 /* these checks are turned off until the above mentioned weirdness is fixed. */
|
||||
#ifdef DIAGNOSTIC
|
||||
if (next != expected_next) {
|
||||
next_dma_print(nd);
|
||||
printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
|
||||
panic("unexpected DMA next buffer in interrupt (found 0x%08x, expected 0x%08x)",
|
||||
next,expected_next);
|
||||
}
|
||||
if (limit != expected_limit) {
|
||||
next_dma_print(nd);
|
||||
printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS);
|
||||
panic("unexpected DMA limit buffer in interrupt (found 0x%08x, expected 0x%08x)",
|
||||
limit,expected_limit);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
next_dma_rotate(nd);
|
||||
next_dma_setup_cont_regs(nd);
|
||||
|
||||
if (!(state & DMACSR_ENABLE)) {
|
||||
{
|
||||
u_long dmadir; /* DMACSR_SETREAD or DMACSR_SETWRITE */
|
||||
|
||||
DPRINTF(("Unexpected DMA shutdown, restarting\n"));
|
||||
|
||||
if (nd->_nd_map_cont) {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_SETSUPDATE | DMACSR_SETENABLE | nd->_nd_dmadir);
|
||||
if (state & DMACSR_READ) {
|
||||
dmadir = DMACSR_SETREAD;
|
||||
} else {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_SETENABLE | nd->_nd_dmadir);
|
||||
dmadir = DMACSR_SETWRITE;
|
||||
}
|
||||
|
||||
} else {
|
||||
if (state & DMACSR_ENABLE) {
|
||||
|
||||
if ((nd->_nd_map_cont == NULL) && (nd->_nd_idx+1 == nd->_nd_map->dm_nsegs)) {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_CLRCOMPLETE | dmadir);
|
||||
} else {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_CLRCOMPLETE | dmadir | DMACSR_SETSUPDATE);
|
||||
}
|
||||
|
||||
if (nd->_nd_map_cont) {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_SETSUPDATE | DMACSR_CLRCOMPLETE | nd->_nd_dmadir);
|
||||
} else {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_CLRCOMPLETE | nd->_nd_dmadir);
|
||||
|
||||
#if (defined(ND_DEBUG))
|
||||
if (nextdma_debug) next_dma_print(nd);
|
||||
#endif
|
||||
#if 0 && defined(DIAGNOSTIC)
|
||||
printf("DMA: Unexpected shutdown, restarting intr(0x%b)\n",
|
||||
NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS);
|
||||
#endif
|
||||
|
||||
if ((nd->_nd_map_cont == NULL) && (nd->_nd_idx+1 == nd->_nd_map->dm_nsegs)) {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_CLRCOMPLETE | dmadir | DMACSR_SETENABLE);
|
||||
} else {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_CLRCOMPLETE | dmadir | DMACSR_SETSUPDATE | DMACSR_SETENABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -676,8 +590,6 @@ nextdma_start(nd, dmadir)
|
||||
}
|
||||
#endif
|
||||
|
||||
nd->_nd_dmadir = dmadir;
|
||||
|
||||
/* preload both the current and the continue maps */
|
||||
next_dma_rotate(nd);
|
||||
|
||||
@ -690,12 +602,12 @@ nextdma_start(nd, dmadir)
|
||||
next_dma_rotate(nd);
|
||||
|
||||
DPRINTF(("DMA initiating DMA %s of %d segments on intr(0x%b)\n",
|
||||
(nd->_nd_dmadir == DMACSR_SETREAD ? "read" : "write"), nd->_nd_map->dm_nsegs,
|
||||
(dmadir == DMACSR_SETREAD ? "read" : "write"), nd->_nd_map->dm_nsegs,
|
||||
NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS));
|
||||
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0);
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_INITBUF | DMACSR_RESET | nd->_nd_dmadir);
|
||||
DMACSR_INITBUF | DMACSR_RESET | dmadir);
|
||||
|
||||
next_dma_setup_curr_regs(nd);
|
||||
next_dma_setup_cont_regs(nd);
|
||||
@ -704,12 +616,11 @@ nextdma_start(nd, dmadir)
|
||||
if (nextdma_debug) next_dma_print(nd);
|
||||
#endif
|
||||
|
||||
if (nd->_nd_map_cont) {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_SETSUPDATE | DMACSR_SETENABLE | nd->_nd_dmadir);
|
||||
} else {
|
||||
if ((nd->_nd_map_cont == NULL) && (nd->_nd_idx+1 == nd->_nd_map->dm_nsegs)) {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_SETENABLE | nd->_nd_dmadir);
|
||||
DMACSR_SETENABLE | dmadir);
|
||||
} else {
|
||||
bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR,
|
||||
DMACSR_SETSUPDATE | DMACSR_SETENABLE | dmadir);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: nextdmavar.h,v 1.8 1999/08/28 09:19:06 dbj Exp $ */
|
||||
/* $NetBSD: nextdmavar.h,v 1.9 1999/08/29 05:56:26 dbj Exp $ */
|
||||
/*
|
||||
* Copyright (c) 1998 Darrin B. Jewell
|
||||
* All rights reserved.
|
||||
@ -52,8 +52,6 @@ struct nextdma_config {
|
||||
int _nd_idx; /* idx of segment currently in dd_next */
|
||||
bus_dmamap_t _nd_map_cont; /* map needed to continue DMA */
|
||||
int _nd_idx_cont; /* segment index to continue DMA */
|
||||
|
||||
int _nd_dmadir; /* DMACSR_SETREAD or DMACSR_SETWRITE */
|
||||
};
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user